| Table 1. SignalTap II Features and Benefits |
| Feature |
Benefit |
| Multiple Logic Analyzers in a Single Device |
Supports multiple clock domains in a single device. |
| Multiple Logic Analyzers in Multiple Devices in a Single JTAG Chain |
Allows multiple devices with multiple clock domains to be analyzed. |
State-Based Trigger Flow  |
Enables easier hardware verification by allowing you to specify any custom triggering flow sequence, including multi-way branches, cyclical data flow, and multiple acquisition end-event conditions. User-specified conditional statements make more efficient use of the memory buffers. You can define a different trigger event for each segment, specify the condition to stop the acquisition, and define a trigger position within a segment. |
| Up to 10 Basic or Advanced Trigger Levels for Each Analyzer |
Allows for more complex data capture commands to be given to the logic analyzer, providing greater accuracy and problem isolation. Version 4.1 adds support for event counter trigger conditions. |
| Flexible Buffer Acquisition Modes |
Each trigger can be set up to sample at different ranges relative to the triggering event, in circular or segmented modes, which allows more accurate data collection. |
| Up to 1,024 Channels in Each Device |
Enables sampling many signals and wide bus structures, and allows for a great deal of data collection to locate problems. |
| Up to 128K Samples in Each Device |
Provides sufficient capacity for any practical application. |
| Clock Support Over 200 MHz |
Allows for sampling of design data at system frequency. |
| Ability to Incrementally Add Nodes, Change Signal Selection, and Change Trigger Conditions Without a Full Recompilation |
Allows you to change which nodes are monitored without a full design recompilation. |
| Lock Mode to Prevent Recompilations |
Prevents SignalTap II configuration changes that require a design recompilation. |
| Power-Up Auto Trigger |
Allows you to perform on-chip debugging immediately after device configuration. |
| No-Cost, Stand-Alone Viewer |
Allows easy deployment of in-system logic analysis capabilities to multiple lab locations or field service personnel. |
| Mnemonic and Radix Tables |
Labels signals with true signal names from software source to assist in identification of problem source. |
| Multiple Bus Display Formats |
Makes viewing and analyzing buses easier (now includes bar chart and line chart display options for captured data). |
| Export Data in Multiple File Formats |
Allows other verification tools to be used to analyze captured data. |
| Resource Usage Estimator |
Provides estimate of logic and memory device resources used by SignalTap II embedded logic analyzer configurations. |
| Auto Detection of Devices in JTAG Chain |
Confirms connection to device before attempting to initiate data capture. |
| Auto Detection of Programming Hardware |
Confirms connection to device before attempting to initiate data capture. |
| Ability to Print Waveforms |
Prints captured waveforms for reporting. |
| Vendor-Independent Application Program Interface (API) for Source-Level Debugging Tools |
Allows third-party software to utilize SignalTap II resources. |
| Native SignalTap II MEX Function Included with MATLAB Interface |
Allows SignalTap II to perform real-time, high-speed data acquisitions and presents the data in the native MATLAB matrix format. |
| User-Friendly Interface |
Uses status monitors to guide you through operation. |
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