Quartus II TimeQuest Timing Analyzer: SDC-Based FPGA Timing Analysis
As FPGAs become denser, faster, and less expensive, they become the target of a broader range of designs and applications. This trend is pushing the limits of traditional FPGA timing analysis tools that are struggling to meet different levels of design complexity. The goal is to provide a timing analysis tool that meets the needs of basic and advanced timing analysis requirements. The new, easy-to-use TimeQuest timing analyzer offers a complete GUI environment for creating constraints and timing reports, as well as ASIC-strength features including native support for Synopsys Design Constraints (SDC) format and full scripting capabilities.
TimeQuest Timing Analyzer "At a Glance"
From basic timing analysis requirements to advanced timing analysis requirements, the TimeQuest timing analyzer offers significant advantages compared to the classic timing analyzer:
- Basic Timing Analysis Requirements—The TimeQuest timing analyzer offers an easy-to-use GUI to create constraints and view timing reports. By using the TimeQuest timing analyzer, you do not have to learn SDC or any constraint format and it offers the same flow as the classic timing analyzer.
- Intermediate Timing Analysis Requirements—The TimeQuest timing analyzer offers native support for SDC format. The TimeQuest timing analyzer makes it easy to learn SDC on-the-fly and offers on-demand, interactive reporting capabilities.
- Advanced Timing Requirements—The TimeQuest timing analyzer offers full scripting capability to create constraints, create reports, and to manage the timing analysis flow. The TimeQuest timing analyzer supports advanced reports and the ability to create custom reports.
Who Should use the TimeQuest Timing Analyzer
Altera recommends using the TimeQuest timing analyzer for all new Altera® designs on 180-nm, 90-nm, and 65-nm process nodes. If you have basic timing requirements, you can take advantage of the easy-to-use dialog boxes and pre-canned reports to close timing quicker. If you have intermediate and advanced timing requirements, you can close timing faster with a timing analysis tool that has native SDC support.
Quartus II Support
The TimeQuest timing analyzer enables you to easily create, manage, and analyze timing constraints, and to quickly perform timing verification. The TimeQuest timing analyzer is available in the Quartus® II Subscription Edition software version 6.0 and later, as well as the Quartus II Web Edition software version 6.1 and later.
Device Support
The TimeQuest timing analyzer supports the following Altera devices:
- High-density Stratix® series FPGAs
- HardCopy® II structured ASICs
- Low-cost Cyclone® series FPGAs
- MAX® II CPLDs
Key Benefits and Features
Benefits for using the TimeQuest timing analyzer include:
- Easy-to-Use GUI—The TimeQuest timing analyzer provides an easy-to-use GUI and interactive reporting for analyzing timing.
- Native Support for Industry-Standard SDC Format—You can leverage a powerful industry-standard timing constraint format and achieve a higher degree of productivity using and re-using the SDC format and tool command language (Tcl)-based scripts.
- Support for Complex Clocking Schemes—The SDC format provides a simpler yet more powerful timing format for faster, easier description and analysis of advanced design constructs (DDR and other source-synchronous protocols, multiplexed clocks etc.)
- Improved Performance—The TimeQuest timing analyzer models timing behavior (e.g., rise/fall time modeling) more precisely than the classic timing analyzer. Performance for Hardcopy II and 65-nm device families can improve by up to 3-5 percent.
- Easier ASIC Prototyping—The Timequest timing analyzer allows for easy migration of SDC constraints for ASIC and HardCopy designs accelerating ASIC prototyping.
Native SDC Support
Native SDC support provides all the constraints controls that you require when performing timing analysis of FPGA-based designs, thus increasing productivity. Coupled with Tcl, native SDC support automates repetitive timing analysis tasks so you can focus on the optimization of timing critical paths.
Other benefits provided by native SDC support in the TimeQuest timing analyzer include:
- Industry-standard timing constraints format
- Investment in SDC adoption for timing analysis is safe, since the format is supported by the majority of EDA vendors
- More efficient specification and fine-tune control of complex timing relationships among signals. SDC is the ideal format for constraining high-speed, source-synchronous interfaces (such as DDR and DDR2) and clock multiplexing design structures
- Reuse of SDC constraints for ASIC-to-FPGA migration. Refer to the SDC & TimeQuest API Reference Manual (PDF) for a complete list of the natively supported SDC constructs
Fast On-Demand and Interactive Data Reporting
If you are already proficient with the SDC format and Tcl scripting, you can drive the TimeQuest timing analyzer and report functionality via its fast Tcl interface. The same advanced functionality is also readily available via the TimeQuest timing analyzer GUI.
The TimeQuest timing analyzer GUI provides an intuitive yet powerful way to perform timing analysis and includes:
Applications
For more information about how to perform the timing analysis of designs containing multiplexed clock structures and source-synchronous interfaces using the SDC format with the Quartus II TimeQuest timing analyzer, refer to the TimeQuest Timing Analyzer: Native SDC Support for Timing Analysis of FPGA-Based Designs White Paper (PDF) and to the TimeQuest Timing Analyzer (PDF) chapter in volume 3 of the Quartus II Handbook.
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