TimeQuest Timing Analyzer for Classic FPGA Timing Verification
The new easy-to-use TimeQuest timing analyzer offers a complete GUI environment for creating constraints and timing reports, as well as ASIC-strength features that include native support for Synopsys Design Constraints (SDC) format and full scripting capabilities. The TimeQuest timing analyzer is the default timing analyzer for 65-nm devices and future process technologies. Altera continues to include the classic timing analyzer with the Quartus® II software for 65-nm and earlier designs.
Who Should use the TimeQuest Timing Analyzer
Altera recommends using the TimeQuest timing analyzer for all new Altera® designs on the 180-nm, 90-nm, and 65-nm process nodes. In addtition, the TimeQuest timing analyzer is recommended for all designs that are being migrated to 65-nm devices.
Note: Designs that include memory interfaces (DDR, DDR II etc.) that are migrating to 65-nm devices are required to use the TimeQuest timing analyzer rather than the classic timing analyzer.
Why use the TimeQuest Timing Analyzer vs. the Classic Timing Analyzer
From basic timing analysis requirements to advanced timing analysis requirements, the TimeQuest timing analyzer offers significant advantages compared to the classic timing analyzer.
- Basic Timing Analysis Requirements—The TimeQuest timing analyzer offers an easy-to-use GUI to create constraints and view timing reports. By using the TimeQuest timing analyzer, you do not have to learn SDC or any constraint format and it offers the same flow (including default clock constraint and fMAX report) as the classic timing analyzer. In addition, the TimeQuest timing analyzer offers more constraint dialog boxes than the classic timing analyzer to accelerate constraint creation.
- Intermediate Timing Analysis Requirements—The TimeQuest timing analyzer offers native support for SDC format. The TimeQuest timing analyzer makes it easy to learn SDC on-the-fly and offers on-demand, interactive reporting capabilities. The TimeQuest timing analyzer models timing behavior (e.g., rise/fall time modeling) more precisely than the classic timing analyzer. Performance for Hardcopy® II and 65-nm device families can improve by up to 3-5 percent.
- Advanced Timing Requirements—The TimeQuest timing analyzer offers full scripting capability to create constraints, create reports, and to mange the timing analysis flow. The TimeQuest timing analyzer supports advanced (though-support) reports and the ability to create custom reports. The TimeQuest timing analyzer makes it easier to constrain source-sychronous interfaces (DDR, DDR2). In addition, TimeQuest with native SDC support makes it easier to prototype your ASIC or move to a Hardcopy Structured ASIC.
For more information on switching to the TimeQuest timing analyzer, refer to the Switching to the TimeQuest Timing Analyzer (PDF) chapter in volume 3 of the Quartus II Handbook.
Conversion Utility
The TimeQuest timing analyzer includes a conversion utility to help convert existing classic timing assignments present in the Quartus II Settings File (QSF) to SDC constraints in a SDC file. To run the conversion utility, select Generate SDC file from QSF in the TimeQuest Constraints menu. The utility uses data from the project report database, so the design should be already compiled prior to using the utility. During the conversion process, the utility verifies a number of settings and converts most classic timing assignments into the SDC format. You should inspect the result of the automatic conversion and include any additional SDC timing constraints needed to perform the timing analysis. It is important to understand the differences between the classic and TimeQuest timing analyzers. Differences in slack reported by the TimeQuest timing analyzer occur because the TimeQuest timing analyzer performs a cross-clock domain path analysis by default.
For more information regarding the conversion utility, see the Switching to the TimeQuest Timing Analyzer (PDF) chapter in volume 3 of the Quartus II Handbook.
Evaluating the TimeQuest Timing Analyzer
To evaluate the TimeQuest timing analyzer:
- Compile your design with the classic timing analyzer.
- Run the TimeQuest timing analyzer from the Tools menu.
- Run the conversion utility and inspect the results.
- Include any additional SDC timing constraints.
- Evaluate the reporting capabilities of the TimeQuest timing analyzer.
The Switching to the TimeQuest Timing Analyzer (PDF) chapter in volume 3 of the Quartus II Handbook contains more information regarding the conversion process.
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