What's New in Quartus II Software v8.0
Quartus® II software version 8.0 delivers unprecedented performance and productivity for high-density FPGAs and is the first FPGA vendor software to support 40-nm devices with Stratix® IV FPGAs. Version 8.0 further extends Altera’s leadership position in performance and productivity by delivering, on average, a full two speed grade advantage and 3x faster compile times for high-density devices when compared to the nearest competitor. With new productivity features and support for Stratix IV FPGAs, version 8.0 reinforces Altera’s commitment in delivering the #1 performance and productivity to FPGA designers.
Stratix IV FPGA Support
Quartus II software version 8.0 demonstrates distinct performance and productivity advantages with Stratix IV FPGAs. Enhancements to the advanced place-and-route algorithms, TimeQuest timing analyzer, and PowerPlay power technology in combination with the Stratix IV FPGA architecture enable designs to achieve the following benefits:
- Industry leading compilation times, on average 3x faster compile times compared to the nearest competitor
- Reduced cost and faster timing closure with industry leading performance, a two speed grade advantage compared to the nearest competitor
- Reduced cost by integrating more logic into a single FPGA with 46 percent higher logic utilization compared to the nearest competitor
- Faster power closure resulting in half the power consumption compared to the nearest competitor
Quartus II software offers complete design flow support for Stratix IV FPGAs, including:
Quartus II version 8.0 supports the following Stratix IV FPGAs:
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Stratix IV GX FPGAs, including the EP4SGX70, EP4SGX110, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 devices
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Stratix IV E FPGAs, including the EP4SE530 device
For more information on Stratix IV FPGAs, please visit the Stratix IV Device page
New Features and Enhancements
With continued focus on productivity, Quartus II software version 8.0 further reduces compilation times. Also new in Quartus II software version 8.0 is the Design Partition Planner, which enables better and easier design partitions for faster compilation times. In addition, the new Tasks window extends Quartus II software’s productivity advantage by guiding you through the Quartus II software design flow.
Enhancements in Version 8.0 Deliver Faster Compile Times
Enhancements to the advanced place-and-route algorithms deliver an additional 22 percent improvement in compile times for Stratix III FPGAs compared to the previous release, resulting in 3x faster compile times, on average, for high-density FPGAs compared to the nearest competitor. Many other enhancements have also been made to reduce compilation times, including:
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A new fast synthesis effort option that reduces Quartus II integrated synthesis time by 33 percent compared to the previous version (for more information, please refer to the Quartus II Handbook)
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Enhancements towards reducing physical synthesis times that result in 33 percent less time compared to the previous version
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Improvements focused on compilation times that deliver compilation times on Linux that are on par with Windows
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A new design partition planner that further reduces compilation times (see below)
Design Partition Planner Further Reduces Compilation Times
Introduced in version 8.0, the Design Partition Planner helps you get the most out of incremental compilation. Today’s engineers are facing longer compilation times resulting in lower design team productivity. Altera’s continuing goal is to reduce compilation times so that you are able to complete multiple design iterations within a single day. Quartus II software’s incremental compilation feature and the design partition planner enable you to reduce your compilation by up to 70 percent. The design partition planner is a graphical interface enabling you to efficiently create better partitions for your designs. Additional benefits of the incremental compilation feature are preserving design performance, and support for team-based design.
For more detailed information on the Design Partition Planner, please see the Quartus II Incremental Compilation for Hierarchical & Team-Based Design (PDF) handbook chapter.
New Tasks Window Extends Productivity Advantage
The new Tasks window is an interactive design flow console that guides you through the FPGA design flow. The Tasks window provides a list of processes, tools, and features organized in an Altera® FPGA design flow. This organization helps new users walk through Altera’s FPGA design flow and gives experienced users a simple quick way to run and open processes, tools and features.
Additional Enhancements
- Expanded SOPC Builder—New JTAG and SPI bridge components for external communication and debug with other FPGAs or host processors. SOPC Builder also delivers faster timing closure and design iterations with full support for incremental compilation and TimeQuest timing analyzer.
- Enhanced TimeQuest Timing Analysis—Faster analysis and debug with expanded reporting and enhanced cross probe capabilities.
- Faster Linux Compilation Times—Improves compilation times on Linux to be on par with compilation times on Windows.
- New Arria™ GX FPGA Features—Provides added 3.125 Gbps protocol support, including 3G Basic, Serial Lite, SDI, XAUI and CPRI, OBSAI in addition to GIGE, Serial RapidIO® (SRIO) standard and PCIe.
- Enhanced FPGA I/O Planning—Accelerates board development with added pin swapping capabilities in the Pin Planner.
- New IP Advisor—Provides design-specific guidelines and recommendations for successful use of Altera‘s PCI Express and DDR3 intellectual properties (IPs).
- DSP Builder—Reduce timing closure efforts with the new advanced block set library allowing customers to achieve 30 to 50 percent higher push button performance for a range of digital signal processing (DSP) functions without the need for manual pipelining and folding.
- IP MegaCore Library Integration—The IP MegaCore library is now integrated into the Quartus II software resulting in a more simplified download experience.
Device Support
Quartus II Subscription Edition software offers support for all Altera® devices, including all members of Altera's high-density FPGA families and HardCopy ASICs. New in Quartus II Subscription Edition software version 8.0:
- Stratix IV FPGAs—Adds first compilation support for Stratix IV GX devices.
- Stratix III FPGAs—Programming support added for the EP3SE50, EP3E260, EP3SL150 and EP3SL70 devices.
- Cyclone® III FPGAs—Added support for Cyclone III automotive ordering codes.
- MAX® II Z CPLDs—Programming support added for all devices including the EPM570Z device.
- HardCopy® III ASICs—Added companion support.
Visit the Quartus II Web Edition Software Feature Comparison web page for a detailed comparison between the fully featured Quartus II Subscription Edition software and the Quartus II Web Edition software.
Free Online Training Series
- Free Quartus II Software Online Training—Take advantage of this series of online training sessions to learn about the latest Quartus II software features. Topics include an introduction to the Quartus II software, power analysis, command-line operation, and Tcl scripting, timing analysis, and more.
- In-Depth, Instructor-Led Training—Three Quartus II software classes address beginner to advanced Quartus II software users. Each class combines lecture with hands-on lab exercises and a question and answer session with the instructor:
- The Quartus II Software Design Series—Foundation
- The Quartus II Software Design Series—Verification
- The Quartus II Software Design Series—Optimization
Technical Resources for Quartus II Software Version 8.0
Download and Purchase Altera's Software
Visit the download center on June 2, 2008 to download Altera's design software version 8.0, including Quartus II subscription edition and web edition software. Altera's design software is also available in DVD format by request.
Altera’s software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim®-Altera edition and a full license to the IP Base Suite, which includes 11 of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license and is available for purchase online at Altera's eStore.
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