SOPC Builder's System Interconnect Fabric Features
SOPC Builder's system interconnect fabric, formally known as the Avalon® switch fabric, is Altera’s specialized interconnect technology. It is available in Quartus® II software and offers a host of features to support system-level design, including:
Avalon Interface Specification
The Avalon interface provides the basis for describing the peripheral interfaces, including:
Automatic System Interconnect Fabric Generation Through SOPC Builder
Through SOPC Builder, you can add peripherals, specify master/slave relationships, and define memory maps. SOPC Builder automatically generates the system interconnect fabric based on your input and peripheral requirements.
In addition to the system interconnect fabric, SOPC Builder generates the software header files containing all the address and register declarations provided by the components. Each time you generate your system, SOPC Builder updates these header files to ensure coherency between the hardware and the software images. Figure 1 shows an SOPC Builder sample screen for the system interconnect fabric.
Figure 1. SOPC Builder User Interface for the System Interconnect Fabric
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Simultaneous Multiple Masters
Optimize your system data flow by creating system architectures custom-tailored to your application-specific bandwidth needs. The system interconnect fabric enables simultaneous multi-master operation for maximum system performance by using the slave-side arbitration technique. Slave-side arbitration determines which master gains access to the slave if multiple masters attempt to access the slave at the same time.
The system interconnect fabric supports simultaneous transactions for all bus masters and automatically includes arbitration for peripherals or memory interfaces that are shared among masters. Additionally, you can use a direct memory access (DMA) peripheral with any slave peripheral to provide bus-mastering capability.
Built-In Address Decoding
The system interconnect fabric includes chip-select signals for all peripherals, even user-defined peripherals, to simplify the design of the embedded system. Separate, dedicated address and datapaths provide an easy interface to on-chip user logic. You do not need user-defined peripherals to decode data and address bus cycles.
Native or Dynamically Sized Peripheral Interfaces
Dynamic bus sizing allows you to use low-cost, narrow memory devices that do not match the native bus size of your CPU. For example, a system configured with a 32-bit datapath can easily integrate an 8-bit flash memory device. In such a system, the dynamic bus sizing logic automatically executes multiple bus cycles, if necessary, to fetch wide data values from the narrow peripheral. SOPC Builder automatically adds the dedicated logic needed to perform re-sizing and alignment.
Peripheral Transfer Support
The system interconnect fabric supports each type of transfer supported by the Avalon interfaces. Each peripheral port into the fabric is generated with the optimal amount of logic to meet the requirements of the peripheral, including wait-state logic, data width matching, and passing wait signals.
Read and Write Transfers With Latency
The system interconnect fabric can perform read and write operations with latency. Latent transfers are useful to masters wanting to issue multiple sequential read or write requests to a slave, which may require multiple cycles for the first transfer but fewer cycles for subsequent sequential transfers. This can be beneficial for instruction-fetch operations and DMA transfers to or from SDRAM. In these cases, the CPU or DMA master can pre-fetch (post) multiple requests prior to completion of the first transfer and thereby reduce overall access latency.
Clock Domain Crossing Circuitry
The system interconnect fabric generated by SOPC Builder automatically adds specialized circuitry to support transactions between peripherals operating on different clocks. The specialized circuitry is useful when peripherals have been designed to operate at a specific frequency (such as video circuits or memory controllers), while other components need to operate at a different frequency.
Streaming Transaction
The Avalon streaming interface was designed for unidirectional flow of data, including multiplexed streams, packets, and digital signal processing (DSP) data, between a source interface and a sink interface. The Avalon streaming interface includes the following features:
- Low latency, high throughput data transfer
- Multiple channel support with flexible packet interleaving
- Sideband signaling of channel, error, and start and end of packet delineation
- Support for data bursting
Up to 128-Bit Datapaths
The Avalon memory-mapped interface allows an addressable range of 1 to 32 bits. Memory and peripherals can be mapped anywhere within the address space of the master port. In other words, a CPU (or other master) with a 32-bit address range has an addressable memory range of up to 4 Gbytes, and the peripherals can be mapped anywhere within that range. For maximum data throughput, component datapaths can be up to 128 bits. Using the dynamic bus sizing capability of the system interconnect fabric, data movement between peripherals with different datapath widths are automatically handled.
Flexible Control Signal Assertion
The Avalon memory-mapped interface allows the control signals for chipselect, read, write, and other signals to be asserted high or low. You can write each peripheral according to the your preference or need. The system interconnect fabric automatically matches assertion logic between components to quickly reuse peripherals in new designs without adjustments.
Fixed and Variable Length Transfers
The Avalon memory-mapped interface supports peripherals that execute read and write data transfers in a fixed numbers of cycles. The number of cycles for a read and a write do not need to match. The Avalon memory-mapped interface also supports peripherals with a wait signal. For these peripherals, the transfers can vary from transfer to transfer by asserting their wait signal.
Burst Transactions
The Avalon memory-mapped interface includes signals for burst data transactions between master/slave pairs. The burstcount and beginbursttransfer signals indicate a master peripheral's capacity to initiate a burst-style transaction. The maximum number of words transferred during a burst is indicated by the value of burstcount. Interleaving, continuous, and wrapping burst-style transactions are supported. The system interconnect fabric generated by SOPC Builder automatically supports the connection of burst masters to non-burst aware slaves.
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