Quartus II SOPC Builder Design Flow and Features
Altera's Quartus® II design software includes the SOPC Builder system-level design tool and supports the optional DSP Builder system-level design tool. System-level design tools allow you to rapidly design and evaluate system-on-a-programmable-chip (SOPC) architectures and increase productivity by designing at a higher level of abstraction.
SOPC Builder Design Flow
The Quartus II SOPC Builder feature:
- Integrates off-the-shelf intellectual property (IP) and your custom logic
- Builds your interconnect
- Creates software development kits based on the components in the systems
SOPC Builder components include embedded processors that are internal or external to the FPGA and peripherals, including IP and customer-created peripheral cores and off-chip devices such as ASSPs and ASICs. With the export of header files and peripheral drivers, SOPC Builder accelerates the development of application software. SOPC Builder enables you to focus on the key components of your systems and begin developing the applications sooner by eliminating the engineering time required for system integration tasks. Figure 1 shows a high-level view of the SOPC Builder design flow.
Figure 1. SOPC Builder Design Flow
SOPC Builder Features
By allowing you to focus on system design and differentiation instead of error-prone manual system integration tasks, SOPC Builder gives you:
- Faster time-to-market
- Ease of use
- Design reusability
Table 1 lists some of the feature highlights of SOPC Builder.
| Table 1. SOPC Builder Feature Highlights |
| Feature |
Description |
| Design Component Selection and Parameter Selection |
Push-button integration of off-the-shelf IP and your own custom SOPC Builder components. Off-the-shelf IP includes:
- Nios® II processor
- Memory interfaces including DDR and DDR2
- Common embedded system peripherals
- Bridges and interfaces including PCI, PCI Express, Serial RapidIO®, and Gigabit Ethernet
- Digital signal processing (DSP) IP
|
| HDL and Interconnect Fabric Generation |
Generates HDL to build a system interconnect fabric optimized for the requirements of each system. Integration tasks automatically performed by SOPC Builder include:
|
| Custom Logic Integration |
Allows you to create your own custom SOPC Builder components. You can reuse components designed for the SOPC Builder system interconnect fabric and drop them into any SOPC Builder project with the click of a button. |
| Testbench Generation |
Outputs testbench suites to test-generated systems. |
| Software Development Kit (SDK) Generation |
Outputs a custom SDK based on the memory map and components of the generated system. Every time the system is updated, a new SDK is generated to pass along to the software developer(s). |
DSP Builder Integration with SOPC Builder
Using Altera's DSP Builder, you can perform algorithmic DSP design at a high level of abstraction in The MathWorks' MATLAB and Simulink software. You can push a button to port the design to HDL files. DSP Builder can generate SOPC Builder-ready DSP blocks that you can easily integrate into a complete SOPC system design using the SOPC Builder. Figure 2 shows a high-level view of the DSP Builder design flow.
Figure 2. DSP Builder Design Flow
Hardware-Software Co-simulation
You can use system-level design tools for early-in-design testing of hardware and software interactions through testbench files and simulation models before constructing any hardware prototypes. You can also use the rapid system generation and hardware-software co-simulation features to perform tradeoff analysis of which functions should be implemented in hardware versus embedded software.
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