Time-Proven Productivity Leadership for FPGA Design Software
Time-proven productivity leadership is a key factor in deciding which FPGA platform to adopt. If you are looking for a proven, easy-to-use software platform for your next programmable logic design, look no further. Altera’s Quartus® II software provides everything you need to design with Altera® PLDs, including FPGAs, SoCs, and CPLDs. It is a complete development package that comes with a user-friendly GUI and best-in-class technology to help you bring your ideas into reality.
Time-Proven Productivity Tools
Altera has a proven track record for productivity leadership. Over the years, Altera delivered a host of tools and features to enhance productivity, many of which are the first in the industry.
Recently, Altera became the first in the industry to announce the Altera SDK for OpenCL*. Combining Open Computing Language (OpenCLTM), an open standard parallel programming language, with the parallel performance capabilities of an FPGA provides a powerful solution for system acceleration. The Altera SDK for OpenCL is in full production release.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
Table 1. Quartus II Software Productivity Tools and Features
|Tool||Year of Introduction||Description|
|Altera SDK for OpenCL||
|The Altera SDK for OpenCL provides a design enviornment to implement OpenCL applications for FPGAs. You can target FPGAs in a heterogeneous system by designing entirely in a C-based language.|
|Qsys system integration tool||
|Qsys is the next-generation system integration tool. This tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.|
|DSP Builder Advanced Blockset||
|DSP Builder Advanced Blockset is a digital signal processing (DSP) development tool that interfaces between the Quartus II software and MathWorks MATLAB/Simulink DSP tools. With DSP Builder Advanced Blockset, you can go from system definition and simulation to system implementation in a matter of minutes. DSP Builder Advanced Blockset, the first tool in the industry to leverage a fused-datapath technology, offers a model-based floating-point design tool that allows implementation of complex floating-point DSP algorithms on an FPGA.|
|System Console debug toolkit||
|System Console is a system-level debug tool that helps you to quickly and efficiently debug your FPGA design in real time using read and write transactions.|
|The Transceiver Toolkit is based on System Console. This toolkit gives you real-time access to your transceiver settings, visualizes the signal eye, and quickly performs transceiver link verification.|
|External Memory Interface Toolkit||
|The External Memory Interface Toolkit is based on System Console. This toolkit helps you bring up your boards faster by identifying calibration issues and measuring the margins for each DQ strobe (DQS) signal.|
|TimeQuest timing analyzer
with SDC support
|TimeQuest timing analyzer is the second generation, easy-to-use timing analyzer which leverages industry-standard Synopsys® Design Constraints (SDC) support to achieve accurate timing, resulting in faster timing closure.|
|PowerPlay power analysis tools||
|Altera’s PowerPlay power analysis technology features Excel-based PowerPlay early power estimators (EPE) and the PowerPlay power analyzer tool in the Quartus II software. These power analysis tools give you the ability to estimate power consumption from early design concept through design implementation.|
|The fused datapath toolflow allows the implementation of complex floating-point DSP algorithms on an FPGA.|
|Altera is the first and only FPGA vendor with full multiprocessor support. The multiprocessor support in the Quartus II software allows you to run your design on multiprocessor computers. Enabling parallel processing on your designs can improve your compilation time by an average of 20 percent.|
|The incremental compile feature supports top-down and bottom-up design, which delivers faster compilation times for design iterations while preserving performance. The incremental compile feature allows you to compile only the changes in a partition, helping you reduce compilation time by up to 70 percent. In addition to reducing compile time, this feature also enables team-based designs.|
Time-Proven Continuous Compilation Time Reduction
With faster compile times, you can improve your productivity by completing multiple design iterations per day. Faster compile times allow you to effectively develop complex designs that leverage the great capabilities of today’s FPGAs.
The Quartus II software has seen almost a decade of compile time improvements, with an average annual compile time improvement of 20 percent. Altera’s advanced place-and-route algorithms contribute to compilation time reduction by allowing you to quickly find the best results based on four cost criteria – timing, congestion, wire length, and power minimization.
Figure 1. Relative Compile Time Improvements Across Releases
Third-Party EDA Tools Support
The Quartus II software interfaces with leading third-party EDA tools throughout the design flow. You can take advantage of various design and verification flows that you are already familiar with to maximize your efficiency.
Extensive Suite of Training Resources
Not sure how to get started with using the Quartus II software? Altera addresses your concern with a wide variety of training resources and collaterals to help you to learn. There are many online video demos, interactive tutorials, and online, instructor-led, and virtual classrooms to familiarize you with the design tool. There is also an introduction manual and handbook where you can find detailed information on specific topics.
Software plays an important role in helping you effectively address your resource and design constraints. There are 100,000s of users who trust and use the Quartus II software to leverage its productivity tools and features to speed up the FPGA development process. Altera’s extensive EDA partner support and suite of training resources further improves your productivity and starts you off on the right track.
So, for your next programmable logic design, use Altera’s Quartus II software.
Learn More Today!
New to FPGA design? Get more resources and information from the FPGA and CPLD design flow web page.
Ready to learn more about the Quartus II software? Watch the webcasts below:
|Webcast: Enhance Your Productivity with Faster Design Compile Times
When choosing your FPGA design software, be sure to consider compile time, a key productivity advantage. In this webcast, you'll learn how Altera's Quartus II design software delivers a 2X to 3X compile time advantage over competitive software.
|Webcast: Increase Your Team's Productivity with the Right FPGA Software
(For engineering managers)
See how choosing the right FPGA software can improve your team's productivity, saving you time, budget, and resources in less than 20 minutes.
|Webcast: Improve Your Productivity with the Right FPGA Software
Get a complete overview of the key features and functions of Quartus II software in less than an hour.
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