Use this checklist as supplememental information during the design planning and implementation phases. The checklist outlines generic guidelines, as well as provides pointers to additional documentation wherever needed. You can print the checklist for your reference, and check off each items based on your individual project scenario.
Doing this during the initial planning phase and revisiting the list during the implementation phase helps you to get organized, and make sure you are using the methodology and settings that help you meet your design requirements.
Design Planning, Implementation, Optimization and Timing Closure Checklist
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1
Use synchronous design practices.
Using synchronous design practices results in your designs being more stable, and you will find it much easier to run timing analysis on your design when you follow synchronous design practices.
Follow recommended coding styles, especially for inferring device dedicated logic such as memory blocks. Consider the resources available in the target device while coding your design. Write your code to take full advantage of available hardware resources in the device, such as RAM blocks and DSP blocks.
For more details about HDL coding styles, refer to the Recommended HDL Coding Styles chapter in the Quartus II Handbook.
3
Review/regenerate timing and other constraints for each new design project, making sure to use appropriate requirements. Pay attention clock signals in your design, and constrain all the clocks in your design.
If your project settings are inherited from earlier Quartus II projects, make sure to revisit the settings and verify that the settings are valid for your new design project. Make sure to make the settings depending on whether you would like to optimize for area or for performance. Ensure timing constraints are complete and accurate, including all clock signals and I/O delays.
4
Follow recommendations to partition your design for incremental compilation. Plan early in the design cycle.
Plan your design to take advantage of incremental compilation to preserve performance, and reduce compilation times, and enable team-based design flows. The Quartus® II software offers tools to help you partition your design, such as Partition Planner and an Incremental Compilation Advisor.
Create a design floorplan for each partition for best results. If you are planning to use incremental compilation, each partition should have an assigned floorplan.
Incremental compilation helps to preserve performance in large team-based designs. Incremental compilation also helps you reduce compilation time.
Instantiate IP cores from Altera’s Megacore IP Library using the MegaWizard® Plug-In Manager for many of the commonly used IP cores.
Use pre-verified Megafunctions to help reduce your design cycle time. For a list of available MegaFunctions, refer to the Megafunctions Literature page.
9
If you have multiple processors available for compilation, set up parallel compilation.
The Quartus II software can detect the number of processors in your computer and take advantage of multiple processors to reduce compilation time. You can also set the number of processors manually in the Compilation Process Settings tab of the Settings panel in the Quartus II GUI.
10
Turn on Optimize Fast-Corner Timing.
When you turn on this setting, the Quartus II software optimizes your design for both the slow-corner and the fast-corner timing and operating conditions. You can turn this setting on from the Fitter Settings panel in the Quartus II GUI.
11
Turn on Enable Multi-Corner Timing Analysis.
When you turn on the multi-corner timing analysis, the TimeQuest Timing Analyzer reports both the best- and worst-case scenarios. In the Quartus II GUI, turn on this setting from the Timing Analysis settings panel.
12
If your design is complete, check whether the timing of your design is satisfactory. Perform Early Timing Estimation.
Early Timing Estimation gives you preliminary timing estimates before running a full compilation, which results in a quicker iteration time.
For more information on how to use the TimeQuest Static Timing Analyzer for analyzing the timing of your design, refer to Timing Analysis section in volume 3 of the Quartus II Handbook.
13
Check for any Errors or Warnings that appear during compilation of your design.
Check all warning messages to ensure that they do not negatively impact your design. Fix the problems that cause errors or warnings related to output loading or I/O rules.
14
After compilation, use the Quartus II Design Assistant to check design reliability and to discover possible design errors.
Review resource utilization reports after compilation in the compilation reports panel of Quartus II user interface.
For more details on resource utilization issues, refer to the Area and Timing Optimization chapter in Volume 2 of the Quartus II Handbook, and the Area Optimization Advisor in the Quartus II software.
16
Review the TimeQuest Timing Analyzer reports after compilation to ensure there are no timing violations.
Use the appropriate Quartus II Advisor for your design needs.
The Quartus II software offers many advisors, including:
A Timing Optimization Advisor to suggest optimization settings to improve the timing performance of your design
An Area Optimization Advisor to suggest optimization settings to reduce resource utilization
A Compilation Time Optimization Advisor to suggest settings to reduce the compilation time for your design
If you run multiple optimization advisors, be aware that the recommendation of one advisor may contradict the recommendation from another advisor. Give higher priority to the recommendations of the advisor that is more critical for your design.
18
Use the Design Space Explorer (DSE) to specify the best settings for your design based on your requirements. This is especially helpful later in the design cycle, because small changes may result in failed timing requirements.
Each FPGA design is unique. There is no standard set of options that always results in the best performance. The DSE is an automated utility available in the Quartus II software that helps you to determine the best settings for your design.
For more information about the DSE, refer to the Design Space Explorer chapter in the Quartus II Handbook and to Quartus II Help.
Create all pin-related assignments using the Quartus II Pin Planner.
Although you may be able to make some pin-related assignments using the Assignment Editor, Altera recommends using the Pin Planner for all pin-related assignments.
For more information about the Pin Planner, refer to the I/O Management chapter of Quartus II Handbook, and to the Quartus II Help.
2
To import any I/O assignments from other Quartus II projects, use the Quartus II software’s Import Assignments from the Assignments menu.
There may be situations in which you must import I/O assignments from other Quartus II Projects (.qsf files), other Tcl scripts, or .fx files.
For more information on importing assignments, refer to the I/O Management chapter of Quartus II Handbook, and to the Quartus II Help.
3
While you are creating assignments or constraints in the Pin Planner, ensure that the Live I/O Check feature is on.
If you do not use Live I/O Check feature, any errors or warnings do not appear instantaneously, but may show up during the I/O assignment analysis or during compilation. Turning on the Live I/O Check helps find problems with the I/O assignments before assignment analysis or compilation.
To turn on the Live I/O Check feature, in the Quartus II software, from the Quartus II Pin Planner, open the View menu and select the I/O Check Status window.
4
Select suitable signaling type and I/O standard for each I/O pin.
Check available device I/O features that can help interface with other devices in the system, such as current strength, slew rate, I/O delays, open-drain, bus hold, programmable pull-up resistors, and PCI clamping diodes.
Ensure those appropriate I/O standards are supported in targeted I/O bank.
6
Check the output loading at output pins.
Use the Pin Planner or Assignments Editor to create output load assignments. If you are using Advanced I/O Timing Analysis, use board trace models to specify the output loads at all the output and bidirectional pins.
To view the schematic of board trace models, right click on a pin in All Pins List in the Pin Planner and select Board Trace Models.
To view the board trace model’s global parameters of an I/O standard, from the Device settings page, select Device Pin Options and select Board Trace Model tab.
7
In the pin planner, check the I/O Standards, current drive strength, and slew rate,if applicable.
8
Check that any unused pins are set appropriately to VCC or GND.
Use the Device and Pins dialogue box to specify how you want to set the unused pins on your device.
9
Allow the software to assign locations for the negative pin in differential pin pairs.
When you make the location assignment of a differential pin, the negative pin is automatically created and assigned.
To learn how you can declare differential pin in your HDL code, refer to the I/O Management chapter in the Quartus II Handbook.
10
Place I/O pins that share voltage levels in the same I/O bank.
11
Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.
12
Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.
13
Follow guidelines for placement of LVDS pins.
The Quartus II software has built-in checks that guide you when you are placing LVDS pins. These rules are checked during I/O assignment analysis.
For more details about what rules are checked, refer to the I/O Managementchapter of the Quartus II Handbook. To learn about high-speed differential I/O interfaces in Altera devices, refer to the appropriate device handbook.
14
Make dual-purpose pin settings, and check for any restrictions when using these pins as regular I/O.
15
Use correct dedicated clock pins for clock and global control signals.
16
Place important clock and asynchronous control signals near ground signals and away from large switching buses.
17
Avoid using I/O pins one or two pins away from the PLL power supply pins for high-switching or high drive strength pins.
18
Configure board trace models for Quartus II advanced I/O timing analysis.
Some device families, such as Stratix III and Cyclone III device familes, support Advanced I/O Timing Analysis (AIOT) only. If required, use the board trace models and specify the board components for each output and bidirectional pin.
19
Ensure that the I/O Assignment Analysis, which checks I/O assignments, has completed with no errors.
You can run the I/O Assignment analysis from the Processing menu of Quartus II GUI.
20
Run the Fitter to verify I/O timing. Use Quartus II Fitter reports after full compilation for sign-off of pin assignments.
The Fitter reports contain the I/O Assignment Analysis summary, and the I/O usage report. Read these reports to determine whether there are any warnings that indicate problems in the design.
21
Verify that the Quartus II pin assignments match those in the schematic and board layout tools.
To transfer the pin information from the Quartus II software to a third-party board tool, use the flow described inI/O and PCB tools section in volume 2 of the Quartus II Handbook.
22
Check whether any third-party signal integrity is required.
Use Quartus II settings dialogue box to specify the I/O model format required for simulation. Use IBIS or HPICE. Perform I/O Assignment analysis in Pin Planner and run the EDA netlist writer. Alternately, compile the design; the EDA netlist writer runs automatically to produce the IBIS model files or HSPICE decks.
23
Ensure that you have performed signal integrity checks. The signal integrity analysis should include the following tasks:
Analyze design for possible simultaneous switching noise problems.
Perform board-level simulation using IBIS models (when available) to identify SI related issues.
Reduce number of pins that switch voltage at exactly the same time whenever possible
Use lower drive strength, differential I/O standards, and lower-voltage standards for high-switching I/Os.
Reduce number of simultaneously switching output pins within each bank.
Spread switching I/Os evenly throughout an I/O bank.
Separate simultaneously-switching pins from input pins that are susceptible to SSN.
Use staggered output delays to shift the output signals through time, or use adjustable slew rate settings
Consider signal integrity issues during board design:
Break out large bus signals on board layers close to the device, route traces orthogonally if two signal layers are next to each, use a separation of 2× to 3× the trace width.
Ensure that the board has decoupling capacitors required for signal integrity on the Altera device. (Contact your Altera FAE for the guidelines for decoupling capacitors.)
For more information about signal integrity issues, refer to the Signal Integrity Center on the Altera website (www.altera.com).
24
For some specific Altera devices, such as Stratix II GX and Stratix III devices, you can also use the SSN spreadsheet tool to estimate the SSN in I/O banks.
To get this SSN tool, contact Altera Applications
25
Check if any third-party board level timing analysis is required (Use the Quartus II Settings dialogue box to specify the tool, for example, Mentor’s Tau.)
26
If making, copying or reusing logic assignments in the .QSF for one device family to another, ensure that the target device supports the logic assignments being used.
In general, all assignments should be made using the Pin Planner or the Assignment Editor
27
Unused I/O pins can be configured in various different ways (e.g. inputs tri-stated, outputs driving ground, etc.) Be aware that different settings will consume various amounts of power
For more details, refer to the I/O Management chapter in Volume 2 of the Quartus II Handbook.
Filling in the input parameters in the EPE correctly will provide more accurate power estimation. Please ensure the input parameters mentioned below have the correct or best estimated value.
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1
Select proper ambient temperature, TA for your device.
Ambient temperature is the air temperature near the PLD. The case temperature on the device may differ from ambient temperature when there are other devices or airflow/heat sink nearby.
2
Use maximum Power Characteristic when using EPE as power supply network design reference.
3
Check and modify the clock frequency accordingly in every design modules for all sheets used in the EPE.
The Quartus II software outputs an average or zero clock frequency for all blocks into the early power estimator file.
4
Check and modify the toggle rates of every design module accordingly for all sheets used in the EPE to avoid under estimation.
Different blocks should have different toggle rates. The Quartus II software outputs an average or zero clock frequency for all blocks when importing a Quartus II-generated file into the early power estimator file.
5
For RAM blocks used in your design, modify enable %, write %, and R/W % accordingly in the RAM sheet of the EPE.
Under estimates, on the enable %, write %, and R/W %, results in under-estimation of the power consumed.
6
To avoid over estimation of power consumption, if differential pins are used for I/Os in your design, check whether a differential pair is entered as one pin into the spreadsheet.
One differential pin in the spreadsheet is a differential pair including both the p and n pins.
7
For I/Os used in your design, you must modify OE % accordingly in the I/O sheet of the EPE. This is necessary when importing early power estimator files from Quartus II software.
Over-estimates on the IO OE% results in over-estimation of the power consumed.
8
For I/Os used in your design, add the Load (pF) values for the outputs in the I/O sheet of the EPE.
This is the pin loading external to the chip (in pF). It applies only to outputs and bidirectional pins. Users do not need to include the pin and package capacitance in this column; only the off-chip capacitance is required.
9
For I/Os used in your design, you must verify whether the I/O standards match design usage. Voltage-referenced I/O standards (such as HSTL and SSTL) use off-chip termination (OCT) schemes, which require additional power from the FPGA VCCIO supply.
10
For the Clocks in your design, you must check and modify global enable % and local enable % accordingly in the clock sheet of the EPE.
Under-estimates on the global enable % and local enable % results in under-estimation of the power consumed.
Quartus II PowerPlay Power Analysis and Optimization Checklist
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1
Before the design is complete, estimate power consumption with the Early Power Estimator spreadsheet.
Many Altera device families have an Early Power Estimator spreadsheet utility to help you estimate the power dissipation before the design is complete. You can download the Early Power Estimators for different device families from the Altera website .
2
To optimize your design for power consumption, use recommended design techniques and Quartus II options, if required.
For more details about low-power design techniques that can reduce power consumption even further, and the Programmable Power Technology available in some Altera device families, refer to the Power Optimization chapter in the Quartus II Handbook.
3
Specify Operating Conditions of your design in the Quartus II software.
Your power estimation is more realistic when you specify correct operating conditions.
4
Compile your FPGA design with realistic timing constraints in Quartus II software.
Using realistic constraints ensures that the Quartus II software does not carry out optimizations that may cause increased power dissipation but are not critical to meet timing performance of your design.
5
Simulate your design and create a gate-level signal activity file (SAF) or Value Change Dump (VCD) file which contains the toggle rate data information of your design using Quartus II Simulator or 3rd party simulator. These files can be use to optimize your design for power and also to get an accurate power estimation.
Refer to the PowerPlay Power Analysis chapter in the Quartus II handbook to get more details about how to generate SAF or VCD file.
6
Use either Signal Activity File(s) or Value Change Dump File(s) or both as an input to the PowerPlay Power Analyzer to accurately estimate the power for your design.
7
If you don’t have the simulation output files available then enter default toggle rate for the I/Os and use Vectorless estimation option in PowerPlay power analyzer to estimate the power consumption of your design.
8
Review PowerPlay power analyzer reports for power planning, heat dissipation and power optimization purposes.
After you run the PowerPlay Power analyzer, you can read the related power reports from the Compilation Report panel of the Quartus II GUI. You may have to turn on the "Write signal activities to report file" and "write power dissipation by block to report file" settings option on PowerPlay power analyzer tool settings page before you run the power analyzer to get more in depth information on your design power.
9
When using a VCD or SAF file to provide signal activities to Power Analyzer, check the Power Analyzer's "Confidence Metric Details" report to ensure that the signal activities from the VCD or SAF files were properly annotated to calculate the design power.
Check that the fraction of signals with data from simulation is used as expected for power calculation. If the percentage is too low, then this might indicate an incorrect entity name setting for the input file. It may also indicate a problem with the simulation itself, e.g. improper test bench setup, improper entity name and that the design was simulated for too short.
10
Inspect the "Block average toggle rate" column in the "Thermal Power Dissipation by Block Type" report section. Check if those average toggle rates seem reasonable.
A too-low or too-high average toggle rate could indicate invalid settings, e.g. bad simulation, non-representative simulation, no clock settings (in case of no simulation). It's especially important to check the average toggle rates for "clock control block", as that drives the clock networks and often indirectly determines toggle rates of the logic in that clock domain.
11
Use PowerPlay power analyzer reports to identify the modules of your design that are consuming large amount of power and optimize those module for power.
Refer to the Power Optimization chapter in the Quartus II handbook to get more details on low power design techniques that can further reduce power consumption for your design.
12
To further optimize your design for power select PowerPlay power optimization option value as “Extra effort” for Analysis & Synthesis Settings in Quartus II software.
This optimization option makes the changes to the synthesis netlist to fully optimize your design for power.
13
To further optimize your design for power select PowerPlay power optimization option value as “Extra effort” for Fitter Settings in Quartus II software.
This setting can only be applied on a project-wide basis and performed place-and-route optimization during fitting to fully optimize the design for power. The user should provide the SAF or VCD simulation data so the Fitter can better adapt to the simulated activity of the design. This can result in larger power reductions.
14
Use the Quartus II Power Optimization Advisor to get additional settings to reduce power dissipation in your design.
15
Choose smallest device that can fit your design as it will have less static power consumption.
16
Select an appropriate cooling solution (use a heat sink, and/or add airflow to the system) or reduce dynamic or I/O power to reduce the junction temperature. This will result in lower device static power.
17
Choose appropriate I/O standards to minimize design power.
18
Use DSP blocks for multiply, multiply accumulate and complex multiplication functions rather than implementing these functions in logic cells.
19
Use the M512, M4K, M9K, M144K and M-RAM blocks, instead of logic cell registers to implement RAMs and medium to large shift registers.
20
Use clock enable signals for your memory blocks.
21
Choose area optimization rather than timing or delay optimization to save power.
22
Use gate-level register retiming to reduce circuit switching activity.
23
Use the altclkctrl megafunction to power-down a clock domain when it is idle.
24
Use a regional clock network or dual-regional clock network in favor of global clock networks, if possible.
Regional clock network or dual-regional clock network drive less clock routing and hence will consume less dynamic power.
25
Use pipelining and retiming for designs with many glitches.
These techniques are very effective for glitch-prone designs because it reduces switching activity, resulting in reduced power dissipation.
26
For Stratix III use a lower core voltage ("selectable core voltage") to reduce both
dynamic and static power.
The Quartus II offers a rich set of on-chip debugging options. Evaluate the tools early on in the design process to properly allocate connector pins and FPGA resources for the debugging process.
SignalTap II Logic Analyzer : JTAG connection required
SignalProbe – Free I/O pins needed
Logic Analyzer Interface (LAI) - JTAG connection required and test header for Logic Analyzer required.
In-system Sources and Probes – JTAG connection required
When using SignalTap II or the LAI, use incremental compilation flow to speed up compilation times and to preserve your top level design.
Be sure to set your design partitions to post-fit netlist type with a preservation level of placement and routing using the Design Partitions Window. Certain post-fit signals can not be connected to SignalTap II or LAI. These include output pins, and signals that have dedicated routing such as the transceiver blocks.
3
If there are multiple devices within the JTAG chain, you can select the device that you want to target using the device pull-down menu in the JTAG configuration window.
4
Consider using the SignalProbe feature if you only a small handful of control signals that you would like routed out externally for debugging. SignalProbe uses no on-chip memory or logic resources.
5
Use the Change Manager to view and apply SignalProbe connections when you recompile your design.
SignalProbe connections are preserved if the design partition that you’re applying a SignalProbe connection to is set to the preservation type Post-fit.
Checklist items 6-9 apply if you are using the SignalTap II logic Analyzer or the Logic Analyzer Interface (LAI)
6
Use a pre-synthesis flow if you want to choose signal names from your RTL, and compilation time is not a huge factor in your design.
Be sure to set your design partitions to source netlist type in the Design Partitions Window
7
Limit the connections to the output of registers. This helps to limit the number of changes you need to make in your configuration file.
8
If you debugging using post-fit signals, certain signals may not appear in the nodefinder due to optimization during the compile process. You can prevent the compiler from optimizing away the nodes that you want to add to your configuration file through the use of attributes in your HDL. Use the keep attribute on combinational nodes and the preserve attribute on registers to prevent the compiler from optimizing away these signals.
9
Note that certain post-fit signals can not be connected to SignalTap II. These include output pins and signals in hard IP blocks that require dedicated routing resources (such as high-speed transceiver blocks)
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