System Console: Faster Board Bring-Up and On-Chip Debug

System Console is a flexible system-level debug tool that helps designers quickly and efficiently debug their design while the design is running at full speed in an FPGA. System Console enables designers to send read and write system-level transactions into their Qsys system to help isolate and identify problems. It also provides a quick and easy way to check system clocks and monitor reset states, which can be particularly helpful during board bring-up. In addition, System Console allows designers to create their own custom verification or demonstration tool using graphical elements, such as buttons, dials, and graphs, to represent many system-level transactions and monitor the processing of data.

Video Demonstrations

		Faster Board Bring-Up with System Console See how you can bring up your board faster with a few simple checks Learn how to quickly isolate issues by checking your system’s resets and clocks, and by performing simple address-based read and write transactions  View Demo
		Building a Custom Verification GUI with System Console See how you can build your own custom GUI to debug and monitor your system Learn how to add different graphical elements to control and monitor your system  View Demo

Getting Started

• Read the System-Level Debugging and Monitoring of FPGA Designs (PDF) white paper
• Watch the System Console video demos
  • Faster Board Bring-Up with System Console
  • Building a Custom Verification GUI with System Console
• Download the Qsys System Design Tutorial (PDF) (includes System Console)
• Read the Analyzing and Debugging Designs with the System Console (PDF) handbook chapter
• Take a System Console training class
  • Free online training – System Console 
  • Instructor-led training – System Integration with Qsys
• Learn about other applications developed on System Console
  • Transceiver Toolkit
  • UniPHY External Memory Interface Debug Toolkit (PDF) handbook chapter