System Console is a flexible system-level debugging tool that helps designers quickly and efficiently debug their design while the design is running at full speed in an FPGA. System Console enables designers to send read and write system-level transactions into their Qsys system to help isolate and identify problems. It also provides a quick and easy way to check system clocks and monitor reset states, which can be particularly helpful during board bring-up. In addition, System Console allows designers to create their own custom verification or demonstration tool using graphical elements, such as buttons, dials, and graphs, to represent many system-level transactions and monitor the processing of data.
What's New for System Console in Quartus II Software v13.0
Other debugging tools can now use System Console channels: SignalTapTM II, In-System Source and Probes, In-System Memory Content Editor, Logic Analyzer Interface, Nios® II Debug and Nios II Terminal.
- Read the System-Level Debugging and Monitoring of FPGA Designs (PDF) white paper
- Watch the System Console video demos
- Download the Qsys System Design Tutorial (PDF) (includes System Console)
- Read the Analyzing and Debugging Designs with the System Console (PDF) handbook chapter
- Take a System Console training class
- Learn about other applications developed on System Console
- Transceiver Toolkit
- UniPHY External Memory Interface Debug Toolkit (PDF) handbook chapter