Verification and Board-Level Tools

• Features ASIC-strength timing analysis tool
• Provides native support for industry-standard Synopsys^® Design Constraints (SDC) format
• Supports complex clocking schemes
• Provides improved performance
• Enables easier ASIC prototyping
• Provides easy-to-use GUI

View video Training Support Handbook (PDF)

• Automatically routes high-performance paths and then programs the non-performance paths as low power
• Features programmable power technology
• Automatically powers down unused logic
• Dramatically reduces overall power use

View video Training Support Handbook (PDF)

• Helps you achieve timing closure faster and shorten verification time
• Provides analysis and editing capabilities in an integrated floorplan
• Allows you to make floorplan assignments, implement engineering change orders (ECOs), and perform power analysis

Support Handbook (PDF)

• Provides flexible system-level debug tool that helps designers quickly and efficiently debug their design while the design is running at full speed in an FPGA
• Sends read and write system-level transactions into their system to help isolate and identify problems
• Quickly checks system clocks and monitor reset states
• Allows you to create your own custom verification or demonstration tool using graphical elements, such as buttons, dials, and graphs

View videos Training Handbook (PDF) System Console web page

• Offers FPGA and board designers real-time access to transceiver settings and improves board bring-up time
• Provides bit-error rate test (BERT) function with pseudo-random binary sequence (PRBS) pattern generator and checker
• Determines the width and height of the signal eye with Stratix^® V FPGA EyeQ
• Offers access to signal integrity hardware features including adaptive equalization (AEQ) and decision feedback equalization (DFE)
• Features AutoSweep with new interval stepping capability allow quick testing of many combinations of PMA Analog settings to find the optimal set for a particular transceiver link
• Provides support for Stratix V GX, Stratix IV GX, Stratix IV GT, Arria^® II GX, and Arria V GX devices (device support varies – for more information, see the Transceiver Toolkit page)

• Provides a system-level debugging tool that captures and displays real-time signal behavior
• Gives you the ability to observe interactions between hardware and software in system designs
• Supports the highest number of channels, sample depth, and clock speeds of any embedded logic analyzer
• Gives you enhanced control over data sampling and display
• Features a graphical interface

View video Training Support Handbook (PDF)

• Helps designers bring their boards up faster by identifying calibration issues and measuring the margins for each DQ strobe (DQS) signal
• Verifies designs using a data-valid window report, a visual representation of the available margins for each individual DQS pin that allows you to quickly identify the source of the problem

Handbook (PDF)

• Provides powerful ways to view your initial and fully mapped synthesis results during the debugging optimization or constraint entry processes
• Allows you to view your initial synthesis results to determine whether you have created the desired logic

View video Training Support Handbook (PDF)

• Manages pin assignments interactively through seamless integration with Quartus II Pin Planner
• Provides feedback on potential SSN violations during pin assignments
• Allows you to interactively manage pin assignments, reduce SSN violations for faster board design, and shorten system-level debug time
• Supports all Stratix III, Stratix IV, and Arria II GX FPGAs

Handbook (PDF)