As time-to-market pressures increase, ASIC mask and development costs rise while FPGAs continue to increase in performance and system-level features. So, more and more traditional ASIC applications are being filled with Altera® FPGAs.
Altera’s Quartus® II design software provides high performance and productivity methodologies that are fundamentally similar to traditional ASIC design flows, along with features that will enable you to easily and successfully design for Altera FPGAs. Quartus II software also offers some innovative technologies to speed up system design and take advantage of FPGA in-system verification.
Altera’s latest generation of FPGAs includes larger logic densities and comprehensive system-level features, and are based on leading-edge process technologies.
You use the same Altera Quartus II design software to design for FPGAs from the beginning of a design cycle, with predictable performance and power consumption.
Overview of Design Flows
While Quartus II software supports the standard register transfer level (RTL) synthesis, place-and-route, and verification ASIC design flow, it does not require some of the physical design and test design steps required for custom ASIC designs (as shown in Figure 1).
Figure 1. Using Quartus II Software Eliminates Several Custom ASIC Design Steps
Scan insertion and clock tree synthesis are not required using Quartus II software, because of the inherent design of Altera devices.
Developing ASICs typically requires careful design and placement of I/O cells to support the latest complex I/O standards with good signal integrity (SI) on all pins. You can use Quartus II design software to assign logic to configurable I/O cells with a simple spreadsheet-like interface assignment editor or a script. Quartus II software can also perform a quick check to validate pin assignments and corresponding I/O standard assignments up front to ensure proper operation.
Altera’s FPGAs include advanced, low-skew clock networks for clock distribution within the device, but do not allow you the freedom to implement fully custom clock networks. However, the pre-defined clock tree structure in Altera FPGAs enormously simplifies the design process and satisfies a majority of applications.
The following synchronous design practices are essential for long-term reliable operation and to make the design portable for implementation in different device speed grades or device architectures.
Quartus II software provides innovative features for rapid system design and hardware/software trade-off analysis. A broad array of off-the-shelf intellectual property (IP) cores are now available for system design in Altera FPGAs. This IP portfolio includes embedded processors, communications functions, optimized digital signal processing (DSP) functions, as well as interfaces and peripherals.
The Altera Qsys system-level integration tool that is included in Quartus II software, automate the process of adding, parameterizing, and linking IP cores into complete systems. A key element of Qsys is its ability to enable early-in-the-design-process testing of hardware and software interactions through testbench files and simulation models before any hardware prototypes are constructed. You can use the rapid system-generation features of Qsys to perform trade-off analysis of which functions should be implemented in hardware and which functions should be implemented in embedded software.
Timing Closure and ECO Support
Reaching timing closure is critical in any FPGA design flow. Quartus II software includes automated tools that offer ASIC-like control. For example, Altera’s Quartus II software includes a suite of physical synthesis optimizations, such as automatic register duplication and register retiming to tune design performance. Quartus II users can also manually duplicate registers to reduce fan-out on critical paths and make path-based assignments on critical timing paths in a design. The Quartus II software timing closure floorplan editor displays timing between any two node locations in the floorplan and can be used to manually adjust logic placement for optimum timing.
In a typical engineering project development cycle, the specification for the programmable logic portion is likely to change when engineering development begins or when all system elements are being integrated. These last-minute design changes are commonly referred to as engineering change orders (ECOs). ECOs are small changes to the functionality of a design, after the design has been fully compiled (that is, synthesis and placement-and-routing are completed). ECO support is a common element in ASIC design flows that Quartus II software supports on the HDL and netlist level, using incremental fitting and Chip Planner features.
ASIC design flows are typically driven by custom scripts or make files, and you can find the same kind of capability in Quartus II software. You can run Quartus II software from a GUI or command-line interface. Quartus II software supports a subset of the popular Synopsys Design Constraint (SDC) syntax used by many ASIC development tools to enter design constraints. Quartus II software also includes a new tool command language (Tcl)-based application programming interface (API) for scripting custom design flows.
EDA Verification Tool Support
If you are trying FPGA design for the first time, you will find that many of your favorite ASIC verification tools can be used in Quartus II design flows. Quartus II software can generate output netlists for analysis by all the leading EDA static timing analysis, HDL simulation, board-level timing analysis, and SI analysis software used in typical ASIC design flows.
There is no substitute for the real-time in-system verification advantages offered by FPGAs. Besides the obvious benefit of being able to make rapid FPGA design iterations to test in-system immediately, FPGA design tools such as Altera's Quartus II software offer the ability to seamlessly insert embedded logic analyzer functionality into designs. Quartus II software can also incrementally route debug signals to pins without changing HDL source files. Design fixes can now be implemented and tested in the lab using Chip Planner functions to view detailed design implementation structures and make incremental modifications in just minutes.