What's new in Quartus II design software version 9.1?
Quartus® II software version 9.1 delivers the #1 performance and productivity for FPGA, CPLD, and HardCopy® ASIC designs. This new release supports Altera's new lowest cost, lowest power FPGA family—Cyclone® IV GX FPGAs with integrated 3.125-Gbps transceivers. The Cyclone IV GX FPGA family is targeted to high-volume, cost-sensitive applications, enabling you to meet increasing bandwidth requirements while lowering costs. Version 9.1 further extends Quartus II software's productivity advantage by delivering 20 percent overall compile time reduction over Quartus II software version 9.0, and maintains 2x to 3x faster compile times than the nearest competitor for high-density 65-nm and 40-nm designs. In addition, the new Rapid Recompile feature in version 9.1 reduces compile times by 50 percent (on average) compared to a full compile when small engineering change order (ECO)-type design changes are made. Finally, this release also supports the largest FPGA in the industry—Stratix® IV E EP4SE820 devices.
New Rapid Recompile for Faster Design Iteration
The new Rapid Recompile feature enhances Quartus II software's ability to further minimize design compilation times. Rapid Recompile maximizes productivity by enabling faster small ECO-type design changes after a full compile, reducing compilation times by 50 percent (on average) versus running another full compile on the design. Rapid Recompile also significantly improves productivity during timing closure by preserving critical timing during late design changes.
- Download Quartus II Subscription Edition software version 9.1 (Includes free 30-day trial)
- Download Quartus II Web Edition software version 9.1 with service pack 1 (Free and no license required)
Cyclone IV GX FPGA Support
Quartus II software now supports Altera's new generation of low-cost and low-power FPGAs—Cyclone IV GX FPGAs with integrated transceivers. This transceiver variant in the Cyclone IV FPGA family supports mainstream protocols up to 3.125-Gbps with integrated hard PCIe intellectual property (IP) blocks. Compared to Cyclone III FPGAs with external transceivers, Cyclone IV GX FPGAs consume up to 30 percent less total power. Quartus II software version 9.1 offers PowerPlay Power Analysis and Optimization Technology to achieve the lowest power within your power budget. Start your Cyclone IV GX design with Quartus II software and take advantage of the power and cost savings without sacrificing performance.
The Cyclone IV GX EP4CGX15, EP4CGX22, and EP4CGX30 devices are supported (advanced support) in this release. For more information, please visit the Cyclone IV FPGA page. With this latest addition, Quartus II software offers support for all low-cost, mid-range, and high-performance (11.3-Gbps) transceiver FPGAs.
Industry's Fastest Compile Times
Quartus II software version 9.1 continues to deliver the industry's fastest compile times (2X to 3X faster than the nearest competitor for high-density 65-nm and 40-nm designs). Version 9.1 also delivers 20 percent overall compile time reduction over Quartus II software version 9.0 in all design stages. Regardless of which design stage you are at, you will experience faster compile times by upgrading to the latest version 9.1 release. In addition, Quartus II software introduces the new Rapid Recompile feature to extend its leadership in design compilation time.
With version 9.1, you get the following compilation advantages:
- Rapid Recompile for compile-time reduction and timing preservation when making small design changes
- Support for multiprocessors resulting in (on average) 20 percent faster compile times
- Advanced place-and-route algorithms for industry-leading compile times
- Incremental compile support for an additional compile-time reduction of up to 70 percent
Faster Multiprocessor Support with New Parallel Synthesis
Quartus II software is the leader in multi-processor support and is the only FPGA design software that performs parallel processing in all synthesis, place-and-route, static timing analysis, and assembler design stages. Quartus II software also can achieve a 20 percent compilation time saving, on average. In the version 9.1 release, new parallel synthesis support significantly reduces synthesis time for designs with partitions.
Faster Timing-Driven Synthesis
Timing-driven synthesis increases performance of your design by performing synthesis while keeping timing constraints in mind. Version 9.1 delivers an enhanced timing-driven synthesis feature, enabling you to improve design performance in 10 percent less compile time than the previous versions for faster timing closure.
Improved Incremental Compile
Time spent closing timing usually pertains to one or two critical blocks of your design. The incremental compile feature allows you make changes and compile just the critical blocks until timing is closed. This methodology allows you to reduce your compilation times by up to 70 percent compared to a flat compile. Version 9.1 adds more flexibility to close timing and optimize your design with partitions.
Additional Enhancements- VHDL 2008 Initial Support—Quartus II software maintains its leadership in language support by providing a more flexible and easy-to-use language structure.
- New and Expanded IP Base Suite—Three new and faster memory controllers
- Expanded SSN Analyzer Tool Support—With added support for Stratix IV and Arria® II GX devices, the SSN Analyzer allows you to interactively manage pin assignments and reduce SSN violations, providing faster board design and shorter system-level debug time.
- Non-Rectangular Floorplanning—Non-rectangular regions help create more compact and efficient floorplans, making it easier to achieve quality metrics. Quartus II software version 9.1 helps to create non-rectangular floorplans, which provides more freedom.
- Free Nios II/e Soft Processor—Now includes the lowest-cost Nios II processor core using the fewest FPGA logic and memory resources in the Nios II family.
- Expanded OS Support—Adds SUSE Enterprise 10 support in addition to SUSE Enterprise 9 support.
Device Support
- Stratix IV GX/Stratix IV GT FPGAs—Adds EP4SGX230, EP4SGX180, EP4S40G2, and EP4S100G2 device programming support. New EP4SGX290, EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5 devices include advanced support.
- Stratix IV E FPGAs—Adds advanced support for the EP4SE820 and the EP4SE230 devices.
- HardCopy III/HardCopy IV ASICs—New HardCopy IV GX compilation support enables design handoff for back-end ASIC processing.
- Arria II GX FPGAs—Adds programming support for EP2AGX65 and EP2AGX45 devices. Removes EP2AGX30 and EP2AGX20 devices from support.
- Removal of Older Families—The ACEXTM 1K, APEXTM 20KC, APEX 20KE, APEX II, FLEX® 6000, FLEX 10K, FLEX 10KA, FLEX 10KE, and HardCopy Stratix device families will be removed from Quartus II software version 9.1 and future releases. The last support for these device families is version 9.0 SP2, which will be available permanently on Altera's Download Center.
Advanced support includes compilation and pin-out support; programming support includes compilation, pin-out, and device programming (POF) support.
Getting Started
Evaluate or upgrade your software even faster with version 9.1 as both Quartus II Web Edition software and ModelSim®-Altera Starter Edition simulation tool do not require a license file. Quartus II Subscription Edition software includes a free 30-day trial and requires a license after the 30-day period. Follow these three steps to get started:
- Download Quartus II software
- Download Quartus II Subscription Edition software (Includes free 30-day trial)
- Download Quartus II Web Edition software (Free and no license required)
- Install Quartus II software
- Start evaluation/design
Pricing and Availability
Both Quartus II Subscription Edition and the free Quartus II Web Edition software packages version 9.1 are now available for download. Altera's Quartus II software and IP are also available in DVD format by request. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter Edition, and a full license to the IP Base Suite, which includes 15 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.
