Quartus II Software - The Productivity and Performance Leader
Altera’s Quartus® II software is the industry's number one software in productivity and performance for CPLD, FPGA, SoC, and HardCopy® ASIC designs. The Quartus II software lets you design for FPGAs in whatever method is most convenient for you. It supports the development of complex systems through a suite of full-featured, high-level design tools that provide C-based, system-/IP-based, and model-based design entry. Altera’s high-level design flows give you the fastest path from idea to silicon.
With Quartus II software v13.0, you can achieve an average of 25 percent faster compilation compared with Quartus II software v12.1, and up to three times improvement for some designs. In addition, Quartus II software v13.0 gives you a 23 percent fMAX advantage over our nearest competitor in the high-end space and superior logic packing capability. Also new is the production release of the Altera® SDK for OpenCL*.
OpenCLTM and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
- Key new features
- Compilation time improvement
- Performance advantage
- Logic utilization advantage
- High-level design tools:
- Intellectual property (IP) support
- Device support
- Getting started
- An average of 25 percent faster compilation
- Improvements in multicore compilation support
- Fitter improvements that unlock the fastest silicon performance in the industry
- Higher logic packing capability than our nearest competitor
- Production release of the Altera SDK for OpenCL
- Enhancements to the Qsys system integration tool, including:
- Support for the ARM® TrustZone® technology plus Advanced Peripheral Bus (APBTM) and High-Performance Bus (AHBTM)
- Support for VHDL bus functional models (BFMs)
- Enhancements to Transceiver Toolkit, including:
- Bit error checking for Stratix® V FPGAs
- Ability to measure and report the data rates of each active transceiver channel
- Enhancements to the SignalTapTM II logic analyzer, including:
- Ability to change basic trigger operations without recompiling
- Cross-triggering from an Altera SoC hard processor system (HPS) event
- Programmer Object File (POF) support for most 28 nm devices
- Simplified process for upgrading IP cores
- Simplified software and device family installation with the new installer
- New software notification center that provides convenient web-based compilation status monitoring and notification emails
Figure 1: Compilation Improvement in Quartus II Software v13.0 vs. Quartus II Software v12.1 on a Set of Internal Benchmark Designs
Quartus II software v13.0 has improved its parallel logic placement algorithms to scale even better with the number of cores on your multiprocessor machine. Designs that require more aggressive fitter effort settings see the most improvements with no impact on fMAX. Figure 1 illustrates the compilation time improvement across a set of internal benchmark designs.
Figure 2: Relative Performance of Stratix V FPGA vs. the Competing High-End FPGA Across Various Speed Grades
The Quartus II software is able to pack more logic into an FPGA than competing design tools.
Figure 3: Logic Utilization in the High-End Stratix V FPGA vs. the Competing High-End FPGA
Figure 3 shows that in our high-end devices – in this case a Stratix V FPGA (5SGXMA7K2F40C2) – a sample OpenCore design (oc_xge_mac) can be instantiated and successfully placed and routed 30 percent more times with the Quartus II software than in a competing high-end FPGA of an equivalent size using the latest competing design tools.
Figure 4: Logic Utilization in the Low-Cost Cyclone V FPGA vs. the Competing Low-Cost FPGA
Figure 4 shows the same OpenCore design placed and routed in an Altera low-cost Cyclone® V FPGA (5CGXFC7D6F31C6) using the Quartus II software. In this case, 35 percent more cores can be successfully instantiated and placed and routed compared to a competing low-cost FPGA of an equivalent size using the latest competing design software. Both figures illustrate that Altera devices consume less logic per core and are able to implement more cores per device.
Combining the Open Computing Language (OpenCL) standard, an open royalty-free parallel programming model, with the parallel performance capability of Altera FPGAs provides a powerful system acceleration solution. The Altera SDK for OpenCL provides a design environment for you to easily implement OpenCL applications on FPGAs. The Altera SDK for OpenCL abstracts away the complexity of FPGA design and allows software programmers to program C for FPGAs. C code can easily be leveraged to automatically generate an FPGA implementation without having to convert it to HDL.
The Altera SDK for OpenCL is in full production release. To discover the high-performance, power-efficient acceleration that OpenCL provides with FPGAs, download the Altera SDK for OpenCL and buy a board (OpenCL license included) to get started.
To learn more about OpenCL for Altera FPGAs, you can:
- Visit the OpenCL for Altera FPGAs: Accelerating Performance and Design Productivity page
- Read the Implementing FPGA Design with the OpenCL Standard (PDF) white paper
Design for Higher Performance and Lower Power with OpenCL on Altera FPGAs (for Software Developers)
Watch this webcast to understand:
Accelerate Performance and Design Productivity with OpenCL on Altera FPGAs (for Hardware Developers)
Watch this webcast to understand:
Qsys, Altera’s next-generation system integration tool, will save you significant time and effort throughout your FPGA design cycle by automatically connecting together IP functions and subsystems. Qsys is powered by an FPGA-optimized network-on-a-chip (NoC) technology, delivering higher performance, improved design reuse, and faster verification compared to its predecessor, SOPC Builder. For more information on migrating from SOPC Builder to Qsys, refer to SOPC Builder to Qsys Migration Guidelines (PDF).
Quartus II software v13.0 introduces several feature enhancements for Qsys, including:
- APB support for HPS debug
- AHB non-bursting slave support
- ARM TrustZone technology support, which brings a system-wide approach to security on high-performance ARM-based computing platforms
- Auto-insertion of Avalon® Streaming (Avalon-ST) adaptors during system generation
- VHDL bus functional models (BFMs)
Implementing SoC Systems in Qsys
Altera’s DSP Builder, along with MathWorks’ MATLAB Simulink tools, allows you to go from system definition and simulation of digital signal processing (DSP) datapaths to hardware implementation in a matter of minutes. DSP Builder works within Simulink to automatically generate VHDL files and Tcl scripts for FPGA synthesis, hardware implementation, and simulation.
DSP Builder lets you easily implement high-performance fixed- and floating-point algorithms, such as matrix equations, fast Fourier transforms (FFTs), vector dot products, and Black-Scholes. To learn more, read the following white papers from BDTI, an independent technology analysis firm:
- An Independent Evaluation of Floating-point DSP Energy Efficiency on Altera 28 nm FPGAs (PDF)
- An Independent Analysis of Floating-Point DSP Design Flow and Performance on Altera 28 nm FPGAs (PDF)
The new features in DSP Builder v13.0 includes the following:
- New Math.h functions with enhanced precision and rounding parameterization, including logarithm and probability
- Parameterizable FFT blocks, which allow fixed- or floating-point FFTs
- More efficient folding capability and improved resource sharing
Implementing FFTs with DSP Builder and MATLAB/Simulink
Please refer to the What's New for IP in v13.0 Release page to find out more.
|Stratix V FPGAs||
|Arria V FPGAs||
|Cyclone V FPGAs||
|Cyclone V SoCs||
Altera provides instructor-led and online classes to help you successfully design with Altera products. Here are some classes you can take:
Instructor-Led (click here for the full list):
- The Quartus II Software Design Series: Foundation
- Parallel Computing with OpenCL
- Designing with DSP Builder Advanced Blockset
- Introduction to the Qsys System Integration Tool
- Video Design Framework Workshop
Online (click here for the full list):
- What’s New in the Quartus II Software Version 13.0 (30 minutes)
- Introduction to Parallel Computing with OpenCL (30 minutes)
- Writing OpenCL Programs for Altera FPGAs (1 hour)
- SoC Hardware Overview Part 1 (1 hour) and Part 2 (30 min)
- Advanced System Design Using Qsys (1.5 hours)
Both the free Quartus II Web Edition software and Quartus II Subscription Edition software are available for download.
The Quartus II Web Edition software and ModelSim®-Altera Starter Edition simulation tool do not require a license file.
The Quartus II Subscription Edition software includes a free 30-day trial, and will require a license after the 30-day period. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore. If you purchase the Quartus II Subscription Edition software, you will receive:
- The Quartus II software
- The ModelSim-Altera Starter edition
- A full license to the IP Base Suite, which includes 15 of Altera’s most popular IP, including DSP and memory cores
Follow these three steps to get started:
- Download the Quartus II software with the new and improved Quartus II software installer
- Download the Quartus II Subscription Edition software (includes free 30-day trial)
- Download the Quartus II Web Edition software (free and no license required)
- Install the Quartus II software
- Start evaluation