Switching From ASIC Design
Although the underlying structure of FPGAs is different than ASICs, Quartus® II software provides methodologies and features that enable ASIC designers to successfully design for Altera® FPGAs and structured ASICs with high performance and productivity. As Altera FPGAs have evolved to become closer in application space to ASICs, FPGA design flows have become fundamentally similar to ASIC design flows. Also, Quartus II software offers some innovative technologies to speed system design and take advantage of the programmable nature of FPGAs for in-system verification. This page provides an overview for ASIC designers moving to FPGA design. These additional resources are also available:
FPGA and Structured ASIC Device Options
Altera’s latest generation of FPGAs includes larger logic densities and comprehensive system-level features, and are based on leading-edge process technologies. Altera’s low-cost HardCopy® series structured ASICs offer the same FPGA features at a lower cost, with higher performance and lower power consumption to further push into custom ASIC application spaces. You can now use the same Altera Quartus II design software to design for FPGAs and HardCopy series structured ASICs from the beginning of a design cycle, with predictable performance and power consumption. When designing for HardCopy Stratix® devices, you can use a pin- and resource-compatible Stratix FPGA for in-system functional verification and to test board designs faster.
Overview of ASIC vs. FPGA Design Flows
The Quartus II software supports the same basic design, register transfer level (RTL) synthesis, and place-and-route and verification flows used by ASIC designers. However, it does not require some of the physical design and test design steps required for custom ASIC designs (as shown in Figure 1).
Figure 1. FPGA and ASIC Design Flows Fundamentally Similar
Scan insertion and clock tree synthesis are not required in FPGA design flows because of the inherent design of Altera FPGAs. In FPGA design flows, place-and-route is performed by the customer using the FPGA vendor place-and-route tools. In ASIC design, place-and-route and physical design verification such as crosstalk analysis between internal device signals may be performed by the customer or handed off to an ASIC foundry for implementation.
Developing ASICs requires careful design and placement of I/O cells to support the latest complex I/O standards with good signal integrity on all pins. You can use Quartus II design software to assign logic to configurable I/O cells with a simple spreadsheet-like interface assignment editor or a script. Quartus II software can also perform a quick check to validate pin assignments and corresponding I/O standard assignments up front to ensure proper operation.
ASIC testing and fault coverage are important parts of the ASIC development process. Testing involves the desired design functionality and the design of the ASIC, and uses boundary scan insertion, built-in-self-test (BIST), signature analysis, Iddq, and automatic test pattern generation (ATPG) techniques. FPGAs already include boundary scan logic as opposed to ASIC design flow where you must insert boundary scan logic and simulate it on top of the actual design logic. FPGAs have already been extensively tested during manufacturing; in FPGA design flows, you can focus on testing design functionality and timing requirements and do not need to perform device design tests such as crosstalk analysis.
Altera’s FPGAs include advanced, low-skew clock networks for clock distribution within the device. The FPGA designer must give up the ASIC designer's freedom to implement fully custom clock networks; however, the pre-defined clock tree structure in an FPGA enormously simplifies the design process and satisfies a majority of applications.
RTL Coding
When moving from ASIC design to FPGA design, you should take care to employ synchronous design practices. Following synchronous design practices is essential for long-term reliable operation and to make the design portable for implementation in different device speed grades or device architectures. To support ASIC designers, the Quartus II software includes integrated design rule checking features to enforce synchronous design practices.
Hierarchical Design
To support ASIC designers, the Quartus II software supports the LogicLock™ block-based design methodology, which is similar to the block-based design flows used in ASIC design flows. Using the LogicLock methodology, you can partition a design into several functional blocks and assign them to individual team members for independent design, optimization, and implementation. These blocks can then be imported into a top-level system design while maintaining design performance of the individual blocks. Optimized blocks may be reused in subsequent projects with the same performance.
System-Level Design
Quartus II software provides innovative features for rapid system design and hardware/software trade-off analysis. A broad array of off-the-shelf intellectual property (IP) cores is now available for system design in Altera FPGAs. This IP portfolio includes embedded processors, communications functions, optimized digital signal processing (DSP) functions, as well as interfaces and peripherals.
Features such as the Altera SOPC Builder software, included in the Quartus II software, automate adding, parameterizing, and linking IP cores into complete systems. A key element of SOPC Builder is its ability to enable early-in-the-design-process testing of hardware and software interactions through testbench files and simulation models before any hardware prototypes are constructed. You can use the rapid system-generation features of SOPC Builder to perform tradeoff analysis of which functions should be implemented in hardware and which functions should be implemented in embedded software.
Timing Closure and ECO Support
Reaching timing closure is critical in any ASIC or FPGA design flow. The Quartus II software now includes automated tools and “power tools” that offer ASIC-like control. For example, Altera’s Quartus II software includes a suite of physical synthesis optimizations such as automatic register duplication and register retiming to tune design performance. Quartus II users can also manually duplicate registers to reduce fan-out on critical paths and make path-based assignments on critical timing paths in a design. The Quartus II software timing closure floorplan editor displays timing between any two node locations in the floorplan and can be used to manually adjust logic placement for optimum timing.
In a typical engineering project development cycle, the specification for the programmable logic portion is likely to change when engineering development begins or when all system elements are being integrated. These last-minute design changes are commonly referred to as engineering change orders (ECOs). ECOs are small changes to the functionality of a design, after the design has been fully compiled (that is, synthesis and place-and-route are completed). ECO support is a common element in ASIC design flows; the Quartus II software offers support for implementing ECOs on the HDL and netlist level using incremental fitting and chip planner features.
Scripting Capabilities
ASIC design flows are typically driven by custom scripts or make files. FPGA designers can now find the same kind of capability in the Quartus II software. You can now run the Quartus II software from a GUI or command-line interface. Quartus II software supports a subset of the popular Synopsys design constraint (SDC) syntax used by many ASIC development tools to enter design constraints. Quartus II software also includes a new tool command language (Tcl)-based application programming interface (API) for scripting custom design flows.
EDA Verification Tool Support
ASIC designers trying FPGA design for the first time will find that many of their favorite ASIC verification tools can be used in Quartus II design flows. The Quartus II software can output netlists for analysis by all the leading EDA static timing analysis, HDL simulation, board-level timing analysis, and signal integrity analysis software used in typical ASIC design flows.
In-System Verification
There is no substitute for real-time in-system verification. By their very nature, FPGAs offer advantages over ASICs for in-system verification. Besides the obvious benefit of being able to make rapid FPGA design iterations to test in-system immediately, FPGA design tools such as Altera's Quartus II software offer the ability to seamlessly insert embedded logic analyzer functionality into designs. Quartus II software can also incrementally route debug signals to pins without changing HDL source files. Design fixes can now be implemented and tested in the lab using chip planner functions to view detailed design implementation structures and make incremental modifications in just minutes.
Conclusion
As time-to-market pressures increase, ASIC mask and development costs rise, and FPGAs continue to increase in performance and system-level features, more and more traditionally ASIC designers are designing with Altera FPGA and structured ASICs. Quartus II software is adapting to the needs of these ASIC designers by providing a similar development environment, offering ASIC-level performance and features, and offering advantages in system design and in in-system verification to further improve time-to-market benefits for FPGA designs.
|
Literature
> 
