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| Results for 'stratix_iii_ki' |  |
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| Results 1 - 10 of about 13. |
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| 1 | Internal Error: Sub-system: FSAC, File: /quartus/fitter/fsac ... Internal Error: Sub-system: FSAC, File: /quartus/fitter/fsac/fsac_titan_dqs_util. cpp, Line: 1700. DLL clk input should be fed by a PLL clk. www.altera.com/support/kdb/solutions/rd11222006_265.html - 28k - 2006-12-01 - Source: Altera |
| 2 | Are there any known issues with the On-Chip Clamp Diode ... Are there any known issues with the On-Chip Clamp Diode assignments in the Quartus II software versions 9.1 SP2 and earlier? www.altera.com/support/kdb/solutions/rd04092010_488.html - 30k - 2010-04-12 - Source: Altera |
| 3 | Are there known issues regarding the Stratix III Error Detection ... Are there known issues regarding the Stratix III Error Detection CRC feature that may result in incorrect MLAB operation? www.altera.com/support/kdb/solutions/rd07012009_883.html - 30k - 2009-07-02 - Source: Altera |
| 4 | Stratix III Device Handbook: Known Issues Stratix III Device Handbook: Known Issues. www.altera.com/support/kdb/solutions/rd04012008_768.html - 33k - 2009-06-01 - Source: Altera |
| 5 | Why is there a voltage drop in single-ended I/O standards when ... Why is there a voltage drop in single-ended I/O standards when located on dedicated differential input pins on side I/O banks in Stratix III devices for designs ... www.altera.com/support/kdb/solutions/rd02082009_485.html - 30k - 2009-02-15 - Source: Altera |
| 6 | Do Stratix III left and right I/O banks support the altmemphy ... Do Stratix III left and right I/O banks support the altmemphy megafunction? www.altera.com/support/kdb/solutions/rd10092006_525.html - 28k - 2007-09-04 - Source: Altera |
| 7 | What are the maximum clock rates for memory interfaces supported ... What are the maximum clock rates for memory interfaces supported in Stratix® III low-power devices? www.altera.com/support/kdb/solutions/rd01172007_852.html - 30k - 2007-04-10 - Source: Altera |
| 8 | Is there an issue with the sampling window timing in Stratix III ... Is there an issue with the sampling window timing in Stratix III devices when using an ALTLVDS receiver in non-DPA mode? www.altera.com/support/kdb/solutions/rd04122010_695.html - 31k - 2010-04-15 - Source: Altera |
| 9 | Has the Stratix III I4 industrial speed grade timing model been ... Has the Stratix III I4 industrial speed grade timing model been updated since the release of the Quartus II software version 9.0 SP2? www.altera.com/support/kdb/solutions/rd09232009_327.html - 28k - 2009-09-25 - Source: Altera |
| 10 | Are there any known issues with DDR2 High Performance (HP) ... Are there any known issues with DDR2 High Performance (HP) Controller On Chip Termination (OCT) Timing in Full Rate Mode when performing Read to Write transactions ... www.altera.com/support/kdb/solutions/rd01212009_111.html - 28k - 2009-03-19 - Source: Altera |
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