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Last Modified Version Found Version Found Version Fixed Version Fixed Document Title, Description, URL
2014-02-10 130000 13.0 130100 13.1 Why do the write, sector_erase or bulk_erase operations of ALTASMI_PARALLEL perform incorrectly?

Due to a problem in Quartus® II software versions 13.0 and 13.0sp1, the ALTASMI_PARALLEL doesn't conduct the correct sequence when the write, sector_erase or bulk_erase&n…
www.altera.com/support/kdb/solutions/rd12092013_489.html - 2013-12-11

2013-12-11 130001 13.0 SP1 0 Why is the enable_dpa_fifo parameter set to "UNUSED" in the generated file even if you enabled the DPA feature in the ALTLVDS_RX MegaWizard

You will see following parameter definition in the MegaWizard™ generated file although you already enabled DPA feature in ALTLVDS_RX "ALTLVDS_RX_component.enable_dpa_fifo…
www.altera.com/support/kdb/solutions/rd11212013_158.html - 2013-12-11

2013-12-11 130000 13.0 0 Error (175001): Could not place path required to route a signal from PLD core to the I/O pin

You may see this error in the Quartus® II software versions 13.0 and 13.1 when using Arria® V or Cyclone® V SoC devices.  This error occurs when you use Hard Processor System …
www.altera.com/support/kdb/solutions/rd11182013_646.html - 2013-12-11

2013-12-11 130001 13.0 SP1 0 What is the correct device part number used on the Arria V GX FPGA Starter Kit?

The correct device part number used on the Arria® V GX FPGA Starter kit is 5AGXFB3H4F35C4N This is incorrectly shown as 5AGXFB3H4F35C5N in the followi…
www.altera.com/support/kdb/solutions/rd10112013_488.html - 2013-12-11

2013-12-10 0 0 Why are there duplicates for the differential signals in the Pin Planner after I run the <variation name>_pin_assignments.tcl file?

Due to a problem in the Quartus® II software Pin Planner tool, some differential signals may appear twice in the Pin Planner for the UniPHY-based memory controller. For example, me…
www.altera.com/support/kdb/solutions/rd11192013_181.html - 2013-12-10

2013-12-10 130001 13.0 SP1 0 Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY?

Due to a problem in the Quartus® II software version 13.1 and earlier, when using the hard memory controller with UniPHY, there might be a tWPRE timing violation when viewing the s…
www.altera.com/support/kdb/solutions/rd11282013_288.html - 2013-12-10

2013-12-10 130100 13.1 0 Why is the "Additional CK/CK# phase" option grayed out inside the MegaWizard GUI for the Stratix V device?

The "Additional CK/CK# phase" option is grayed out in the MegaWizard™ GUI because custom phase shifts for the memory clock is not supported for that device and protocol. The Strati…
www.altera.com/support/kdb/solutions/rd10282013_814.html - 2013-12-10

2013-12-10 130001 13.0 SP1 0 What is the maximum burst length for the hard memory controller?

The maximum burst length is 128 in the hard memory controller. If you require a wider width, it is recommended to use an adapter.
www.altera.com/support/kdb/solutions/rd12092013_826.html - 2013-12-10

2013-12-10 0 0 Critical Warning (308019): (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme.

When running the Design Assistant tool in the Quartus® II software, the following critical warning message may appear: Critical Warning (308019): (Critical) Rule C101: Gated clock…
www.altera.com/support/kdb/solutions/rd11202013_901.html - 2013-12-10

2013-12-10 0 0 How do I calculate the ECC for DDR3 UniPHY based controller?

The error correction code (ECC) calculation for UniPHY-based memory contollers is based on the Hamming Coding scheme. The Hamming Coding scheme derives the parity bits and app…
www.altera.com/support/kdb/solutions/rd04092013_850.html - 2013-12-10

2013-12-10 130001 13.0 SP1 0 Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller?

When running an RTL simulation for the UniPHY-based hard memory controller in Arria® V or Cyclone® V device, you may find local_cal_success go high but local_init_done st…
www.altera.com/support/kdb/solutions/rd11242013_620.html - 2013-12-10

2013-12-09 0 0 Error:286034 Cannot find Memory Initialization File or Hexadecimal (Intel-Format) File db/<name>.hdl.mif

Due to a problem in the Quartus® II software version 13.1, you may see this error message when you compile a revision whose name is different than the project name.
www.altera.com/support/kdb/solutions/rd12052013_480.html - 2013-12-09

2013-12-09 0 0 How do I report net delay violations?

To display net delay timing reports, run the report_net_delay command. The TimeQuest timing analyzer does not report net delay violations by default.  
www.altera.com/support/kdb/solutions/rd11152013_841.html - 2013-12-09

2013-12-09 0 0 How do I address hold time violations for paths where destination register is implemented inside a dedicated DSP block in Arria V devices?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see hold violations in Arria® V designs for paths where the source register is implemented using a st…
www.altera.com/support/kdb/solutions/rd12022013_628.html - 2013-12-09

2013-12-09 0 0 Why do I see a Fatal Error in the Quartus II software after routing my Stratix III PLL output directly to a device output pin?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see a fatal error if you connect a Stratix® III PLL clock output directly to a device outpu…
www.altera.com/support/kdb/solutions/rd12022013_718.html - 2013-12-09

2013-12-09 0 130100 13.1 Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_titan_atom_visitor_main.cpp, Line: 1966
Atom type not supported by PVA

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this Internal Error while running the PowerPlay Power Analyzer. 
www.altera.com/support/kdb/solutions/rd11172013_38.html - 2013-12-09

2013-12-09 130100 13.1 0 Error (12921): Please run Analysis and Synthesis (quartus_map) without the --recompile option before requesting Rapid Recompile Analysis & Synthesis

You may see this error message if you run Rapid Recompile for unsupported device families. Currently Rapid Recompile only supports Stratix® V devices.
www.altera.com/support/kdb/solutions/rd12032013_538.html - 2013-12-09

2013-12-09 130000 13.0 0 Internal Error: Sub-system: HDB, File: /quartus/db/hdb/hdb_inst_name.cpp, Line: 1613

Due to a problem in the Quartus® II software version 13.0 and later, you may see this internal error during the Fitter if your design has location assignments f…
www.altera.com/support/kdb/solutions/rd11252013_357.html - 2013-12-09

2013-12-09 130001 13.0 SP1 0 Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_power_region.cpp, Line: 2351

Due to a problem in the Quartus® II software version 13.0 SP1 and later, you may see this error if your design contains the following line in the Quartus II Settings File (.qs…
www.altera.com/support/kdb/solutions/rd10222013_699.html - 2013-12-09

2013-12-04 130200 13.1
Arria 10
Edition
0 Riviera-PRO Crashes When Compiling Altera PHYLite for Memory Megafunction HDL File

If, in the Quartus II software version 13.1a10 or later, you created an Altera PHYLite for memory megafunction example design and perform simulation using Riviera-PRO 2013.06, the…
www.altera.com/support/kdb/solutions/fb148228.html - 2013-12-06

2013-12-06 130001 13.0 SP1 0 Why does PCI Express link training fail intermittently ?

Due to a bug, you may see link training failure with the Hard IP for PCI Express® IP Core due to the transmission of corrupted TS1s. The Hard IP core LTSSM state cycles between the…
www.altera.com/support/kdb/solutions/rd11192013_905.html - 2013-12-06

2013-12-10 130001 13.0 SP1 130100 13.1 Issue with Configuration Space Bypass Mode Qsys Example Design for Arria V GZ Hard IP for PCI Express IP Core

The Configuration Space Bypass Mode Qsys example design for the Arria V GZ Hard IP for PCI Express IP does not work in the Quartus II 13.0 SP1 release. A required file, altera_pci…
www.altera.com/support/kdb/solutions/fb132607_a5gz.html - 2013-12-05

2013-12-04 120101 12.1 SP1 130100 13.1 Arria V GT CPRI IP Cores at Data Rate 9.8 Gbps Do Not Provide Transceiver Status on gxb_rx_pll_locked and gxb_rx_freqlocked Signals

In CPRI IP core variations that target an Arria V GT device and that run at a CPRI line rate of 9.8 Gbps, the transceiver status output signals gxb_rx_pll_locked and gxb_rx_freqlo…
www.altera.com/support/kdb/solutions/fb148889.html - 2013-12-05

2013-12-05 110100 11.1 130000 13.0 Cyclone V Hard IP for PCI Express IP Core May Fail Link Training

The Cyclone V Hard IP for PCI Express IP Core may fail link training and remain in the Detect.Quiet state. This failure is caused by an incomplete reset of the TX PMA which result…
www.altera.com/support/kdb/solutions/fb113954.html - 2013-12-05

2013-12-05 110100 11.1 130001 13.0 SP1 CvP Update Not Available at Gen2 Rate for the Arria V Hard IP for PCI Express IP Core

You cannot use the Configuration via Protocol (CvP) update mode at the Gen2 data rate for the Arria VHard IP for PCI Express IP Core.
www.altera.com/support/kdb/solutions/fb125216.html - 2013-12-05

2013-12-05 120101 12.1 SP1 130000 13.0 Link Training Failure in Arria V Avalon-MM Hard IP for PCI Express Due To Incorrect PMA Settings

Version 12.1 SP1 of the Quartus II software specifies incorrect values for many pre-emphasis and VOD settings, resulting in link training failures. This issue affects all Arria V …
www.altera.com/support/kdb/solutions/fb103502.html - 2013-12-05

2013-12-04 130100 13.1 0 Demonstration Testbench for Some CPRI IP Core Verilog HDL Variations Fails Simulation of HDLC Functionality

If you generate a Verilog HDL model for a CPRI IP core variation that has a data rate of 4.915 Gbps, 6.144 Gbps, or 9.8 Gbps and targets an Arria V GZ, Arria V GT, or Stratix V de…
www.altera.com/support/kdb/solutions/fb153794.html - 2013-12-05

2013-12-05 130000 13.0 130001 13.0 SP1 Gen2 Link Issues for Cyclone V Hard IP for PCI Express IP Core

Gen2 links experience a high error rate for the Cyclone V Hard IP for PCI Express IP Core.
www.altera.com/support/kdb/solutions/fb134347.html - 2013-12-05

2013-12-05 100100 10.1 130100 13.1 Configuration Via Protocol (CvP) Not Working for Arria V GZ Hard IP for PCI Express x2 Variants

Arria V GZ Hard IP for PCI Express variants using CvP and x2 configuration fail during link training initialization.
www.altera.com/support/kdb/solutions/fb99538.html - 2013-12-05

2013-12-05 130001 13.0 SP1 130100 13.1 Issue with Configuration Space Bypass Mode Qsys Example Design for Stratix V Hard IP for PCI Express IP Core

The Configuration Space Bypass Mode Qsys example design for the Stratix V Hard IP for PCI Express IP does not work in the Quartus II 13.0 SP1 release. A required file, altera_pcie…
www.altera.com/support/kdb/solutions/fb132607.html - 2013-12-05

2013-12-05 100000 10.0 130100 13.1 Cyclone IV GX CPRI IP Cores at Data Rates Above 0.6144 Gbps Have Wrong TX Transceiver Clock Connection

In CPRI IP core variations that target a Cyclone IV GX device and that run at a CPRI line rate of 1.2288, 2.4576, or 3.072 Gbps, the TX transmitter reference clock input signal is…
www.altera.com/support/kdb/solutions/fb143483.html - 2013-12-05

2013-12-04 130100 13.1 0 CPRI IP Core Demonstration Testbench Does Not Support Aldec Riviera-PRO Simulator

The CPRI IP core demonstration testbench cannot simulate successfully with the Aldec Riviera-PRO simulator.
www.altera.com/support/kdb/solutions/fb158226.html - 2013-12-04

2013-12-04 0 0 Why is my Avalon-MM mode PCI Express core not resetting my logic correctly?

When using the Avalon Memory  Mapped Interface version of the Hard IP for PCI® Express core, "reset_status" interface signal is "Active Low".NOTE: with Avalon Streaming I…
www.altera.com/support/kdb/solutions/rd11282013_15.html - 2013-12-04

2013-12-03 130100 13.1 0 Arria V, Cyclone V, and Stratix V CPRI IP Core Autorate Negotiation Testbench Fails Simulation in the Synopsys VCS MX Simulator

CPRI IP core variations that target an Arria V, Cylcone V, or Stratix V device fail simulation with the autorate negotiation testbench in the Synopsys VCS MX simulator. Following …
www.altera.com/support/kdb/solutions/fb154656.html - 2013-12-04

2013-12-04 120100 12.1 0 Why do I experience intermittent link up problems when using the Stratix V or Arria V GZ Hard IP for PCI Express Gen 2 core?

There is an issue when using the Stratix® V or Arria V GZ Hard IP for PCI Express® IP core, where the link does not consistently come up.  This issue is seen when the cor…
www.altera.com/support/kdb/solutions/rd07232013_512.html - 2013-12-04

2013-12-04 130102 13.1
Update2
0 Arria 10 Gen3 x2 Example Design Simulation Issue

The Arria 10 Gen3 x2 example design might timeout when performing an MSI DMA Read and issue the following error message: INFO: 109129 ns TASK:chained_dma_test INFO: 109129 ns …
www.altera.com/support/kdb/solutions/fb157170.html - 2013-12-04

2013-12-04 130102 13.1
Update2
0 Arria 10 Hard IP for PCI Express IP Core Support for x2 Variants

The Arria 10 Hard IP for PCI Express user guides indicate that x2 support is generally unavailable. However, x2 support is available for almost all configurations. The exception i…
www.altera.com/support/kdb/solutions/fb157200.html - 2013-12-04

2013-12-04 0 0 Critical Warning: parameter 'invalid_code_flag_only' of instance '...|av_hssi_8g_rx_pcs_rbc' has illegal value '' assigned to it.

You may see the following synthesis message when implementing the Arria® V Hard IP for PCI® Express in Quartus® II software versions 13.1 and earlier. Info (10648): …
www.altera.com/support/kdb/solutions/rd12022013_509.html - 2013-12-04

2013-12-04 0 130100 13.1 Error (175001): Could not place Hard IP Error (10104): Unable to find a path between I/O pad and PINPERST port of PCI Express Hard IP.

Quartus® II software reports this fitter error when you make an incorrect nPERSTL* pin to PCI Express Hard IP location assignment in Cyclone® V devices.Pin nPERSTL0 is associa…
www.altera.com/support/kdb/solutions/rd12042013_909.html - 2013-12-04

2013-12-04 130001 13.0 SP1 130100 13.1 Example Design for Avalon-MM 256-Bit Hard IP for PCI Express Not Working

The example design for the Avalon-MM 256-Bit Hard IP for PCI Express does not work in simulation or hardware for 13.0 SP1.
www.altera.com/support/kdb/solutions/fb131587.html - 2013-12-04

2013-12-03 130001 13.0 SP1 0 Error: Please specify correct phase shifts

You may encounter this error when instantiating the Altera_PLL megafunction with certain output clock phase shift settings. For example, an ALTLV…
www.altera.com/support/kdb/solutions/rd07042013_614.html - 2013-12-03

2013-12-03 130200 13.1
Arria 10
Edition
0 100G Interlaken MegaCore Function User Guide Provides Insufficient Information to Connect Arria 10 TX PLL

According to the 100G Interlaken MegaCore Function User Guide, user logic should drive the tx_pll_locked input signal to an Arria 10 100G Interlaken IP core with the logical AND o…
www.altera.com/support/kdb/solutions/fb171345a.html - 2013-12-03

2013-12-03 130200 13.1
Arria 10
Edition
0 40-100GbE MAC and PHY IP Core Fails Attempted Update to Quartus II Software v13.1 Arria 10 Edition

Designs that contain a 40- and 100-Gbps Ethernet Mac and PHY IP core fail the IP upgrade process in the Quartus II software v13.1 Arria 10 Edition. This IP core does not support t…
www.altera.com/support/kdb/solutions/fb165629.html - 2013-12-03

2013-12-03 130200 13.1
Arria 10
Edition
0 50G Interlaken MegaCore Function User Guide Provides Insufficient Information to Connect Arria 10 TX PLL

According to the 50G Interlaken MegaCore Function User Guide, user logic should drive the tx_pll_locked input signal to an Arria 10 100G Interlaken IP core with the logical AND of…
www.altera.com/support/kdb/solutions/fb171345b.html - 2013-12-03

2013-12-03 0 0 Error: can't read "safebit": no such variable

You may get this error messages when executing the BSDL Customizer tcl files with unsupported devices. If you open the BSDL Customizer tcl files, the device string for newer d…
www.altera.com/support/kdb/solutions/rd07262011_217.html - 2013-12-03

2013-12-03 120100 12.1 130200 13.1
Arria 10
Edition
100G Interlaken MegaCore Function User Guide Erroneously Indicates MetaFrameLength Can Be Less Than 128 64-Bit Words

According to the 100G Interlaken MegaCore Function User Guide, the Meta frame length in words parameter can have a value of 64 8-byte words. However, this is incorrect. The minimu…
www.altera.com/support/kdb/solutions/fb166520a.html - 2013-12-03

2013-12-03 130000 13.0 130200 13.1
Arria 10
Edition
50G Interlaken MegaCore Function User Guide Erroneously Indicates MetaFrameLength Can Be Less Than 128 64-Bit Words

According to the 50G Interlaken MegaCore Function User Guide, the Meta frame length in words parameter can have a value of 64 8-byte words. However, this is incorrect. The minimum…
www.altera.com/support/kdb/solutions/fb166520b.html - 2013-12-03

2013-12-03 0 0 Arria® 10 Device Handbook: Known Issues

No reported issues at this time.
www.altera.com/support/kdb/solutions/rd07302013_646.html - 2013-12-03

2013-12-02 130000 13.0 0 Internal Error: Sub-system: SEDQ, File: /quartus/sld/sedq/sedq_number.cpp, Line: 332

Due to a problem in the Quartus® II software version 13.0 and later, you may see this error when you add nodes to the Data tab of the SignalTap™ II Logic Analyzer. E…
www.altera.com/support/kdb/solutions/rd11142013_789.html - 2013-12-02

2013-12-02 120100 12.1 0 Error (175001): Could not place ATX PLL

Due to a problem in the Quartus® II software version 12.1 and later, you may see fitter problems placing the ATX PLL when migrating from earlier versions of the Quartus II sof…
www.altera.com/support/kdb/solutions/rd10222013_204.html - 2013-12-02

2013-12-02 130000 13.0 0 Error: TB_Gen: More than one reset ports found

Due to a problem in Quartus® II software version 13.0 and later, you may see this error message when you generate a Qsys testbench. This error occurs if a Qsys component has an exp…
www.altera.com/support/kdb/solutions/rd11062013_652.html - 2013-12-02

2013-12-02 120000 12.0 0 Error (170025): Fitter requires that more entities of type <cell type> be placed in a region than are available in the region

Due to a problem is the Quartus® II software version 12.1 and later, you may see this error if the fitter has promoted a high fan-out clock to a regional clock instead of a gl…
www.altera.com/support/kdb/solutions/rd10302013_719.html - 2013-12-02

2013-12-02 130001 13.0 SP1 130100 13.1 Failed to load Altera_PLL v13.0 Megawizard for Arria V GZ

Due to a problem in the Quartus® II software version 13.0 SP1, you may see this error when opened the Altera PLL and you have only installed the Arria® V GZ device library.
www.altera.com/support/kdb/solutions/rd10112013_834.html - 2013-12-02

2013-12-02 0 0 (mgcld) UNSUPPORTED: "alteramtivsim" (PORT_AT_HOST_PLUS ) <port>@<server> (License server system does not support this feature.)

You may see this error when using ModelSim-Altera software if you have a corrupt license.
www.altera.com/support/kdb/solutions/rd11132013_584.html - 2013-12-02

2014-02-05 130100 13.1 0 Preamble Pass-through Mode Does Not Work with PFC Frames

Low Latency Ethernet 10G MAC designs with Enable preamble pass-through mode and Enable priority-based flow control (PFC) options turned on, will produce incorrect data or pause fr…
www.altera.com/support/kdb/solutions/fb166749.html - 2013-12-01

2014-06-30 0 0 Why do I see increased low frequency jitter when using the ATX PLL of Stratix V or Arria V GZ transceiver devices?

Due to a problem in the Quartus® II software you may see increased low frequency jitter when using the ATX PLL of Stratix® V or Arria® V GZ transceiver devices. The Quartus II so…
www.altera.com/support/kdb/solutions/rd11112013_835.html - 2013-11-29

2013-11-29 0 0 How can I use the Altera Secure File Transfer System (SFTA) to upload and download files?

To securely transfer large files to and from Altera you must use the Altera Secure File Transfer System (SFTA). If you are a first time user or your SFTA account has become inacti…
www.altera.com/support/kdb/solutions/rd11192013_686.html - 2013-11-29

2013-11-27 130100 13.1 0 Incorrect Register Value After Tx/Rx Reset

Some of the Low Latency 10GbE MAC registers will have incorrect value after being reset with tx_rst_n or rx_rst_n.. This issue affects the following registers: 0x0FE-0x0FF: Tx Und…
www.altera.com/support/kdb/solutions/fb151913.html - 2013-11-28

2014-02-05 130100 13.1 0 Transmit Path: CRC Insertion Must Be Turned On

For Low Latency Ethernet 10G MAC designs that turn on PTP 1-step clock support, you must enable CRC insertion. If you do not configure CRC insertion, you may get incorrect data fr…
www.altera.com/support/kdb/solutions/fb160653.html - 2013-11-28

2013-11-26 120100 12.1 130100 13.1 100G Interlaken IP Core itx_chan Signal Must Be Held Steady for the Duration of the Packet

User logic must hold the 100G Interlaken IP core itx_chan signal steady for the duration of the packet on the TX user data transfer interface, from the time user logic asserts the…
www.altera.com/support/kdb/solutions/fb142831a.html - 2013-11-27

2013-11-27 0 0 How do I generate Raw Programming Data (.rpd) files for EPCS or EPCQ configuration devices which only contain configuration data?

A .rpd file which is generated from a Programmer Object File (.pof) or JTAG Indirect Configuration file (.jic) is always the same size as the EPCS or EPCQ configuration device whic…
www.altera.com/support/kdb/solutions/rd11182013_802.html - 2013-11-27

2013-11-26 130000 13.0 130100 13.1 40-100GbE MAC and PHY IP Core MegaCore Function User Guide Lists Wrong Module Names in Resource Utilization Tables

In the 40- and 100-Gbps Ethernet Mac and PHY MegaCore Function User Guide, the resource utilization numbers for 40GbE variations appear correctly in the tables, but the module nam…
www.altera.com/support/kdb/solutions/fb153201.html - 2013-11-27

2013-11-26 130000 13.0 130100 13.1 50G Interlaken IP Core itx_chan Signal Must Be Held Steady for the Duration of the Packet

User logic must hold the 50G Interlaken IP core itx_chan signal steady for the duration of the packet on the TX user data transfer interface, from the time user logic asserts the …
www.altera.com/support/kdb/solutions/fb142831b.html - 2013-11-27

2013-11-27 130000 13.0 0 IP Compiler for PCI Express SDC Constraint Generates Warnings

The following SDC constraint in the automatically generated Synopsys Design Constraints (.sdc) file for the IP Compiler for PCI Express generates warning messages: set_clock_group…
www.altera.com/support/kdb/solutions/fb134563.html - 2013-11-27

2013-11-27 130001 13.0 SP1 130100 13.1 Why does the Altera PLL fail to lock in simulation after installing the dp5 patch?

The Altera® PLL simulation model may fail to operate correctly and fail to assert the locked signal after installing the dp5 patch for version 13.0sp1 of the Quartus® II software.Y…
www.altera.com/support/kdb/solutions/rd11192013_957.html - 2013-11-27

2013-11-27 0 0 What is the number of program/erase cycles for a serial configuration (EPCS) device or a quad-serial configuration (EPCQ) device?

The EPCS and EPCQ devices support more than 100,000 program/erase cycles per sector.
www.altera.com/support/kdb/solutions/rd10312013_646.html - 2013-11-27

2014-05-13 120100 12.1 0 Why is the Read Device Dummy Clock instruction unreliable when using the QUAD and DUAL IO options on the ALTASMI_PARALLEL megafunction?

When the  read_dummyclk input of the ALTASMI_PARALLEL megafunction is asserted, the megafunction performs a read of the non-volatile control register of the EPCQ configur…
www.altera.com/support/kdb/solutions/rd11192013_10.html - 2013-11-27

2013-11-27 130001 13.0 SP1 0 What is the correct part number used on the Arria V FPGA Development Kit?

The correct device part number for the FPGA used on the  Arria® V FPGA Development kit  is a 5AGXFB3H6F40C5NES device. This is incorrectly shown as 5A…
www.altera.com/support/kdb/solutions/rd10112013_478.html - 2013-11-27

2013-11-26 130000 13.0 130100 13.1 50G Interlaken MegaCore Function User Guide Erroneously Indicates BurstMax Can Have Value Greater Than 256 Bytes

According to the 50G Interlaken MegaCore Function User Guide, MaxBurst can have a value of 512 bytes. However, this is incorrect. The only values that MaxBurst can have in this IP…
www.altera.com/support/kdb/solutions/fb158022.html - 2013-11-27

2013-11-27 100000 10.0 0 IP Compiler for PCI Express User Guide is Missing Description of lane_act[3:0] Signal

The IP Compiler for PCI Express User Guide does not describe the lane_act[3:0] signal. The following information is missing from the user guide: Lane active mode: This output sign…
www.altera.com/support/kdb/solutions/fb134541.html - 2013-11-27

2013-11-26 130100 13.1 0 40-100GbE MAC and PHY IP Core remote_fault_status and local_fault_status Signals Are Not Visible at Top Level in MAC-Only Variations

In MAC-only variations of the 40- and 100-Gbps Ethernet Mac and PHY MegaCore function, the remote_fault_status and local_fault_status signals are not visible in the top-level inte…
www.altera.com/support/kdb/solutions/fb154869.html - 2013-11-27

2013-11-27 0 0 Why does the Quartus II programmer display a different flash memory name when performing an Auto Detect when multiple flash memory devices are connected to the parallel flash loader (PFL)?

When multiple flash memory devices are connected to the PFL in MAX® devices, the Quartus® II programmer displays a different flash memory name when performing Auto Detect. Thi…
www.altera.com/support/kdb/solutions/rd10282013_187.html - 2013-11-27

2013-11-27 0 0 What is the data retention time for a serial configuration (EPCS) device or a quad-serial configuration (EPCQ) device?

The data retention time for an EPCS or EPCQ device is more than 20 years.
www.altera.com/support/kdb/solutions/rd10312013_363.html - 2013-11-27

2013-11-26 120100 12.1 0 RapidIO II IP Core Has Wrong Default TX VOD Setting in Arria V and Cyclone V devices

The RapidIO II IP core does not set the transceiver TX VOD value correctly in Arria V GX, Arria V GT, and Cyclone V devices. The default value violates the RapidIO specification. …
www.altera.com/support/kdb/solutions/fb163810.html - 2013-11-26

2013-11-26 130000 13.0 0 Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File hps_AC_ROM.hex

This critical warning may be displayed by the Quartus® II software for designs targeting SOC devices. The warning can safely be ignored as this file is not required by t…
www.altera.com/support/kdb/solutions/rd11252013_188.html - 2013-11-26

2013-11-26 0 0 Why does my USB debug Master not work in System console on the Cyclone V GX FPGA development kit

Due to a problem on the Cyclone® V GX FPGA Development Kit, when using the USB Debug Master core in Qsys, System console does not discover the master device when you…
www.altera.com/support/kdb/solutions/rd03202013_599.html - 2013-11-26

2013-11-26 130000 13.0 0 Why is clCreateSubBuffer defined in the Altera DSK for OpenCL cl.h but not in ateracl.lib

clCreateSubBuffer creates a buffer object from an existing buffer object, and it is defined in the Open CL specification 1-2.   Altera SDK for Open CL™ supports only the …
www.altera.com/support/kdb/solutions/rd11192013_30.html - 2013-11-26

2013-11-26 0 0 How do stop all warnings being seen as errors in DS-5?

If you remove –Werror complier option from Makefile, warnings will not be flagged as errors. 
www.altera.com/support/kdb/solutions/rd11182013_597.html - 2013-11-26

2013-11-25 120100 12.1 0 RapidIO II IP Core Does Not Declare Illegal Transaction Decode for MAINTENANCE Read Response With More Than 32 Bits of Payload

When the RapidIO II IP core receives a MAINTENANCE Read response with more than 32 bits of payload, the RapidIO II IP core MAINTENANCE module should declare an Illegal Transaction…
www.altera.com/support/kdb/solutions/fb169828.html - 2013-11-26

2013-11-26 130001 13.0 SP1 0 Why are the Memory preset settings missing in the Cyclone® V HPS Qsys GUI component?

Due to a problem in the Quartus® II software version 13.0 sp1, the memory presets setting are no longer available from the Qsys Hardware Processor System MegaWizard GUI in the…
www.altera.com/support/kdb/solutions/rd08122013_723.html - 2013-11-26

2013-11-25 120100 12.1 0 Port 0 Control 2 CSR Data Rate Support and Enable Fields All Have the Value of 1

The _GB_SUPPORT and _GB_ENABLE fields of the Port 0 Control 2 CSR (offset 0x154) are set by default to the value of 1. However, these fields should only be set to the value of 1 f…
www.altera.com/support/kdb/solutions/fb156607.html - 2013-11-26

2013-11-25 120100 12.1 130100 13.1 Control of RapidIO II IP Core EF_PTR Fields is Incorrect

The RapidIO II MegaCore Function User Guide states that the Extended features pointer parameter in the RapidIO II parameter editor controls the final EF_PTR in the chain of pointe…
www.altera.com/support/kdb/solutions/fb85398.html - 2013-11-26

2013-11-25 120100 12.1 130100 13.1 RapidIO II IP Core Does Not Support VHDL Models

The RapidIO II IP core does not support VHDL models. If you generate a RapidIO II IP core in VHDL, it cannot compile successfully. The RapidIO II MegaCore Function User Guide clai…
www.altera.com/support/kdb/solutions/fb79178.html - 2013-11-26

2013-12-02 130100 13.1 0 Possible Timing Failure on Designs Targeting Arria V and Cyclone V Devices

This problem affects DDR2, DDR3, and LPDDR2 SDRAM Controllers with UniPHY. DDR2, DDR3, and LPDDR2 soft interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience …
www.altera.com/support/kdb/solutions/fb165855.html - 2013-11-26

2013-11-25 120100 12.1 0 RapidIO II IP Core link-response Timeout Behavior Does Not Match Documentation

According to the RapidIO II MegaCore Function User Guide, after the RapidIO II IP core sends a link-request, if it times out waiting for a link-response, it sends another link-req…
www.altera.com/support/kdb/solutions/fb160419.html - 2013-11-26

2013-11-26 110000 11.0 0 RapidIO IP Core Has Wrong Default TX VOD Setting in Arria V and Cyclone V Devices

The RapidIO IP core does not set the transceiver TX VOD value correctly in Arria V (GX, GT, SX, and ST) and Cyclone V devices. The default value violates the RapidIO specification…
www.altera.com/support/kdb/solutions/fb162180.html - 2013-11-26

2013-11-26 130000 13.0 0 Why are the Altera OpenCL SDK definitions num_vector_lanes and num_copies not in the 13.0sp1 documentation?

The num_vector_lanes and num_copies definitions have changed name to more intuitive names num_simd_work_items num_compute_units  
www.altera.com/support/kdb/solutions/rd11192013_138.html - 2013-11-26

2013-11-26 120100 12.1 130001 13.0 SP1 Why can't my own coefficient be used by the FIR compiler GUI?

The documentation for the FIR Compiler II  GUI  in the Quartus® II software version 12.1 - 13.0, incorrectly describes the file format for the input coefficient…
www.altera.com/support/kdb/solutions/rd08122013_194.html - 2013-11-26

2013-11-25 130000 13.0 0 Long Term CK Jitter Exceeds Spec in HPS Memory Interface in Arria V and Cyclone V Devices

This problem affects DDR2, DDR3, and LPDDR2 products. DDR2, DDR3, and LPDDR2 interfaces using the HPS memory interface on Arria V or Cyclone V devices, produce a long term CK jitt…
www.altera.com/support/kdb/solutions/fb167412.html - 2013-11-25

2013-12-02 130100 13.1 0 Migrating UniPHY IP from 13.0 SP1 DP5 to 13.1 Resets GUI to Default Values

This problem affects DDR2, DDR3, LPDDR2, QDR II, RLDRAM II, and RLDRAM 3 UniPHY-based products. When a top-level EMIF wrapper generated in the Quartus II software version 13.0 SP1…
www.altera.com/support/kdb/solutions/fb168318.html - 2013-11-25

2013-11-27 130001 13.0 SP1 0 Cannot Reopen SDI II Wrapper File in MegaWizard

The MegaWizard Plug-In Manager does not recognize the Serial Digital Interface (SDI) II top level wrapper file when you choose Edit an existing custom megafunction variation. The …
www.altera.com/support/kdb/solutions/fb160625.html - 2013-11-20

2013-11-27 130000 13.0 0 Recovery Timing Violation

When you compile your designs with the Serial Digital Interface (SDI) II MegaCore function, you may encounter recovery timing violation. This violation is caused by the reset cont…
www.altera.com/support/kdb/solutions/fb147290.html - 2013-11-20

2013-11-27 130000 13.0 0 Half Duplex Operation on 10/100M Ethernet MAC Not Supported

The Triple Speed Ethernet designs that turn on the Enable MAC 10/100 half duplex support option do not enable the half duplex operation. The user interface may allow you to turn o…
www.altera.com/support/kdb/solutions/fb163263.html - 2013-11-20

2013-11-27 120100 12.1 130100 13.1 Inaccurate Receiver Video Format Detection for SDI Rx Protocol Only Instance

When you select SDI Rx protocol only instance, the reported receiver video format always defaults to the PAL (1/1.000) value. For example, rx_video_format value is 0x27 for both 1…
www.altera.com/support/kdb/solutions/fb158752.html - 2013-11-20

2013-11-27 130000 13.0 0 GXB 0 ppm Warning for SerialLite II Designs with Custom PHY

The Quartus II software will show the following warning for designs that use more than 1 channel between the SerialLite II MegaCore function and the Custom PHY IP during integrati…
www.altera.com/support/kdb/solutions/fb94561.html - 2013-11-20

2013-11-27 120100 12.1 130100 13.1 When Asserted, reg_burst_count Fails to Perform Burst Transaction

When asserted, the reg_burst_count signal fails to perform a burst transaction in designs using Audio Embed, Audio Extract, Clocked Audio Input, or Clocked Audio Output IPs.
www.altera.com/support/kdb/solutions/fb156550.html - 2013-11-20

2013-11-27 110000 11.0 120000 12.0 FIR Coefficient Reload May Get Delayed

FIR Compiler II intermittently inserts unnecessary delay registers between a coefficient storage register and the multiplier that uses that coefficient. This issue may cause the …
www.altera.com/support/kdb/solutions/fb46001.html - 2013-11-20

2014-06-30 0 0 Critical Warning (184043): Fitter was unable to find transceiver reconfiguration controllers

You may see this Quartus® II critical warning if you turn off the PROJECT_SHOW_ENTITY_NAME setting and your Stratix® V, Arria® V, or Cyclone® V design includes transceivers. The P…
www.altera.com/support/kdb/solutions/rd10292013_663.html - 2013-11-19

2013-11-19 130100 13.1 0 RapidIO IP Core Does Not Return ERROR Response Packet to MAINTENANCE Request with Illegal Size

When the RapidIO IP core receives a MAINTENANCE request with an illegal size (rdsize not equal to 4’b1000 for a MAINTENANCE read request, or wrsize not equal to 4’b1000 for a MAIN…
www.altera.com/support/kdb/solutions/fb167941.html - 2013-11-19

2013-11-19 130100 13.1 0 RapidIO IP Core Hangs After Receiving MAINTENANCE Read Response With DONE Status but No Payload

When the RapidIO IP core receives a MAINTENANCE read response with DONE status but without a payload, the IP core should indicate an error. However, the IP core hangs. Refer also …
www.altera.com/support/kdb/solutions/fb167940.html - 2013-11-19

2013-11-19 0 0 How do I calculate DFE power consumption using the Quartus II Power Play Power Analyzer (PPPA) and Early Power Estimator (EPE) for Stratix V and Arria V GZ devices?

Due to a limitation of the Quartus® II software version 13.1 and earlier, the Power Play Power Analyzer (PPPA) tool will not include Decision Feedback Equalizer (DFE) power consump…
www.altera.com/support/kdb/solutions/rd11182013_585.html - 2013-11-19

2013-11-19 110000 11.0 130100 13.1 RapidIO IP Core Qsys Design Example Simulation Warning

When you simulate the RapidIO Qsys design example, warning messages display. These messages complain of a missing rio_sys_onchip_memory2_0.hex file.
www.altera.com/support/kdb/solutions/fb101308.html - 2013-11-19

2013-11-19 110001 11.0 SP1 130100 13.1 RapidIO IP Core 5.0 Gbaud Variations Do Not Handle Out-of-Order Response Packets Properly

When a RapidIO IP core variation at 5.0 Gbaud receives out of order read responses on the RapidIO link, the IP core sends the wrong payload data on the I/O Avalon-MM slave interfa…
www.altera.com/support/kdb/solutions/fb133567.html - 2013-11-19

2013-11-19 0 0 Critical Warning: PLL clock *|divclk not driven by a dedicated clock pin or neighboring PLL source.

You may see the above critical warning when the reference clock to a UniPHY-based memory controller is sourced from a global clock routing resource. The global routing resource wil…
www.altera.com/support/kdb/solutions/rd11042013_699.html - 2013-11-19

2013-11-19 120100 12.1 130100 13.1 RapidIO IP Core Qsys Design Example Cannot Simulate with -novopt Flag Set

If you turn on the -novopt flag in the ModelSim simulator, the RapidIO Qsys design example fails while loading in the simulator.
www.altera.com/support/kdb/solutions/fb101226.html - 2013-11-19

2013-11-19 90100 9.1 0 Wrong Default Transceiver Equalization Setting in RapidIO IP Core in Some Device Families

The default value for the transceiver equalization setting in a RapidIO IP core should be the Low setting. The default Low setting supports adjustment upwards as you encounter sig…
www.altera.com/support/kdb/solutions/fb52169.html - 2013-11-19

2013-11-18 130000 13.0 0 What timing constraints are used by the Design Assistant?

The Quartus® II Design Assistant (DA) does not use any constraints from the Synopsys Design Constraints (.sdc) file. During processing you may see the following messages: Inf…
www.altera.com/support/kdb/solutions/rd11062013_975.html - 2013-11-18

2013-11-18 130000 13.0 130100 13.1 How do I list the IPs requiring upgrade using the command line?

The Quartus® II Help version 13.0 for ip_upgrade incorrectly displays: quartus_sh --ip_upgrade -list_ips
www.altera.com/support/kdb/solutions/rd11052013_522.html - 2013-11-18

2013-11-18 0 0 Why does my qsys-script command fail?
Error: invalid command name "< command name >"

qsys-script command fails if you do not include a package version. When running a qsys-script command you must perform one of the following actions: Specify the package v…
www.altera.com/support/kdb/solutions/rd10282013_107.html - 2013-11-18

2013-11-18 130000 13.0 130100 13.1 Why does the generation of the altsyncram IP from the command line fail?

Command line generation of the altsyncram IP component is not supported in the Quartus® II software version 13.0 and later. The chapter Command Line Scripting (PDF) in t…
www.altera.com/support/kdb/solutions/rd10312013_616.html - 2013-11-18

2013-11-18 120100 12.1 0 Error (184057): Fitter cannot read the .mif db/<name>.mif

Due to a problem in the Quartus® II Software version 12.1 and later, you may see this error message when you have multiple revisions in your design. The Quartus II software in…
www.altera.com/support/kdb/solutions/rd11012013_123.html - 2013-11-18

2013-11-18 110000 11.0 0 Which protocols are supported by Quartus II Floating License Server?

The Quartus® II software version 11.0 and later, uses the 10.x FLEXlm license manager. This software uses only the TCP/IP protocol. 
www.altera.com/support/kdb/solutions/rd11152013_923.html - 2013-11-18

2013-11-15 130000 13.0 0 Why does my register view stop responding in DS-5 when I use a peripheral map?

If the register view in Arm DS-5 Altera Edition is left open viewing the content of registers located within the FPGA fabric when a debugging session is closed,  the register …
www.altera.com/support/kdb/solutions/rd11122013_210.html - 2013-11-15

2013-11-15 120000 12.0 120100 12.1 Prefitter Not Instantiating io_clock_divider and DQSLB when DQSLB has No Associated EMIF Pins

This problem affects QDR II, and RLDRAM II products. For designs with x18 or x36 DQ groups, it is possible that the data pins do not require I/Os in all the DQ groups. When this h…
www.altera.com/support/kdb/solutions/fb79326.html - 2013-11-15

2013-11-15 130000 13.0 0 What is the size of the instruction cache on the HPS DMA Contoller in Cyclone V and Arria V SOC devices?

The instruction cache size of the ARM DMA-330  IP on Cyclone® and Arria® V series SOC devices is 512 bytes. The cache line size is 8 words (4 bytes each), resulting in a line…
www.altera.com/support/kdb/solutions/rd11122013_771.html - 2013-11-15

2013-11-15 130000 13.0 0 Error _mm_interconnect_0_addr_router.sv(196): (vlog-2730) Undefined variable: 'write_transaction'

Due to a problem in the Quartus® II software version 13.0 and later, a Qsys system that contains an AXI Default Slave but no AXI Slave will not compile and simulate correctly.…
www.altera.com/support/kdb/solutions/rd10312013_789.html - 2013-11-15

2013-11-15 0 0 Nios® II Boot to from EPCQ or EPCS in Quartus® II 13.0

The flow to configure Nios® II to boot from EPCS /EPCQ, generate required programming files, and program development kits can be complex.    Also due to some problem…
www.altera.com/support/kdb/solutions/rd11122013_865.html - 2013-11-15

2014-06-30 130100 13.1 0 Why does sof2flash, elf2flash,elf2hex and bin2flash fail when run on a Windows PC?

Due to a problem in the Quartus II software® version 13.1,  some of the NIOS® II EDS utilities may fail with no error output or messages when run on a Windows PC. The af…
www.altera.com/support/kdb/solutions/rd11112013_614.html - 2013-11-15

2013-11-26 0 0 Why do I see random read errors when using the ALTDQ_DQS2 megafunction?

Due to a problem in the ALTDQ_DQS2 megafunction in the Quartus® II software, when doing PVT testing, a glitch may occur at the output of the DQS logic block which may cause ra…
www.altera.com/support/kdb/solutions/rd10232013_290.html - 2013-11-15

2013-11-20 130100 13.1 0 Mentor Graphics AXI Verification IP AE in the Quartus II 13.1 release does not support QuestaSim 10.2b for windows

Mentor Graphics® AXI3™/AXI4™ Verification IP Suite Altera® Edition that is released with Quartus® II 13.1 will not work with QuestaSim® 10.2b for windows.
www.altera.com/support/kdb/solutions/rd10302013_617.html - 2013-11-15

2013-11-14 0 0 Is a board trace model required for UniPHY-based Controller?

No, board trace models are not needed for UniPHY-based controllers.
www.altera.com/support/kdb/solutions/rd08212012_926.html - 2013-11-14

2013-11-14 110100 11.1 0 Why is the efficiency of the Cyclone V and Arria V hard memory controller lower than expected for single port designs?

The Multi-Port Front End (MPFE) which is used with the Hard Memory Controller for Arria® V and Cyclone® V devices contains an arbiter which enables load balancing across multiple p…
www.altera.com/support/kdb/solutions/rd10302012_952.html - 2013-11-14

2013-11-14 110100 11.1 120100 12.1 Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals?

Due to a problem in the Quartus® II software version 11.1 and later, the DDR3 UniPHY-based memory controllers with the efficiency monitor enabled incorrectly use the Aval…
www.altera.com/support/kdb/solutions/rd08302012_420.html - 2013-11-14

2013-11-13 0 0 Does the Altera JRunner software support programming of CPLDs?

No, the Altera® JRunner software is developed to configure Altera FPGA devices in JTAG mode for embedded configurations. The Altera JRunner software does not support prog…
www.altera.com/support/kdb/solutions/rd10302013_701.html - 2013-11-13

2013-11-12 120100 12.1 0 L2 Cache Controller Revision Incorrectly Listed as r3p2

The Cortex-A9 Microprocessor Unit Subsystem chapter in Volume 3: Hard Processor System Technical Reference Manual of the Arria V Device Handbook and the Cyclone V Device Handbook …
www.altera.com/support/kdb/solutions/fb162407.html - 2013-11-13

2013-11-13 0 0 What is the top side marking format for Altera devices?

The top side marking format for current Altera® devices is shown in the diagrams below for ball-grid array (BGA) and non-BGA devices.  For more details, refer to  ADV0012…
www.altera.com/support/kdb/solutions/rd10292013_192.html - 2013-11-13

2014-03-04 0 0 Can I reduce the current on VCC_AUX pins (ICC_AUX) by toggle rates or resource usage?

No, the current on VCC_AUX pins (ICC_AUX) is not directly affected by toggle rates or resource usage.  The current on VCC_AUX pins (ICC_AUX) depends o…
www.altera.com/support/kdb/solutions/rd10302013_62.html - 2013-11-13

2013-11-13 130001 13.0 SP1 130100 13.1 How do I set the paramter FAST_SIMULATION of my 40- and 100-Gbps Ethernet MAC and PHY in VHDL?

In Quartus® II software version v13.0SP1 and earlier you must manually modify the IP libraries of the 40- and 100-Gbps Ethernet MAC and PHY IP Core to set the parameter FAST_SIMULA…
www.altera.com/support/kdb/solutions/rd10212013_745.html - 2013-11-13

2013-11-13 130000 13.0 130100 13.1 Why have unused ports appeared on the Triple Speed Ethenet (TSE) IP in Quartus II software version 13.0?

Due to an issue the following unused ports have incorrectly appeared on the TSE IP in Quartus® II software version 13.0: magic_sleep_n, magic_wakeup, xoff_gen, xon_gen In Qu…
www.altera.com/support/kdb/solutions/rd11072013_288.html - 2013-11-13

2014-04-13 0 0 How do I reduce the percentage of crosstalk and SSN towards differential pins in Cyclone V devices?

The attached document will describe how to reduce the percentage (%) of crosstalk and percentage (%) of Simultaneous Switching Noise (SSN) towards differential pins in the Quartus®…
www.altera.com/support/kdb/solutions/rd10102013_979.html - 2013-11-13

2013-11-27 120100 12.1 130100 13.1 Incorrect Clock Connections for Avalon-ST Receive and Transmit Interface

The Avalon Streaming (Avalon-ST) receive source gets wrongly connected to the transmit clock and the Avalon-ST transmit sink gets wrongly connected to the receive clock. However,…
www.altera.com/support/kdb/solutions/fb142588.html - 2013-11-12

2013-11-12 120101 12.1 SP1 130000 13.0 Why Nios II Sof2flash failed to generate flash file for Cyclone II?

Due to a problem in the Quartus® II software version 12.1SP1,  the NIOS® II sof2flash utility is not able to generate a flash file from a Cyclone® II .SOF file.…
www.altera.com/support/kdb/solutions/rd11072013_929.html - 2013-11-12

2013-11-12 130000 13.0 0 Critical Warning (18061): Ignored Power-Up Level option on the following registers

This warning message may be generated for designs using the Serial Digital Interface (SDI) MegaCore® Function software version 13.0 or 13.1. Critical Warning (18061): Ignored…
www.altera.com/support/kdb/solutions/rd11072013_196.html - 2013-11-12

2013-11-12 0 0 What are the definitions of the SPI signals routed from Hard Processor Subsystem (HPS) block to FPGA in Cyclone V SoC and Arria V SoC devices?

Current documentation does not define all the SPI signals routed from HPS block to the FPGA block within Cyclone® V SoC and Arria® V SoC devices.  
www.altera.com/support/kdb/solutions/rd07162013_171.html - 2013-11-12

2013-11-11 110100 11.1 0 Why is tRCD larger than expected with my DDR3 UniPHY controller?

You may see a larger than expected tRCD delay in DDR3 UniPHY quarter-rate memory controllers because the transactions are generated by the controller clock which is running at…
www.altera.com/support/kdb/solutions/rd06122013_805.html - 2013-11-11

2013-11-11 120100 12.1 0 Why doesn't read data return as expected from an Avalon-MM slave ?

Due to a problem in the Quartus® II software version 12.1 and earlier, read data may not return as expected when the Avalon-MM master's data port bit width is wider than …
www.altera.com/support/kdb/solutions/rd01082013_685.html - 2013-11-11

2013-11-11 130100 13.1 0 Why is the Netlist Viewer not updated after the design has been modified and recompiled?

Due to a problem in the Quartus® II software version 13.1 and later, the Netlist Viewer may not be updated after a design is modified and recompiled. This problem may occur when th…
www.altera.com/support/kdb/solutions/rd10062013_288.html - 2013-11-11

2013-11-11 130000 13.0 0 How do I upgrade my LPM, RAM, or ROM megafunctions?

Due to a problem in the Quartus® II software version 13.0 and later, you cannot use the Upgrade IP Components feature to upgrade LPM, RAM, or ROM megafunctions.
www.altera.com/support/kdb/solutions/rd08202013_503.html - 2013-11-11

2013-11-11 130000 13.0 0 Why does Quartus II report that no devices are installed despite installing them?

Due to a problem in the Quartus® II software version 13.0, you may see the following message during installation if your license is not valid or no longer under main…
www.altera.com/support/kdb/solutions/rd07282013_809.html - 2013-11-11

2014-02-25 130000 13.0 130100 13.1 TCP DSTREAM Connection Fails with Trace Enabled

If you try to start a DS-5 debug configuration that connects to the target using DSTREAM over Ethernet, and the 4 GB DSTREAM trace buffer is enabled, the connection fails. You see…
www.altera.com/support/kdb/solutions/fb96231.html - 2013-11-07

2013-11-07 130000 13.0 0 Bootloader Fails to Run with UART0 Disabled

In v13.1, even if UART0 is disabled in the HPS component, the preloader generator turns on spl.performance.SERIAL_SUPPORT (UART0 serial I/O support). In v13.0, even if UART0 is di…
www.altera.com/support/kdb/solutions/fb155746.html - 2013-11-07

2013-11-07 130100 13.1 0 Bonding Does Not Work for Multiple MPFE Ports in Hard Memory Controller

This problem affects DDR2, DDR3, and LPDDR2 products. In Arria V and Cyclone V devices, you can bond two hard memory controllers to increase their bandwidth. To use bonding, you m…
www.altera.com/support/kdb/solutions/fb165793.html - 2013-11-05

2014-01-06 130100 13.1 0 Nios II GNU toolchain upgrade from GCC 4.1.2 to GCC 4.7.3

In ACDS version 13.1, the Nios® II GNU toolchain is upgraded from GCC 4.1.2 to GCC 4.7.3. Users upgrading to the new toolchain need to take note of the following changes liste…
www.altera.com/support/kdb/solutions/rd10302013_291.html - 2013-11-05

2013-11-05 110000 11.0 0 Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands?

The High Performance Controller II (HPCII) used by the DDR2 UniPHY and ALTMEMPHY cores issues back to back read/write commands on every other controller clock cycle (afi_…
www.altera.com/support/kdb/solutions/rd02142012_914.html - 2013-11-05

2013-12-13 130100 13.1 0 Internal Exception Error During Elaboration with NCSim

This problem affects designs that contain a Reed-Solomon II decoder. when you elaborate your design in Cadence NcSim, you may receive a elaboration error.
www.altera.com/support/kdb/solutions/fb146729.html - 2013-11-05

2013-11-05 0 0 Error (181011): Incompatible on-chip termination settings detected for pins in the DQS group fed by DQS I/O pin "<QK clock pin>". All pins in group must use the same OCT control block.

Due to a problem in the Quartus® II software, this error may appear when instantiating multiple RLDRAM 3 UniPHY interfaces in the design. Quartus II software assigns the incorrect …
www.altera.com/support/kdb/solutions/rd05172013_989.html - 2013-11-05

2013-11-05 110001 11.0 SP1 0 Does Quartus II software support x36 QDRII/II+ SRAM emulation mode in Stratix V devices?

The x36 QDR II/II+ SRAM emulation mode is not supported for Stratix® V devices.
www.altera.com/support/kdb/solutions/rd11152011_5.html - 2013-11-05

2013-11-04 0 0 Internal Error: Sub-system: PJC, File: /quartus/sys/pjc/pjc_new_tcl.cpp, Line: 18954
acf_manager->load_side_revision_if_needed( revision_name.c_str()) == ACF_REVISION_MANAGER::LEGAL

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may this error when running the Clean Project utility from the Project menu. If you have project revi…
www.altera.com/support/kdb/solutions/rd08282013_208.html - 2013-11-04

2013-11-01 130100 13.1 0 EMIF Generation for Arria V or Cyclone V Devices Requires Stratix V Device Database to be Installed

This problem affects DDR2, DDR3, LPDDR2 and RLDRAM II products. When generating an external memory interface for an Arria V or Cyclone V device, the generation process may fail to…
www.altera.com/support/kdb/solutions/fb157149.html - 2013-11-04

2013-11-04 130000 13.0 130001 13.0 SP1 ECC Not Enabled in Cyclone V SoC HPS Devices

This problem affects DDR2, DDR3, and LPDDR2 products. For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, interface widths of 24 (16 plus ECC) and 40 (32 plus …
www.altera.com/support/kdb/solutions/fb108775.html - 2013-11-04

2013-11-01 130100 13.1 0 x8 and x16 HPS Designs not Supported on Arria V and Cyclone V Devices

This problem affects DDR2 and DDR3, and LPDDR2 products. On Arria V and Cyclone V devices, x8 and x16 HPS designs are not supported.
www.altera.com/support/kdb/solutions/fb164231.html - 2013-11-04

2013-11-04 0 0 Why is input data lost when using the Avalon ST channel multiplexer?

Due to a problem in the Avalon® Streaming Channel Multiplexer component available in Qsys, data may be lost from the input port while the ready input of the output port is dea…
www.altera.com/support/kdb/solutions/rd09232013_431.html - 2013-11-04

2013-11-01 130100 13.1 0 IP Generation Fails When Both Efficiency Monitor and Ping Pong PHY Enabled

This problem affects DDR2, DDR3, LPDDR2, RLDRAM II and RLDRAM 3 products. IP generation fails when you attempt to instantiate your UniPHY-based external memory interface IP with b…
www.altera.com/support/kdb/solutions/fb158297.html - 2013-11-04

2013-11-01 130100 13.1 0 EMIF Maximum Frequency Specification Update for Stratix V

This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Stratix V devices may have difficulty achieving timing closure at certain maximum frequencies.
www.altera.com/support/kdb/solutions/fb163770.html - 2013-11-04

2013-11-04 0 0 Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_tx_editors.cpp, Line: 1046

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this error if your SignalTap™ II Logic Analyzer has a trigger condition which includes a node…
www.altera.com/support/kdb/solutions/rd08272013_386.html - 2013-11-04

2013-11-04 130000 13.0 130100 13.1 Is vertical migration supported in Cyclone V SoC devices?

Yes, vertical migration is supported in the U672 packages of Cyclone® V SE and SX devices. Prior to the following patch, however, vertical migration between these devices…
www.altera.com/support/kdb/solutions/rd08272013_16.html - 2013-11-04

2013-11-01 130100 13.1 0 Group Mask Settings in EMIF Debug Toolkit Not Applied During Recalibration

This problem affects DDR2, DDR3, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. For any UniPHY-based external memory interface IP generated in the Quartus II software version 13…
www.altera.com/support/kdb/solutions/fb153524.html - 2013-11-04

2013-11-04 130100 13.1 0 DDR3 HPS Interfaces Supported Only to 450 MHz on Arria V SoC ES Devices

This problem affects DDR3 products. In Arria V SoC ES devices, the HPS hard memory controller supports DDR3 interfaces to a maximum of 450 MHz. Higher frequency interfaces are not…
www.altera.com/support/kdb/solutions/fb144502.html - 2013-11-04

2013-11-04 130001 13.0 SP1 130100 13.1 ECC Enabled Automatically in Cyclone V SoC HPS Devices

This problem affects DDR2, DDR3, and LPDDR2 products. For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, if you create interface widths of 24 or 40, ECC is en…
www.altera.com/support/kdb/solutions/fb129162.html - 2013-11-04

2013-11-01 130100 13.1 0 Possible Simulation Failure in Skip Calibration Mode

This problem affects DDR2, DDR3, and LPDDR2 products. Arria V or Cyclone V external memory interfaces that use the hard memory controller and were generated in the Quartus II soft…
www.altera.com/support/kdb/solutions/fb157477.html - 2013-11-04

2013-11-01 120101 12.1 SP1 0 EMIF Maximum Frequency Specification Update

This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience problems achieving timing closure at certain…
www.altera.com/support/kdb/solutions/fb156054.html - 2013-11-01

2013-10-30 130100 13.1 0 Unable to Install DS-5: “Error running msiexec”

You might see an error message similar to the following when you try to install DS-5: Error running msiexec ... Program ended with an error exit code The DS-5 installer does not r…
www.altera.com/support/kdb/solutions/fb146385.html - 2013-10-31

2014-02-28 130000 13.0 0 Why does my Cyclone V PCIe design have intermittent link up issue?

The Quartus® II software version 13.0sp1 and earlier have incorrect settings for the Receiver Common Mode Voltage (Vcm) and the Receiver Signal Detection Voltage Threshold (Vth) …
www.altera.com/support/kdb/solutions/rd10162013_246.html - 2013-10-31

2013-10-31 120100 12.1 130001 13.0 SP1 Conflicting Pin Assignment Error with UART0

If your HPS design was created with Qsys v13.0 or earlier, and you open it in v13.0 SP1 or later, you might see an error message similar to the following: The selected peripheral …
www.altera.com/support/kdb/solutions/fb137954.html - 2013-10-31

2013-10-30 130000 13.0 0 DS-5 Debugger Unable to Connect to SoC HPS

If you try to connect the DS-5 debugger to the SoC HPS with a USB-Blaster, you might see an error message similar to the following: Connection Failed Unable to connect This proble…
www.altera.com/support/kdb/solutions/fb143377.html - 2013-10-31

2013-10-30 0 0 External Memory Interface Handbook: Known Issues

Issue 138581: Volume 3, Chapter 12: Timing Diagrams for UniPHY IP, Version 2.1 Figure 12-18 shows that the avl_size is 0. This value is illegal and should be 1. Everything else in…
www.altera.com/support/kdb/solutions/rd10082013_533.html - 2013-10-30

2013-10-30 120000 12.0 130000 13.0 Why do I see timing violations for the altera_reserved_tck signal when using DDR3 SDRAM controller with UniPHY?

Due to a problem in the Quartus® II software version 12.1sp1 and before, when instantiating a DDR3 SDRAM controller with UniPHY, you may get a hold timing violation for altera_rese…
www.altera.com/support/kdb/solutions/rd08312012_660.html - 2013-10-30

2013-10-30 0 0 Why is the PCIe Hard IP core not sending out the required flow control (FC) update within 30 us

Due to an issue with the Altera® PCI Express® Hard IP, FC update may not happen within the required 30us.
www.altera.com/support/kdb/solutions/rd10222013_523.html - 2013-10-30

2013-10-30 120000 12.0 0 Why are the values for FS (Full Swing) and LF (Low Frequency) zero when simulating a PCIe Hard IP core for Gen3?

There is an issue with the PCIe® Hard IP simulation models when targeting the Stratix® V and Arria® V GZ device families, where the values for FS and LF are zero for Gen3.&nbs…
www.altera.com/support/kdb/solutions/rd10022013_210.html - 2013-10-30

2014-01-08 0 0 What is the description of the MsiIntfc_o[81:0] and MsixIntfc_o[15:0] signals?

If you select Enable multiple MSI/MSI-X support under the Avalon Memory-Mapped (Avalon-MM) System Settings banner in Hard IP for PCI Express® MegaWizard™ window, it expor…
www.altera.com/support/kdb/solutions/rd09262013_223.html - 2013-10-30

2013-12-02 130000 13.0 0 How should I connect the clocks on the Triple-Speed Ethernet (TSE) MegaCore IP when implemented in Qsys

When the TSE IP MAC is implemented in Qsys, the required clock connections are as detailed below:Qsys Name :  Interface Description in the User Guidecontrol_port_clock_co…
www.altera.com/support/kdb/solutions/rd10302013_752.html - 2013-10-30

2013-10-29 120000 12.0 120101 12.1 SP1 Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of (value)

This error may occur when compiling a project which contains an LPDDR2 controller and one or more non-associated on-chip termination (OCT) blocks. The reason is that the outp…
www.altera.com/support/kdb/solutions/rd11152012_357.html - 2013-10-29

2014-06-04 0 0 Why is my JTAG chain broken when the HPS_nRST or HPS_nPOR signal is asserted?

The hard processor system (HPS) JTAG port (HPS_TCK, HPS_TMS, HPS_TDI, HPS_TDO) of Arria® V SoC and Cyclone® V SoC devices is held in Test Logic Reset when either HPS_nRST or H…
www.altera.com/support/kdb/solutions/rd08122013_684.html - 2013-10-29

2013-10-29 0 0 Can I use the hard processor system (HPS) flash programmer to program a Raw Binary File (.rbf)?

The HPS flash programmer supports only the Binary File (.bin) type, not .rbf extension.
www.altera.com/support/kdb/solutions/rd10222013_501.html - 2013-10-29

2013-10-29 130001 13.0 SP1 130100 13.1 Assign LVDS I/O standard-supported pins in right I/O banks of Arria V A1/A3/C3 devices as PLL clock input pins only

If you use the Quartus II software version 13.0 DP2 or 13.0 SP1 to create a design that targets an Arria V A1, A3 or C3 device, and you use the LVDS I/O standard-enabled pins in t…
www.altera.com/support/kdb/solutions/fb128391.html - 2013-10-29

2013-10-29 120001 12.0 SP1 0 Error (129029): Input port CLK on atom "<DLL instance>", which is a arriav_dll primitive, is not connected to a valid source File: <project path>/dll.v Line: 53

The PLL output cannot be connected to the DLL directly when Enable access to dynamic phase shift ports is selected in the Altera PLL MegaWizard™ GUI. The Quartus® II…
www.altera.com/support/kdb/solutions/rd01152013_434.html - 2013-10-29

2013-10-29 120000 12.0 120100 12.1 The supplied JTAG Debug Information (.jdi) file for the project does not appear to match the specified target device as not all nodes have hierarchy info.

Due to an issue with the Quartus® II software version 12.0 and later, this error may occur the Quartus II software output files is set to a directory other than the defau…
www.altera.com/support/kdb/solutions/rd06122012_292.html - 2013-10-29

2013-10-29 0 0 Does the Stratix V MLAB block support byte enable option in x16 depth mode?

No, Stratix® V device MLAB blocks do not support the byte enable option in x16 depth mode.
www.altera.com/support/kdb/solutions/rd10102013_890.html - 2013-10-29

2013-10-29 110001 11.0 SP1 0 How do I reduce the UniPHY DDR3 controller pulsing avl_ready low on the Avalon interface?

Depending on the type of accesses on the controller's Avalon® interface, you may see the avl_ready pulse low in some situations where it should not be expected. This occurs because…
www.altera.com/support/kdb/solutions/rd08142013_467.html - 2013-10-29

2013-10-29 120100 12.1 130100 13.1 Rapid Recompile feature is disabled for all device families

If you compile a design that was created by a previous version of the Quartus II software, and the Quartus II Settings File (.qsf) contains the setting set_global_assignment ‑name…
www.altera.com/support/kdb/solutions/fb97271.html - 2013-10-29

2013-10-28 0 0 How do I duplicate nodes in Data tab of the SignalTap II Logic Analyzer?

To duplicate nodes in Data tab of the SignalTap™ II Logic Analyzer, select the nodes, then drag and drop while holding Ctrl key.
www.altera.com/support/kdb/solutions/rd10212013_335.html - 2013-10-28

2013-10-28 120000 12.0 0 How do I restore the Enable decompression during Partial Reconfiguration option?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, in Convert Programming File utility the Enable decompression during Partial Reconfiguration option is not…
www.altera.com/support/kdb/solutions/rd09132013_317.html - 2013-10-28

2013-10-28 100100 10.1 0 Infrequent Host Replay Timer Timeout for Stratix V Hard IP for PCI Express IP Core

Infrequent host replay timer timeouts can occur, because the Stratix V Hard IP for PCI Express IP Core infrequently skips transmitting ACK DLLP for a given received packet. This i…
www.altera.com/support/kdb/solutions/fb104302.html - 2013-10-28

2013-10-28 0 0 Why does grouping and ungrouping signals in the SignalTap II Logic Analyzer require recompilation?

Changing how signals are grouped in the SignalTap™ II Logic Analyzer when the basic OR trigger is selected changes the logic which then requires a recompilation.
www.altera.com/support/kdb/solutions/rd10212013_372.html - 2013-10-28

2013-10-28 130000 13.0 0 Can I uninstall Quartus II patches?

Starting with the Quartus® II software version 13.0, you can uninstall patches if you installed the patch with the Allow patches to be uninstalled option&n…
www.altera.com/support/kdb/solutions/rd10222013_449.html - 2013-10-28

2013-10-22 130000 13.0 0 Error: operand 0 must be FPSCR --'vmsr fpexc, r0'

Due to a problem in SoC Embedded Design Suite, this error may be seen during compilation in ARM DS-5 Altera Edition when  vmsr fpexc, r0 in used in .s asse…
www.altera.com/support/kdb/solutions/rd10212013_826.html - 2013-10-22

2013-10-25 0 0 Why can't I route NAND, SDMMC and USB peripherals to the FPGA in Quartus 13.1 customer beta?

The Quartus® II software version 13.0 incorrectly allowed the HPS NAND, SDMMC and USB interfaces to be routed to the FPGA Fabric This has been fixed for the Quartus® II softw…
www.altera.com/support/kdb/solutions/rd10212013_587.html - 2013-10-22

2013-10-22 0 0 Does my Avalon-MM Master Interface need to generate egintransfer”/”beginbursttransfer” signals?

No, "begintransfer" and "beginbursttransfer" are optional signals in the Avalon Specification. These signals will be automaticically generated by QSYS if req
www.altera.com/support/kdb/solutions/rd07262013_942.html - 2013-10-22

2013-10-22 130001 13.0 SP1 0 What is the correct receiver dc gain range for the XCVR_RX_DC_GAIN qsf variable in Cyclone V transceiver devices?

The correct equalizer range for the XCVR_RX_DC_GAIN qsf variable in Cyclone® V transceiver devices is 0-1. This is incorrectly shown as 0-4 in the Transceiver PHY I…
www.altera.com/support/kdb/solutions/rd10042013_296.html - 2013-10-22

2013-10-22 0 0 What is the material finish for the conductive surface on the 10-pin female plug for ByteBlaster, USB-Blaster, and EthernetBlaster cables?

Tin (Sn) is the material finish for the conductive surface on the 10-pin female plug on the ByteBlaster™, USB-Blaster™, and EthernetBlaster cables.
www.altera.com/support/kdb/solutions/rd10042013_830.html - 2013-10-22

2013-10-22 0 0 What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY?

Altera® does not recommend terminating the mem_reset_n signal. DDR3 DIMMs typically do not use any termination on the memory reset signal. Refer to the memory vendor data…
www.altera.com/support/kdb/solutions/rd07212013_499.html - 2013-10-22

2013-10-22 130001 13.0 SP1 0 Error (332000): can't read "local_pll_driver_core_clk": no such variable

When you use LPDDR2 SDRAM Hard Memory Controller in Quartus® II software version 13.0SP1, you will see the following fitter errors when you compile your project. Error (…
www.altera.com/support/kdb/solutions/rd07282013_198.html - 2013-10-22

2013-10-22 0 0 Why do I see incorrect initialization of my Arria V M10K memory blocks?

Due to a problem in the Quartus® II software version 13.0sp1 and earlier you may find the initial content of Arria® V M10K memory blocks to be incorrect in hardware. The problem i…
www.altera.com/support/kdb/solutions/rd10042013_803.html - 2013-10-22

2013-10-22 120000 12.0 0 Why does a misaligned memory trap happen in the NicheStack TCP/IP Stack when sending multicast message ?

Due to a problem of NicheStack TCP/IP Stack - Nios® II Edition, a misaligned memory trap happens when a multicast message is sent and a stream of multicast messages are being recei…
www.altera.com/support/kdb/solutions/rd08232013_134.html - 2013-10-22

2013-10-22 120101 12.1 SP1 130001 13.0 SP1 Why does the avl_ready signal stay low when using the hard memory controller with multi-port front end port widths of 128 bits?

Due to an issue in the hard memory controller in the Quartus® II software version 12.1sp1, the avl_ready signal will stay low if using 128-bit width ports. Calibration may pas…
www.altera.com/support/kdb/solutions/rd04102013_576.html - 2013-10-22

2013-10-22 120101 12.1 SP1 0 Why does the Report DDR section in TimeQuest only report 10 paths?

By default, the UniPHY-based controller timing analysis in TimeQuest will report 10 paths. To increase the number of paths shown: Open <variation name>_p0_parameters.tc…
www.altera.com/support/kdb/solutions/rd04102013_285.html - 2013-10-22

2013-10-22 0 0 Error: libbytestream.so ELF 32 class not present

Due to a problem in the Quartus® II software, this error may occur when sourcing the libbytestream_pli.so library with the ModelSim®-Altera software or oth…
www.altera.com/support/kdb/solutions/rd10032012_557.html - 2013-10-22

2014-03-04 120101 12.1 SP1 130100 13.1 Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY?

Due to a problem in the Quartus II software version 13.0sp1 and earlier, the output of DQS logic block may cause random read errors. The following configurations may be affected: …
www.altera.com/support/kdb/solutions/rd09252013_109.html - 2013-10-22

2013-10-22 0 0 Why do the CSR registers report ECC data errors when the read data is not corrupted?

The configuration and status registers (CSR) may report bit errors even though the traffic generator monitor does not detect data corruption when you enable both error correct…
www.altera.com/support/kdb/solutions/rd09262013_617.html - 2013-10-22

2013-10-22 0 0 Error: More than 20 IO rows exported.

You may see this error when importing a PowerPlay Early Power Estimation file generated by the Quartus® II software into the following Early Power Estimator (EPE) tools: MAX® II…
www.altera.com/support/kdb/solutions/rd10172013_473.html - 2013-10-22

2013-10-22 0 0 How are QSPI chipselect signals controlled during boot ?

The boot software in the HPS BootROM expects the QSPI boot device to be connected to QSPI_SS0 out of chipselect signals (QSPI_SS3/2/1/0).
www.altera.com/support/kdb/solutions/rd09182013_514.html - 2013-10-22

2013-10-22 0 0 What voltage should the HPS BOOTSEL (BSEL) and HPS CLOCKSEL (CSEL) pins be connected to?

The pull-up resistors for the BSEL and CSEL pins should be tied to the VCCIO voltage for the banks that contain those pins.
www.altera.com/support/kdb/solutions/rd10082013_320.html - 2013-10-22

2013-10-21 0 0 Stratix® GX Device Handbook: Known Issues

Issue 132933: Volume 3, Chapter 1 "Configuring Stratix & Stratix GX Devices" Version 3.2 Table 1–15 incorrectly states "When using EPC2 devices, only external 10-kΩ pull-up …
www.altera.com/support/kdb/solutions/rd10052013_906.html - 2013-10-21

2013-10-21 100000 10.0 0 Using Merging Feature

When you generate designs with a version of the high-performance controller II (HPC II) earlier than 11.0, the merging feature is turned off by default. Burst Merging is not suppo…
www.altera.com/support/kdb/solutions/spr390121.html - 2013-10-21

2013-10-21 0 0 Can I get a version of alterad for Solaris later than 9.5?

The Quartus® II software support on Solaris has been discontinued, and updates to the alterad daemon for Solaris are not provided. Version 9.5 of the alterad daemon is the last ver…
www.altera.com/support/kdb/solutions/rd10152013_465.html - 2013-10-21

2013-10-21 100000 10.0 0 Using Burst Merging Feature for DDR2 and DDR3 SDRAM Controller with UniPHY

For designs created in a version of the high-performance controller II (HPC II) earlier than 11.0, the burst merging feature is turned off by default when a you generate a control…
www.altera.com/support/kdb/solutions/spr348355.html - 2013-10-21

2013-10-21 120100 12.1 0 Why is the Maximum Fan-Out assignment ignored?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this warning if the Maximum Fan-Out assignment is applied to a register that drives an input …
www.altera.com/support/kdb/solutions/rd07232013_49.html - 2013-10-21

2013-10-21 0 0 Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_titan_atom_visitor_main.cpp, Line: 1966
Atom type not supported by PVA

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this Internal Error while running the PowerPlay Power Analyzer. 
www.altera.com/support/kdb/solutions/rd10022013_121.html - 2013-10-21

2013-10-21 0 0 Stratix® Device Handbook: Known Issues

Issue 132933: Volume 2, Chapter 11 Configuring Stratix & Stratix GX Devices, Version 3.2 Table 11–15 incorrectly states "When using EPC2 devices, only external 10-kΩ pull-up…
www.altera.com/support/kdb/solutions/rd10052013_671.html - 2013-10-21

2013-10-21 110001 11.0 SP1 0 Internal Error: Sub-system: PDB, File: /quartus/db/pdb/pdb_archive.cpp, Line: 2851

This error may be seen when opening an existing project or creating a new project in the Quartus® II software version 11.0 SP1 when the device installation files have been cor…
www.altera.com/support/kdb/solutions/rd11162011_918.html - 2013-10-21

2013-10-17 120100 12.1 0 Why does a delay sometime occur when accessing DDR3 memory ?

In the Quartus® II software version 12.1, when the UniPHY DDR3 IP configuration is for a single rank interface and meets these requirements, DQS tracking is enabled : Stratix V, A…
www.altera.com/support/kdb/solutions/rd11192012_232.html - 2013-10-17

2013-10-15 0 0 Are single bit errors corrected when the Enable Error Detection and Correction Logic option is selected and the Enable Auto Error Correction option is disabled in the DDR3 SDRAM controller with UniPHY?

When using the DDR3 controller with UniPHY, the Enable Error Detection and Correction Logic option is enabled, any data coming back from memory via read command with single bit err…
www.altera.com/support/kdb/solutions/rd09122013_56.html - 2013-10-15

2013-10-15 120002 12.0 SP2 130000 13.0 Warning (332174): Ignored filter at <variation name>_p0.sdc(679): _UNDEFINED_PIN__driver_core_clk could not be matched with a clock

When you use the hard memory controller in the Quartus® II software version 12.0sp2 and compile the files generated by Qsys or the files in the folder instead of the <…
www.altera.com/support/kdb/solutions/rd09252012_941.html - 2013-10-15

2013-10-15 0 0 Why is the memory reset output port unconstrained in the memory controller?

In the Quartus® II software, the TimeQuest tool may report unconstrained paths for the UniPHY or ALTMEMPHY memory controllers. The mem_reset_n output signal to the memory…
www.altera.com/support/kdb/solutions/rd09092013_700.html - 2013-10-15

2013-10-14 130000 13.0 0 Why am I unable to select Design Assistant rules for state machines starting in Quartus II software version 13.0?

Beginning with the Quartus® II software version 13.0, Design Assistant (DA) state-machine rules M101, M102, M103, M104, and M105 are no longer supported and cannot be enabled.…
www.altera.com/support/kdb/solutions/rd10112013_370.html - 2013-10-14

2013-10-14 0 0 Why does the TimeQuest timing analyzer report restricted Fmax with the reason "Limit due to hold check"?

In the TimeQuest timing analyzer, Fmax is only based on the setup check, while the Restricted Fmax checks setup, hold and minimum period/pulse width. Usually, Fmax is not limited b…
www.altera.com/support/kdb/solutions/rd09302013_60.html - 2013-10-14

2013-10-14 0 130000 13.0 Warning (308023): (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers.

Due to a problem in the Quartus® II software version 12.1 SP1 and earlier, Design Assistant may incorrectly issue R102 warnings. This problem affects designs where a dual-stage res…
www.altera.com/support/kdb/solutions/rd09242013_649.html - 2013-10-14

2013-10-14 0 0 How do I constrain the osc output pin for ALTUFM megafunctions?

To constrain the optional osc output pin on ALTUFM_NONE, ALTUFM_I2C, ALTUFM_SPI, and ALTUFM_PARALLEL megafunctions, use either of the following methods: Constrain the clock auto…
www.altera.com/support/kdb/solutions/rd10012013_145.html - 2013-10-14

2013-10-14 130000 13.0 0 Why does my Quartus II software installation fail when using McAfee antivirus software?

Due to a conflict between the Quartus® II software version 13.0 and 13.0 SP1 and the McAfee antivirus software, you may see failures during Quartus II installation.  These fai…
www.altera.com/support/kdb/solutions/rd09302013_539.html - 2013-10-14

2013-10-14 0 0 Internal Error: Sub-system: THR, File: /quartus/ccl/thr/thr_thread.c, Line: 266

Due to the limitation of memory resource availablility for 32-bit operating systems, you may see this internal error during compilation when using the 32-bit version of t…
www.altera.com/support/kdb/solutions/rd10022013_356.html - 2013-10-14

2013-10-14 130001 13.0 SP1 0 Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_port.cpp, Line: 409

Due to a problem in the Quartus® II Web Edition software version 13.0SP1, you may see this internal error when running the EDA Netlist Writer to generate an output n…
www.altera.com/support/kdb/solutions/rd09302013_869.html - 2013-10-14

2013-10-14 0 0 Warning (332060): Node: <node> was determined to be a clock but was found without an associated clock assignment.

You may get this warning message in the Quartus® II software for signals that drive the clock input of a register or the enable input of a latch if you have not created a…
www.altera.com/support/kdb/solutions/rd10022013_898.html - 2013-10-14

2013-10-10 0 0 How do I connect the signals of the ALTDQ_DQS2 Hard Read FIFO?

The ALTDQ_DQS2 Hard Read FIFO has the following ports as described below: lfifo_rden: Data input to the Read FIFO Read Enable. This signal is the full read enable token generated b…
www.altera.com/support/kdb/solutions/rd05272013_511.html - 2013-10-10

2013-10-10 0 0 How does the Avalon data bus map to the external DDR3 bus for DDR3 with ECC interface?

For DDR3 UniPHY controllers, the width of the Avalon data bus depends on the Rate on Avalon-MM interface setting of the controller. The options are half-rate or quarter-r…
www.altera.com/support/kdb/solutions/rd06202013_951.html - 2013-10-10

2013-10-10 130000 13.0 0 Does the Advanced clock phase control adjustment in the HPS DDR3 work?

You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks.
www.altera.com/support/kdb/solutions/rd09032013_507.html - 2013-10-10

2013-10-10 0 0 How config_data is shifted into the scan chain block when dynamic reconfiguration is used in ALTDQ_DQS2 Megafunction?

LSB bit will be scanned into the config data pin first, from LSB to MSB bits.This information will be updated in the upcoming update of ALTDQ_DQS2 Megafunction User Guide.
www.altera.com/support/kdb/solutions/rd09192013_137.html - 2013-10-10

2014-02-19 130000 13.0 0 Why is my HPS DDR3 controller failing calibration?

Your HPS DDR3 controller generated with Quartus® II software version 13.0 or 13.0sp1 may experience a calibration failure and produce the following debug messages in the debug…
www.altera.com/support/kdb/solutions/rd08142013_761.html - 2013-10-10

2013-10-10 0 0 Why does the example design simulation fail when the UniPHY controller is generated with PHY only option?

When simulating the example design of a UniPHY controller with PHY only option, some ports in the controller *_e0_c0 instance are not connected causing the simulation to…
www.altera.com/support/kdb/solutions/rd08042013_468.html - 2013-10-10

2013-10-09 120101 12.1 SP1 0 Why do I see long simulation times when simulating UniPHY-based controllers in skip calibration mode?

When simulating a UniPHY-based controller in skip calibration mode, you may find that the simulation takes longer than expected. Usually with skip calibration mode, the calibration…
www.altera.com/support/kdb/solutions/rd08212013_107.html - 2013-10-09

2013-10-09 110102 11.1 SP2 0 Synchronous edges BOTH requires associated clock

You will get this error message if you generate a Qsys system that contains a PCIe® Hard IP core, the nreset_status signal is exported and a testbench is being generating…
www.altera.com/support/kdb/solutions/rd09272013_799.html - 2013-10-09

2013-10-09 0 0 Why is the PCI Express Hard IP not generating ECRC when Advanced error reporting (AER), ECRC checking, ECRC generation and ECRC forwarding are enabled?

The PCI® Express Hard IP will not automatically set the TLP TD bit if ECRC forwarding is enabled. When ECRC forwarding is enabled the TLP TD bit will be sent unchanged by the IP.&n…
www.altera.com/support/kdb/solutions/rd09042013_818.html - 2013-10-09

2013-10-09 0 0 Why can the LVDS I/O not be selected in the Triple Speed Ethernet MegaCore GUI for Cyclone series devices?

LVDS I/O cannot be selected in the Triple Speed Ethernet MegaCore® GUI if the target device is a Cyclone® series device. This is because the LVDS …
www.altera.com/support/kdb/solutions/rd09252013_592.html - 2013-10-09

2013-10-09 130000 13.0 0 Why is the value of LED_LINK different than the value of the LINK_STATUS register in Triple Speed Ethernet (TSE) IP MegaCore function in Quartus II software version 13.0?

 The LED_LINK signal can be different from the value of the 
www.altera.com/support/kdb/solutions/rd09162013_357.html - 2013-10-09

2013-10-08 0 0 Why is the input data rate parameter text box not present in the ALTLVDS_RX megafunction in the Quartus II software version 13.0sp1?

In the Quartus® II software version 13.0, the input data rate text box was available when using external PLL mode with DPA enabled in the ALTLVDS_RX megafunction. Beginning …
www.altera.com/support/kdb/solutions/rd10022013_93.html - 2013-10-08

2013-10-08 0 0 Can I choose the DCLK frequency for slave devices when using a multiple device Active Serial (AS) configuration scheme in 28nm devices?

No, when using a multiple device AS configuration scheme in Stratix®  V, Arria®  V, and Cyclone®  V devices,  a 12.5 MHz clock is always used for DCLK…
www.altera.com/support/kdb/solutions/rd09292013_71.html - 2013-10-08

2013-10-08 0 0 ERR_MaxRefsPostponed :: More than a total of 8 Refresh commands postponed by more then trefi = <trefi_value> ns

This error may be seen while simulating your memory controller using a vendor memory model. Altera does not officially support vendor memory models. However, if you choose to …
www.altera.com/support/kdb/solutions/rd08222013_900.html - 2013-10-08

2013-10-08 0 0 How can I enable the "Disable EPCS ID check" option when generating my programming file via the command line (quartus_cpf)?

To enable the Disable EPCS ID check option when using the quartus_cpf command, you need to add the following line to a quartus.ini file in your project directory or the Quartus® II…
www.altera.com/support/kdb/solutions/rd10022013_142.html - 2013-10-08

2013-10-08 0 0 Is there a known issue with generating a PowerPlay Early Power Estimator Comma-Separated Value File (.csv) for the Early Power Estimator (EPE) tool in the Quartus II software version 13.0sp1 and earlier for Cyclone V SoC devices?

Yes, there is a known issue with generating a PowerPlay Early Power Estimator .csv file in the Quartus® II software version 13.0sp1 and earlier for Cyclone® V SoC devices. When t…
www.altera.com/support/kdb/solutions/rd10042013_143.html - 2013-10-08

2013-10-08 0 0 Can the PCIe Hard IP core and the DDR3 IP core share the same refclk?

It is not recommended to share the refclk between the PCIe® Hard IP core and the external memory interface IP core, which includes all UniPHY and ALTMEMPHY-base…
www.altera.com/support/kdb/solutions/rd09302013_307.html - 2013-10-08

2013-10-08 0 0 Is there a known issue with the Altera PLL megafunction lock range fitter report in the Quartus II software?

Yes, for some Altera PLL megafunction configurations, the Quartus® II software version 13.0sp1 and earlier may report "N/A" for the PLL Freq Min Lock and PLL Freq Max Lock val…
www.altera.com/support/kdb/solutions/rd10042013_791.html - 2013-10-08

2013-10-08 0 0 Warning (205015): Pin "~ALTERA_CRC_ERROR~" has no VCCIO voltage of the configuration pin

You may see this error in the Quartus® II software when generating IBIS models with the Print per pin RLC package model with mutual coupling option enabled. This error occurs if yo…
www.altera.com/support/kdb/solutions/rd09272013_0.html - 2013-10-08

2014-03-31 120000 12.0 0 How is the voltage selected for the VCCRSTCLK_HPS pin in the Pin-Out File (.pin) generated by the Quartus II software?

When using Cyclone® V or Arria® V devices that support the Hard Processor System (HPS), the .pin file created by the Quartus® II software will select from various voltages for…
www.altera.com/support/kdb/solutions/rd10012013_555.html - 2013-10-08

2013-10-08 130001 13.0 SP1 0 Internal Error: Sub-system: SIN, File: /quartus/h/sin_micro_tnodes_enum_translator_auto.cpp. Line: 5985

In the Quartus® II software version 13.0sp1, you may see this internal error when running the PowerPlay Power Analyzer if a transceiver receiver channel uses either the LVDS o…
www.altera.com/support/kdb/solutions/rd10022013_471.html - 2013-10-08

2013-10-08 0 0 How do I set the timing parameters for DDR3L?

Some of the timing parameters in the manufacturers' DDR3L SDRAM datasheets may not be defined, but you can refer to the DDR3 SDRAM datasheet to use the timing p…
www.altera.com/support/kdb/solutions/rd09302013_115.html - 2013-10-08

2013-10-07 0 0 Why does my reset signal get inverted when using incremental compilation?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see incorrect behavior of reset signals when using incremental compilation. Specifically, th…
www.altera.com/support/kdb/solutions/rd09132013_440.html - 2013-10-07

2013-10-07 130001 13.0 SP1 0 Internal Error: Sub-system: HDB, File: /quartus/h/qtl_object_cache_sys.h, Line: 1010

Due to a problem in the Quartus® II software version 13.0 SP1, you may see this error during the Fitter stage when compiling your project.
www.altera.com/support/kdb/solutions/rd09232013_129.html - 2013-10-07

2013-10-07 0 0 Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_pr.cpp, Line: 1684

Due to a problem in the Quartus II software version 13.0 and earlier, using dual-regional clocks in a Partial Reconfiguration (PR) design  may result in above intern…
www.altera.com/support/kdb/solutions/rd09062013_861.html - 2013-10-07

2013-10-07 0 0 Why do I get the same timing results for all timing corners when using Design Space Explorer?

In the Quartus® II software, Design Space Explorer (DSE) may report the same results for fall timing corners if your Synopsys Design Constraints (.sdc) file contains a set_operatin…
www.altera.com/support/kdb/solutions/rd09112013_103.html - 2013-10-07

2013-10-07 0 0 Error (175001): Could not place fractional PLL
Info (175028): The fractional PLL name: <PLL instance name>|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
Error (12349): The Fitter was unable to route the far global PLL feedback path for the fractional PLL. Please review the detailed help for this message for possible workarounds

You may see this error message during compilation with the Quartus® II software, if your PLL mode is in Normal and Source Synchronous compensation feedback mode which requires…
www.altera.com/support/kdb/solutions/rd09062013_845.html - 2013-10-07

2013-10-07 0 0 *** Fatal Error: Stack Overflow
Module: quartus_map.exe
Lock in use: 54

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this error when you compile a design containing a long series of LUTs with no registers such …
www.altera.com/support/kdb/solutions/rd09232013_776.html - 2013-10-07

2013-10-07 130001 13.0 SP1 0 Application failed initialize properly

You may get this error message when launching the Quartus® II Programmer Only software version 13.0 SP1 if your computer does not have Microsoft Visual C++ installed and you are ru…
www.altera.com/support/kdb/solutions/rd09192013_938.html - 2013-10-07

2013-10-07 130001 13.0 SP1 0 How can I enable vertical migration in Cyclone V SX and SE devices in the Quartus II software version 13.0 SP1?

To enable vertical migration support for Cyclone V SX and SE devices in the Quartus II software version 13.0 SP1, download and install patch 1.31 from the links below. For det…
www.altera.com/support/kdb/solutions/rd08302013_866.html - 2013-10-07

2013-10-04 130000 13.0 0 What is the afi_reset_export_n port used for?

Beginning with the Quartus® II software version 13.0, the memory controllers with UniPHY IP generate an extra port afi_reset_export_n when PLL sharing is not enabled or PLL sharing…
www.altera.com/support/kdb/solutions/rd09262013_885.html - 2013-10-04

2013-10-02 120100 12.1 130000 13.0 Why does the Fitter report an ALM utilization greater than 100%?

Due to a problem in the Quartus® II software version 12.1 SP1 and earlier, the Fitter may incorrectly report greater than 100% ALM utilization for certain devices.
www.altera.com/support/kdb/solutions/rd03182013_312.html - 2013-10-02

2013-10-01 0 0 How do I perform IBIS simulation when a VREF pin is used as general purpose regular I/O pin?

The pin capacitance is higher on VREF pins than general purpose I/O pins.  The IBIS models do not contain the additional pin capacitance for the VREF pins when used …
www.altera.com/support/kdb/solutions/rd09202013_445.html - 2013-10-01

2013-10-01 0 0 For Fast Passive Parallel (FPP) configuration, if the data is sent in bursts should the clock be paused and the data line be tri-stated during periods without data present?

Yes, for FPP configuration it is recommended to pause DCLK and tri-state the data lines for periods of inactivity. If DCLK is still toggling when there is no actual data present, i…
www.altera.com/support/kdb/solutions/rd09252013_219.html - 2013-10-01

2013-10-01 0 0 Is it possible to use the quartus_cpf command to generate a Progammer Object File (.pof) and JTAG Indirect Configuration (.jic) programming file for Active Serial (AS) x4 mode with encryption enabled?

It is not possible to generate the .pof/.jic programming file for AS x4 mode with encryption enabled in the Quartus® II software when using the quartus_cpf…
www.altera.com/support/kdb/solutions/rd09122013_808.html - 2013-10-01

2013-10-01 0 0 Stratix IV Pin Connection Guidelines: Known Issues

Issue 137246: Version 1.8 If the JTAG connections are not used, user should connect the TDI pin to VCCPD via a 1-kΩ resistor, connect TMS to VCCPD via a 1-kΩ resistor, tie&nb…
www.altera.com/support/kdb/solutions/rd09102013_249.html - 2013-10-01

2014-05-27 0 0 What is the Instruction Register (IR) length of the Hard Processor System (HPS) JTAG pins on Cyclone V and Arria V SoC devices?

The HPS JTAG pins are not intended for boundary scan for Cyclone® V and Arria® V SoC devices.  The HPS JTAG pins do not have a Boundary-Scan Description La…
www.altera.com/support/kdb/solutions/rd09232013_86.html - 2013-10-01

2013-10-01 0 0 What is the cyclic redundancy check (CRC) calculation time formula for different values of n (where n is the number of divisor)?

The handbooks for Cyclone® III, Cyclone IV, Cyclone V,  Arria® II, Arria V, Stratix® IV, and Stratix V devices show the maximum and minimum CRC calcul…
www.altera.com/support/kdb/solutions/rd09252013_345.html - 2013-10-01

2013-10-23 0 0 Stratix® III Pin Connection Guidelines: Known Issues

Issue 137246: Version 1.3 If the JTAG connections are not used, you need to  connect the TCK to GND, TDI and TMS pin to VCCPD, tie the TRST p
www.altera.com/support/kdb/solutions/rd09102013_29.html - 2013-10-01

2013-10-01 0 0 What are the maximum and minimum clock frequencies when driving the EDCRC block from user logic?

The following application notes describe how to use error detection cyclic redundancy check (CRC):AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (PDF)…
www.altera.com/support/kdb/solutions/rd04292013_781.html - 2013-10-01

2013-09-30 0 0 Why do I see the read data of all High when I read the last address from M20K RAM ?

This is caused by software issue. Impact of this issue is when you use StratixV device M20K with Single Port RAM and dual clock port mode.
www.altera.com/support/kdb/solutions/rd09102013_708.html - 2013-09-30

2013-09-26 0 0 When accessing the ETH_RX_DATA register, why does the CPU interface of the CPRI MegaCore function stop resopnding?

When the ETH_RX_DATA register is accessed on the CPU interface, the CPRI MegaCore® function waits until a frame of Ethernet data is received on the Fast C & M interface.&n…
www.altera.com/support/kdb/solutions/rd09232013_349.html - 2013-09-26

2013-11-05 100000 10.0 0 Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of '<clock frequency>' on node '<ALTLVDS instance name>pll_fclk~PLL_OUTPUT_COUNTER'

You may get this error when selecting phase shift values for the What is the phase alignment of 'rx_in' with respect to 'rx_inclock' parameter in the ALTLVDS_RX megafunction. …
www.altera.com/support/kdb/solutions/rd09202013_56.html - 2013-09-25

2013-11-12 130000 13.0 0 Where do I find the driver software and documention for the Altera 16550 Compatible UART?

The Altera® 16550 Compatible UART IP MegaCore® function incorrectly appears as a component in Qsys for Quartus® II software version 13.0, and is not included in vers…
www.altera.com/support/kdb/solutions/rd09172013_912.html - 2013-09-25

2013-09-25 130000 13.0 0 Why does the Triple Speed Ethernet MegaCore Function not generate XOFF / XON pause frames even when the XOFF / XON registers or XOFF / XON I/O pins are asserted?

Due to an issue with the Triple Speed Ethernet MegaCore® function, XON / XOFF pause frames may not be generated if you disable the Enable MAC 10/100 half duplex support o…
www.altera.com/support/kdb/solutions/rd09182013_547.html - 2013-09-25

2013-09-25 0 0 What is the mapping between the Handbook defined Device Quadrants and the Quartus II Software Chip Planner Regional Clock Regions for Stratix V devices?

The mapping between the Handbook defined Device Quadrants and the Quartus® II Software Chip Planner Regional Clock Regions for Stratix® V devices is as follows: Device Quadrant 1 …
www.altera.com/support/kdb/solutions/rd09252013_138.html - 2013-09-25

2013-11-20 0 0 How can I set the input clock phase shift for capturing data in the ALTLVDS_RX megafunction?

The ALTLVDS_RX megafunction provides a limited drop-down list selection for setting the clock and data relationship in non-DPA mode.  The parameter is What is the phase alignm…
www.altera.com/support/kdb/solutions/rd09202013_385.html - 2013-09-25

2014-06-30 100100 10.1 0 Warning 12283 – Assignment INPUT_TERMINATION on transceiver refclk clk buf/pin pcie_ref_clk is not supported

You get this warning in the Quartus® II software if you implement the assignment specified in the Transceiver Clocking in Stratix® V Devices chapter in volume 2 of the&nb…
www.altera.com/support/kdb/solutions/rd09242013_212.html - 2013-09-25

2013-10-03 120100 12.1 0 Why are the Type 9 frames corrupted in the RapidIO II MegaCore function?

Due to an issue with the RapidIO® II MegaCore® function, Type 9 frames may be corrupted if the payload size is not a multiple of eight bytes.
www.altera.com/support/kdb/solutions/rd09182013_704.html - 2013-09-25

2014-04-13 130000 13.0 0 What is the correct number of reconfiguration interfaces required for a XAUI PHY IP when using Stratix V, Arria V, and Cyclone V transceiver devices?

The correct number of reconfiguration interfaces required for a XAUI PHY IP when using Stratix® V, Arria® V, and Cyclone® V transceiver devices is five. The XAUI PHY IP MegaWizard…
www.altera.com/support/kdb/solutions/rd09022013_981.html - 2013-09-24

2013-09-24 0 0 Does Cyclone V -C8 device support DDR3 Soft Memory Controller?

Cyclone® V C8 device does not support DDR3 with Soft Memory Controller (SMC). You have to select faster speed grade device for DDR3 SMC.
www.altera.com/support/kdb/solutions/rd09122013_584.html - 2013-09-24

2013-09-24 0 0 When using UniPHY IP in Stratix V devices, what are the options for changing the calibrated OCT termination values from the default values ?

The default Input and Output calibrated termination resistance values are applied by running the <IP_name>_p0_pin_assignments.tcl script.After performing board level simulati…
www.altera.com/support/kdb/solutions/rd08142013_557.html - 2013-09-24

2013-09-24 0 130001 13.0 SP1 Why do I see functional problems in my clocked video input (cvi) module?

You may see functional(hardware) problems for the CVI module for designs created using the Quartus® II software versions 13.0 and earlier as internal timing violations may be …
www.altera.com/support/kdb/solutions/rd09112013_546.html - 2013-09-24

2014-03-04 130001 13.0 SP1 0 Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ?

In the the Quartus®  II 13.0SP1 release, the Cyclone V SoC Hard Processor System Component SDRAM Interface Vref port is incorrectly configured as an output. If you are ge…
www.altera.com/support/kdb/solutions/rd09202013_752.html - 2013-09-24

2013-09-24 20202 2.2 SP2 0 Can the transceiver PHY in Gigabit Ethernet mode compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation?

No, the transceiver PHY (ALT2GXB, ALT_GXB and Native PHY IP's) in Gigabit Ethernet mode cannot compensate for clock frequency differences between the recovered clock and the refere…
www.altera.com/support/kdb/solutions/rd09182013_734.html - 2013-09-24

2013-09-24 130001 13.0 SP1 0 Why do I get an error when selecting a rank of 4 with 4 chip selects for a DDR3 LRDIMM?

For Stratix V DDR3 memory controllers, when selecting the LRDIMM memory format with the "Number of ranks per slot" set to 4 and the "Number of chip selects per device/DIMM" set to …
www.altera.com/support/kdb/solutions/rd09042013_11.html - 2013-09-24

2013-09-24 0 0 What is the state of unused transceiver transmit pins on Stratix IV, Arria II, and Cyclone IV devices?

The state of unused transceiver transmit pins on Stratix® IV, Arria® II, and Cyclone® IV devices is floating.
www.altera.com/support/kdb/solutions/rd09112013_818.html - 2013-09-24

2013-09-24 120000 12.0 0 Why do I only see configuration pin names listed in my Quartus II software Pin-Out File (.pin) when using dual-purpose pins as regular I/O pins?

If you set dual-purpose configuration pins as regular I/O pins when in user mode, the Quartus® II software generated .pin file will only show their configuration function name…
www.altera.com/support/kdb/solutions/rd11152012_952.html - 2013-09-24

2013-09-26 0 0 Can I connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP?

No, you cannot connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP.
www.altera.com/support/kdb/solutions/rd09112013_153.html - 2013-09-24

2013-09-24 0 0 What is the Moisture Sensitivity Level (MSL) of Excalibur devices?

The MSL of Excalibur™ devices is 3.   This information is printed on the moisture barrier bag that the devices are shipped in.  
www.altera.com/support/kdb/solutions/rd09192013_288.html - 2013-09-24

2013-09-24 120000 12.0 130000 13.0 Why am I seeing a difference in the option of number of chip selects for DDR3 UniPHY IP generated in Quartus II V12.0 and V13.0 and later versions?

The behaviour of DDR3 IP generated in QII V12.0 is incorrect. The number of chip select option for DDR3 UniPHY controller is limited to 2 for both Arria V and Cyclone V device.
www.altera.com/support/kdb/solutions/rd09182013_11.html - 2013-09-24

2013-09-24 130000 13.0 0 Why do I see a Qsys warning for the pll_sharing conduit even when the PLL sharing mode option is set to 'No Sharing' in the UniPHY Megacore settings?

The pll_sharing conduit is exposed in Qsys even when the UniPHY Megacore's PLL sharing mode is set to 'No Sharing'.  This will cause Qsys to issue a warning "**_pll_shari…
www.altera.com/support/kdb/solutions/rd09192013_785.html - 2013-09-24

2013-09-23 0 0 What OS Ports are required by DSE for correct operation?

When using Design Space Explorer (DSE), you may receive the following messages: Info: Point <#> is being started on clientInfo: Point <#> is uploading files to client…
www.altera.com/support/kdb/solutions/rd08282013_907.html - 2013-09-23

2013-09-23 120100 12.1 0 How do I display assertion markers in the ModelSim-Altera wave window?

Assertion markers are not displayed by default in ModelSim-Altera versions associated with the Quartus II software version 12.1 and later.
www.altera.com/support/kdb/solutions/rd09022013_318.html - 2013-09-23

2013-09-23 0 0 Can't open dockable window - can't load library "prj_pjnq.dll". The specified module could not be found

You may see this error when you try to launch the Quartus II software if your antivirus software has blocked the file db_llu.dll from the <Quartus II installation directory>/…
www.altera.com/support/kdb/solutions/rd09022013_411.html - 2013-09-23

2013-09-23 130000 13.0 0 Why does my fPLL phout port have no output duing simulation using ModelSim?

Due to a problem in the Quartus® II software version 13.0 and 13.0sp1, you may see that the fPLL DPA output port phout has no valid output during simulation. This problem…
www.altera.com/support/kdb/solutions/rd06282013_128.html - 2013-09-23

2013-09-23 0 0 Unknown option: -sip

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this error when you execute a Tcl script that has been generated using the Generate Tcl File …
www.altera.com/support/kdb/solutions/rd08272013_433.html - 2013-09-23

2013-09-19 0 0 Why does the Qsys system generation get stuck when running a Pearl script for an on-chip memory component?

Qsys generation may get stuck when executing a pearl script associated with an On-Chip Memory component.  In the "Generate" window, you may see the process stopped at a m…
www.altera.com/support/kdb/solutions/rd09192013_530.html - 2013-09-19

2013-09-18 110000 11.0 0 Example Driver Limitation for DDR, DDR2, and DDR3 Controllers with ALTMEMPHY

This problem affects DDR, DDR2, and DDR3 products with ALTMEMPHY. The driver for the example designs for the DDR, DDR2, and DDR3 controllers with ALTMEMPHY contains a design limit…
www.altera.com/support/kdb/solutions/fb24739.html - 2013-09-18

2013-09-18 100100 10.1 0 PCIe Gen2 Link Training Error When Using Hard Reset Controller

An intermittent PCIe Gen2 Hard IP link-up issue may occur in Quartus II version 13.0SP1 and earlier. When using the hard reset controller in a Gen2 native configuration, the Strat…
www.altera.com/support/kdb/solutions/fb152545.html - 2013-09-18

2013-09-18 130001 13.0 SP1 0 Possible No Fit Errors on Cyclone V HPS Devices

This problem affects DDR2, DDR3, and LPDDR2 products targeting Cyclone V HPS devices. You may encounter cryptic no-fit errors such as: Could not find location with OCT_CAL_BLOCK_I…
www.altera.com/support/kdb/solutions/fb143380.html - 2013-09-18

2013-09-18 120000 12.0 0 Default tCCD for LPDDR2 Devices Hard Codes to 2 Cycles

This problem affects LPDDR2 products. This issue applies to LPDDR2 interfaces, when an LPDDR2-S2 memory device is used. Generated example designs always set tCCD=2 cycles for LPDD…
www.altera.com/support/kdb/solutions/fb51930.html - 2013-09-18

2014-06-30 0 0 How do I map the 8 available transceiver VOD settings in the Stratix V GX IBIS-AMI model to the 64 available settings in the Custom and Low Latency PHY MegaWizards, and Transceiver Toolkit?

You can map the 8 available transceiver VOD settings in the Stratix® V GX IBIS-AMI model to the 64 available settings in the Custom and Low Latency PHY MegaWizards™ and Transceiver…
www.altera.com/support/kdb/solutions/rd09182013_648.html - 2013-09-18

2013-09-18 110100 11.1 0 Error in IP Compiler for PCI Express with Two Virtual Channels

Hard IP variations of the IP Compiler for PCI Express with an Avalon-ST interface that have two virtual channels are missing the rx_st_empty1 signal that indicates whether the rx_…
www.altera.com/support/kdb/solutions/fb31548.html - 2013-09-18

2013-11-19 130001 13.0 SP1 130100 13.1 Is there any issue with Cyclone V SoC HPS support for DDR2 design which has width less than 24 bits?

Due to an issue with the Quartus® II software version 13.0sp1 and earlier, the Cyclone® V SoC HPS support for DDR2 SDRAM controller with UniPHY is not available. A design…
www.altera.com/support/kdb/solutions/rd09102013_448.html - 2013-09-17

2013-09-17 110101 11.1 SP1 120100 12.1 Error (175001) : Could not place pin <pin name>

You will receive this error message if you place 3.3V input signals into an I/O bank that is powered by 2.5V when targeting a Stratix® V device in the Quartus® II software version …
www.altera.com/support/kdb/solutions/rd01122012_91.html - 2013-09-17

2013-09-17 0 0 How can I calculate how much space is left in my configuration device with compression turned on?

You can calculate how much space is left in your configuration device with compression turned on by following these steps: Use a typical compression factor of 30% to 5…
www.altera.com/support/kdb/solutions/rd09062013_259.html - 2013-09-17

2013-09-17 0 0 Is it possible to use the crcblock WYSIWYG component and the CRC_ERROR signal internally without enabling the external CRC_ERROR pin in the Quartus II design software for Stratix V, Arria V, or Cyclone V devices?

Yes, it is possible to use the crcblock WYSIWYG component and the CRC_ERROR signal internally without enabling the external CRC_ERROR pin in the Quartus® II software…
www.altera.com/support/kdb/solutions/rd09062013_327.html - 2013-09-17

2013-09-17 0 0 Error in reading SFL VERSION

You may see the following error if you are trying to program a Jam™ Standard Test and Programming Language (STAPL) Format File (.jam) that was converted from a JTAG Indirect Config…
www.altera.com/support/kdb/solutions/rd09052013_743.html - 2013-09-17

2013-09-17 0 0 How can I achieve the MLAB specification in Simple dual-port x16 depth as specified in the Stratix V device datasheet?

You can achieve the MLAB specification in Simple dual-port x16 depth as specified in the Stratix® V device datasheet if the MLAB Implementation In 16-Bit Deep Mode option is&n…
www.altera.com/support/kdb/solutions/rd09102013_702.html - 2013-09-17

2013-09-17 0 0 Why are the DDR3 controller write-to-read and read-write turnaround times longer than expected?

For UniPHY-based DDR3 memory controllers, the turnaround times are calculated using the following equations: Read-to-write turnaround = ‘CAS latency’ – ‘CAS write latency’ + (‘Burs…
www.altera.com/support/kdb/solutions/rd05132013_938.html - 2013-09-17

2013-09-17 0 0 Warning (11106): Shared VREF <pin number> is used as GPIO <pin name>. This action reduces fmax performance.

VREF pins have a high pin capacitance than other pins in devices that support dual-purpose VREF pins. Avoid using the VREF pins as an I/O pin of a bus or clock function because the…
www.altera.com/support/kdb/solutions/rd07192013_516.html - 2013-09-17

2013-09-17 0 0 Is there an issue with the output clock frequency if you set the duty cycle values other than 50% in the Altera PLL megafunction?

Yes, you may encounter an issue with the output clock frequency when setting duty cycle values other than 50% in the Altera PLL megafunction.  This can occur when using t…
www.altera.com/support/kdb/solutions/rd09042013_243.html - 2013-09-17

2013-09-16 0 0 <Quartus II installation directory>/libstdc++.so.6: version `GLIBCXX_3.4.15' not found

You may see this error message when using Google Chrome browser with the 64-bit version of the Quartus® II software on Linux platforms. This error occurs because the vers…
www.altera.com/support/kdb/solutions/rd08262013_741.html - 2013-09-16

2014-04-20 120100 12.1 0 Errata - Stratix V and Arria V timing model issues in the Quartus II software version 13.0 SP1

Timing models for Stratix® V and Arria® V devices are being updated in the the Quartus® II software version 13.0 SP1 DP5 to address issues in version 13.0 SP1. During timing…
www.altera.com/support/kdb/solutions/rd08122013_511.html - 2013-09-16

2013-09-16 0 0 Why does my design use high-speed tiles when the Programmable Power Maximum High-Speed Fraction of Used LAB Tiles logic option is set to 0?

Although the Quartus® II Help definition of the Programmable Power Maximum High-Speed Fraction of Used LAB Tiles logic option does not specify any limitations, this option onl…
www.altera.com/support/kdb/solutions/rd08232013_234.html - 2013-09-16

2013-09-16 130000 13.0 0 You enabled or disabled the following Design Assistant rules: <list of rules> but at least one of the rules contains an illegal value

Due to a change in the Quartus II software version 13.0, you may see this error if your Quartus II Settings File (.qsf) enabled Design Assitant checking for rules M101, M102, M103,…
www.altera.com/support/kdb/solutions/rd08262013_176.html - 2013-09-16

2013-09-16 0 0 How do I determine the package option of my 1152 Pin FineLine Ball-Grid Array (FBGA)--Flip Chip device?

Your Altera® device is an 1152-Pin FineLine Ball-Grid Array (FBGA)-option 2-Flip Chip package if it is impacted by Process Change Notification (PCN) 0902 (PDF), otherwise the …
www.altera.com/support/kdb/solutions/rd05222009_272.html - 2013-09-16

2013-09-12 130000 13.0 0 Why does the EMIF toolkit generate a blank report when masking a rank?

Due to a problem in the Quartus® II software version 13.0 and later, the EMIF Toolkit may generate a blank report when masking a rank and recalibrating.
www.altera.com/support/kdb/solutions/rd09112013_777.html - 2013-09-12

2013-09-12 130001 13.0 SP1 0 Error (175001): Could not place HPHY

When you implement DDR3L Hard Memory Controller (HMC) and DDR3L Hard Processor System (HPS) in one project using Arria® V ST device in Quartus® II software version 13.0SP1, you may…
www.altera.com/support/kdb/solutions/rd08052013_958.html - 2013-09-12

2013-09-12 0 0 Can I swap DQ pins of the HMC to ease routing congestion?

After assigning the dedicated DQ pins of the FPGA according to the index on the mem_dq port, it is OK to swap the data bits on the board. Please make sure to only swap data bits wi…
www.altera.com/support/kdb/solutions/rd06102013_643.html - 2013-09-12

2013-09-12 110100 11.1 0 Error: Error during execution of "{C:/altera/12.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally

You may experience the above error when generating a UniPHY-based memory controller. The error occurs because one of the system environment variables 'TEMP' points to a network dri…
www.altera.com/support/kdb/solutions/rd02192013_986.html - 2013-09-12

2013-09-11 130000 13.0 0 Why do I get the following error during the Quartus II Analysis & Synthesis when upgrading an Avalon Memory-Mapped (Avalon-MM) Stratix V Hard IP for PCI Express IP core design from version 12.1 to 13.0?

You will get the following error message during Quartus® II Analysis & Synthesis when upgrading an Avalon®-MM Stratix® V Hard IP for PCI Express® IP core design from version 12…
www.altera.com/support/kdb/solutions/rd08062013_201.html - 2013-09-11

2013-12-16 120001 12.0 SP1 0 PCIe Gen2 Link Training Error When Using Hard Reset Controller

An intermittent PCIe Gen2 Hard IP link-up issue may occur in Quartus II version 13.0SP1 and earlier. When using the hard reset controller in a Gen2 native configuration, the Arri…
www.altera.com/support/kdb/solutions/fb152545_a5gz.html - 2013-09-11

2012-06-26 120001 12.0 SP1 0 PCIe Gen2 Link Training Error When Using Hard Reset Controller

An intermittent PCIe Gen2 Hard IP link-up issue may occur in Quartus II version 13.0SP1 and earlier. When using the hard reset controller in a Gen2 native configuration, the Arri…
www.altera.com/support/kdb/solutions/fb152545_a5gz.html - 2013-09-11

2013-09-11 0 130000 13.0 Why can I not find the the coef_seq.cpp in \fir_compiler\misc, as described in the user guide?

  The FIR MegaCore® User Guide states that both the C++ source code file (coef_seq.cpp) and  the window executable program (coef_seq.exe) for FIR filter Coefficie…
www.altera.com/support/kdb/solutions/rd08292013_387.html - 2013-09-11

2013-09-11 0 0 What clock should I use to capture the PIPE interface signals on the test_out bus when using SignalTap II Logic Analyzer?

Use pld8gtxclkout to capture the PIPE signals on the test_out interface using the SignalTap™ II Logic Analyzer.  This clock signal is located in the follow…
www.altera.com/support/kdb/solutions/rd08252013_224.html - 2013-09-11

2013-09-10 130000 13.0 0 Why does the Cyclone V Early Power Estimator (EPE) fail to report a Physical Medium Attachment (PMA) power change when changing Differential Output Voltage (VOD) and Pre-Emphasis settings?

If you change any of the transceiver PMA settings (e.g. VOD or Pre Emphasis) the Channel Power and overall device power remain the same when you are using the Cyclone® V EPE. …
www.altera.com/support/kdb/solutions/rd09062013_432.html - 2013-09-10

2014-06-04 0 0 What happens if the Stratix V device power sequence is not followed?

All Stratix® V devices require a power sequence as specified in the power management section of the device handbook. If this power sequence is not followed, the device may se…
www.altera.com/support/kdb/solutions/rd09042013_538.html - 2013-09-10

2013-09-10 120000 12.0 130000 13.0 Is there a known issue with the size of a file generated using the sof2flash utility in Quartus II software versions 12.1, 12.1 SP1, and 12.0?

Yes, there is a known issue with the size of a file generated using the sof2flash utility in the Quartus® II software versions 12.1, 12.1 SP1, and 12.0.  In the…
www.altera.com/support/kdb/solutions/rd09062013_300.html - 2013-09-10

2013-09-10 0 0 Why does the Early Power Estimator (EPE) show unrealisticly high current values for some voltage rails in the Report Tab?

The EPE tool may show unrealisticly high current values in the report tab if the Regional Language settings in Windows are not set to "English". 
www.altera.com/support/kdb/solutions/rd09062013_325.html - 2013-09-10

2013-09-10 130001 13.0 SP1 0 Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank <bank number> have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists.

This warning will be generated for designs using Cyclone® V devices in the Quartus® II software version 13.0sp1 when using differential and single-ended I/O standards in …
www.altera.com/support/kdb/solutions/rd09042013_949.html - 2013-09-10

2013-09-09 0 0 Is the ramstyle synthesis attribute supported for VHDL memory inference when the memory is implemented using an array of natural types?

Due to a problem in the Quartus® II software versions 13.0 SP1 and earlier, the ramstyle attribute is not supported when inferring memories in VHDL if the memory is implemented usi…
www.altera.com/support/kdb/solutions/rd08222013_795.html - 2013-09-09

2013-09-09 0 0 Why do I see hold timing violations within Altera DDR3 IP on paths where both the source and destination register are placed within a single ALM?

Due to a problem in the Quartus® II software versions 13.0 SP1 and earlier, you may see hold timing violations in your Altera DDR3 IP for paths where both the source and destinatio…
www.altera.com/support/kdb/solutions/rd08222013_556.html - 2013-09-09

2013-09-09 110100 11.1 0 Why does the SignalTap II Logic Analyzer Node Finder not display any signals?

This problem can occur if you have different capitalization between the Project Navigator and the Node Finder. The hierarchy name are case sensitive and different case will represe…
www.altera.com/support/kdb/solutions/rd08152013_498.html - 2013-09-09

2013-09-09 130000 13.0 0 Why does my .sdc file get read twice when I call it using the read_sdc command from another .sdc file?

Due to a problem in the Quartus® II software versions 13.0 and 13.0 SP1, Synopsys Design Constraint (.sdc) files called using the read_sdc command may be read twice during compilat…
www.altera.com/support/kdb/solutions/rd08222013_21.html - 2013-09-09

2013-09-09 0 0 Can I ignore unconstrained clocks in ALTUFM_SPI module in Max V devices?

The clocks *|dffe28 and *|dffe31 are not timing sensitive. You can safely ignore these unconstrained clocks in the ALTUFM_SPI module. This affects designs targeting MAX® …
www.altera.com/support/kdb/solutions/rd08202013_447.html - 2013-09-09

2013-09-09 0 0 {*Name Protected*} (*/stratixv_atoms.vhd: line 5355, position 21) and verilog parameter being overridden {*Name Protected*}.{*Name Protected*} (*/stratixv_atoms_ncrypt.v: line -1, position -1) are not type compatible.

You may see this error when simulating a VHDL design in the Cadence NC-Sim software if the VHDL instantiates lower level Verilog HDL files.
www.altera.com/support/kdb/solutions/rd08222013_710.html - 2013-09-09

2013-09-09 0 0 Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_split_bits_utility.cpp, Line: 612

Due to a problem in the Quartus® II Software version 13.0 SP1 and earlier, you may see this error when compiling a design using the Partial Reconfiguration (PR) or Config…
www.altera.com/support/kdb/solutions/rd08222013_912.html - 2013-09-09

2013-09-09 0 0 Why do I see "Cannot place <n> nodes into a single ALM" fitting errors when using incremental compilation Post-Fit netlist types?

Due to a problem in the Quartus® II Software versions 13.0 SP1 and earlier, you may experience fitting issues when using incremental compilation Post-Fit netlist types where the Fi…
www.altera.com/support/kdb/solutions/rd08222013_171.html - 2013-09-09

2013-12-10 100100 10.1 120100 12.1 Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Issue

The Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide includes a Gen2 x8 example design. However, Gen2 CvP is not available for Stratix V devices.
www.altera.com/support/kdb/solutions/fb152536_a5gz.html - 2013-09-06

2013-09-09 100100 10.1 120100 12.1 Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Issue

The Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide includes a Gen2 x8 example design. However, Gen2 CvP is not available for Stratix V devices.
www.altera.com/support/kdb/solutions/fb152536.html - 2013-09-06

2013-09-05 0 0 Are the SerialLite I and SerialLite II IP protocols compatible?

No, the SerialLite I and SerialLite II IPs are incompatible due differences in the protocol layer. These differences include the location of the SOP (Start of Packet), EO…
www.altera.com/support/kdb/solutions/rd09042013_392.html - 2013-09-05

2013-09-05 0 0 Are the SerialLite II and SerialLite III IP protocols compatible?

No, the SerialLite II and SerialLite III IPs are incompatible due the different encoding schemes used by each. SerialLite II uses 8B/10B encoding and SerialLite III uses …
www.altera.com/support/kdb/solutions/rd09042013_245.html - 2013-09-05

2013-09-05 0 0 Why does TimeQuest report the incorrect freqency for coreclkout when using the ATX PLL with the PCIe IP core for Stratix V devices?

This problem occurs when implimenting a Gen 1 or Gen 2 PCIe® IP core using the ATX PLL in the Arria® V GZ or Stratix® V device family.  For ES devices, the…
www.altera.com/support/kdb/solutions/rd08082013_507.html - 2013-09-05

2013-09-04 0 0 Do I need to set the TD bit in the first dword of the PCI Express TLP header to generate and forward ECRC?

The PCI Express® Hard IP core requires that the Application Layer set the TD bit for each transmitted TLP header.
www.altera.com/support/kdb/solutions/rd08062013_961.html - 2013-09-04

2014-02-16 130001 13.0 SP1 0 Are there any updates to the 10GBASE-KR PHY IP core in Quartus II software version 13.0 SP1 dp1?

In certain high error conditions, the 10GBASE-KR PHY IP core link training algorithm selects a post-tap value that is too low.
www.altera.com/support/kdb/solutions/rd07222013_90.html - 2013-09-04

2013-09-04 0 0 Is there an indication that the Application Layer has received a PME_to_ACK message using the Avalon-MM Arria V Hard IP for PCI Express IP core ?

The Avalon-MM Arria® V Hard IP for PCI Express® IP core does not indicate to the Application Layer when it receives a PME_to_ACK TLP message.  Because of this l…
www.altera.com/support/kdb/solutions/rd08062013_489.html - 2013-09-04

2013-09-04 130000 13.0 0 Why do I get the following error during the Quartus II Analysis & Synthesis when upgrading a Avalon-MM Stratix V Hard IP for PCI Express IP core design from version 12.1 to v13.0?

Error (12077): Node instance "auto_hub" instantiated with unknown parameter "BROADCAST_FEATURE"Error (12154): Can't elaborate inferred hierarchy "sld_hub:auto_hub" There is an issu…
www.altera.com/support/kdb/solutions/rd09042013_183.html - 2013-09-04

2013-09-03 130000 13.0 0 Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value

You might see this error when entering phase_shift values for output clocks in the Altera PLL megafunction in the Quartus® II software version 13.0: Error: PLL Output Counter…
www.altera.com/support/kdb/solutions/rd08302013_330.html - 2013-09-03

2013-09-05 0 0 What is the maximum specification of the phasedone low time?

The maximum phasedone low pulse width is 3 scanclk cycles.
www.altera.com/support/kdb/solutions/rd03222010_740.html - 2013-09-03

2013-09-03 0 0 What are the specs for the "ears" or the squared corners of the ground slug for a 144-Pin EQFP package?

The specs for the "ears" or the squared corners of the ground slug for a 144-Pin EQFP package can be found here.
www.altera.com/support/kdb/solutions/rd08292013_488.html - 2013-09-03

2013-08-28 0 0 Error: pcie_hard_ip_0_pcie_bfm_0: add_fileset_file: No such file

During Qsys system generation, the following error message appears if either of the following conditions are true:1) The Quartus® II installation does not include th…
www.altera.com/support/kdb/solutions/rd06302013_418.html - 2013-08-28

2013-08-28 0 0 How should I manage the TAG field for Non-Posted accesses with PCIe Avalon Memory-Mapped (Avalon-MM) interface?

The Hard IP for PCI Express® with Avalon-MM interface requires the TAG field to be set as shown below for Non-Posted accesses.  TAG = 0x00 - 0x07 : Txs Slave Port TAG = 0x08 …
www.altera.com/support/kdb/solutions/rd07222013_277.html - 2013-08-28

2013-08-28 120100 12.1 0 Why does signal detect fail in an Cadence NCSim simulation when switching between Gen1 and Gen3 using the Altera PHY IP Core for PCI Express?

When simulating the Altera® PHY IP Core for PCI Express® with Cadence NCSim targeting the Stratix® V device family, the PCIe® link may fail to detect a receiver when swit…
www.altera.com/support/kdb/solutions/rd08272013_932.html - 2013-08-28

2014-06-26 0 0 Why does TimeQuest report recovery and removal violations for the asynchronous reset paths when compiling the XAUI PHY IP core?

Due to a problem in the XAUI PHY IP core, the embedded Synopsys Design Constraint (SDC) is missing a false path for the paths from tx_reset_n to reset_tx_clk_n_meta/reset_tx_c…
www.altera.com/support/kdb/solutions/rd07032013_800.html - 2013-08-28

2013-11-12 120000 12.0 0 Why do I see excessive receiver latency when using the Low Latency or Native PHY, 10G PCS Basic mode on Stratix V GX or Arria V GZ devices?

You may see excessive receiver latency when using the Low Latency or Native PHY, 10G PCS Basic mode on Stratix® V GX or Arria® V GZ devices under the following conditions: B…
www.altera.com/support/kdb/solutions/rd08012013_685.html - 2013-08-28

2013-08-27 130001 13.0 SP1 0 Why my DDR3 HMC example designs targeting Arria V devices with C5 speed grade at 533MHz failed timing?

The reason for the timing issue is large clock uncertainty. To minimize the clock uncertainty from the PLL, you need to try to maximize the VCO frequency and also keeping the M cou…
www.altera.com/support/kdb/solutions/rd08162013_796.html - 2013-08-27

2013-08-27 130000 13.0 0 Error: Channel PLL Parameter 'output_clock_frequency' is set to an illegal value of ' MHz' and PMA Direct parameter is set to 'false'.

You may encounter the above Quartus® II fitter error if you are using the Cyclone® V Custom PHY in with a transceiver speed grade of -6 and a core speed grade of -7 in Quartus…
www.altera.com/support/kdb/solutions/rd06062013_823.html - 2013-08-27

2013-08-27 130000 13.0 0 How can I generate the VHDL simulation model for the intr_capturer component in the SoC Golden Hardware Reference Design (GHRD)?

The Quartus® II software versions 13.0 and 13.0sp1 provide the capability to generate VHDL models for Qsys system components.  However the VHDL simulation models for the …
www.altera.com/support/kdb/solutions/rd08072013_857.html - 2013-08-27

2013-08-27 0 0 Error (176310): Can't place multiple pins assigned to pin location <pin_number> (<pin_name>)

You may see this pin placement error in the Quartus® II software if you have enabled the Passive Serial (PS)configuration scheme and assigned the DCLK pin as a regul…
www.altera.com/support/kdb/solutions/rd08222013_868.html - 2013-08-27

2013-08-27 120000 12.0 0 How do I modify the "Starting Channel Number" parameter in a Qsys-Generated RapidIO transceiver instance?

The Qsys-generated RapidIO variant will not allow you to modify the "Starting Channel Number" of its transceivers. This applies to the Cyclone® IV, Arria® II and Stratix® IV trans…
www.altera.com/support/kdb/solutions/rd08152013_666.html - 2013-08-27

2013-08-27 0 0 What is the frequency range of SDRAM output clocks in HPS?

In the Cyclone V device handbook, Hard Processor System Technical Reference Manual, SDRAM PLL output clocks are not listed in the Table 2-6. The maximum frequency of each cloc…
www.altera.com/support/kdb/solutions/rd08122013_40.html - 2013-08-27

2013-08-27 130000 13.0 0 Error: xcvr: set_port_property sets an illegal FRAGMENT_LIST for port unused_tx_parallel_data

When using Arria® V transceiver devices, you may see the above transceiver Native PHY MegaWizard™ error in the following configuration when using Quartus II software version 13.0sp…
www.altera.com/support/kdb/solutions/rd08262013_361.html - 2013-08-27

2013-08-27 130001 13.0 SP1 0 Why does the PCIe Hard IP core get stuck in DETECT.QUIET state with Quartus II software version 13.0SP1?

With Quartus® II software version 13.0SP1, the LTSSM for the PCIe® Hard IP for the Arria® V GZ and Stratix® V device family may occasionally get stuck in the DETECT.QUIET…
www.altera.com/support/kdb/solutions/rd08212013_152.html - 2013-08-27

2013-08-27 130000 13.0 0 Why does my Cyclone V SOC board fail to boot from QSPI or FPGA?

The SoC Dev Kit Reference Manual Table 2-11, incorrectly documents the boot source settings for QSPI and FPGA.   
www.altera.com/support/kdb/solutions/rd08192013_560.html - 2013-08-27

2013-08-26 130000 13.0 0 How can I check whether my input pins use the I/O register in the Quartus II software version 13.0 and later?

Beginning with the Quartus® II software version 13.0, the Input Register colum in the Resource Section: Input Pins section of the Fitter report is removed. To verify whether t…
www.altera.com/support/kdb/solutions/rd08072013_496.html - 2013-08-26

2013-08-26 0 0 Can I simulate the altpriority_encoder megafunction?

No, there is no simulation model for the altpriority_encoder megafunction. This megafunction was part of legacy IP and is no longer supported. The megafunction can b…
www.altera.com/support/kdb/solutions/rd08122013_471.html - 2013-08-26

2013-08-26 130001 13.0 SP1 0 Internal Error: Sub-system: SSYN, File: /quartus/synth/ssyn/ssyn_tdb_partition_mgr.cpp, Line: 1654

Due to a problem in Quartus® II software version 13.0 SP1, you may encounter this internal error during synthesis if you have physical synthesis enabled.
www.altera.com/support/kdb/solutions/rd08142013_128.html - 2013-08-26

2014-04-13 0 0 How do I program the dynamic I/O delay chains using the ALTIOBUF megafunction in Stratix V, Arria V, and Cyclone V devices?

Follow these instructions to program the dynamic I/O delay chains using the ALTIOBUF megafunction in Stratix® V, Arria® V, and Cyclone® V devices.  Each IOE programmable dela…
www.altera.com/support/kdb/solutions/rd02272013_65.html - 2013-08-26

2014-07-21 0 0 Why do I get a fatal error when simulating a PLL in ModelSim?

Due to a problem in the Quartus® II software, you may see the following errors when simulating using ModelSim if your design contains an Altera PLL megafunction with…
www.altera.com/support/kdb/solutions/rd08182013_307.html - 2013-08-26

2013-08-29 130001 13.0 SP1 0 Info (20034): Auto device selection is not supported for Arria V device family. The default device, 5AGXFB3H6F35C6, is set

When generating the Altera PLL megafunction targeting Arria® V devices, the file appears to be generated correctly, but the log file generates this info message: Info (2003…
www.altera.com/support/kdb/solutions/rd08232013_458.html - 2013-08-26

2013-08-29 130001 13.0 SP1 0 Info (20034): Auto device selection is not supported for Cyclone V device family. The default device, 5CGXFC7C7F23C8, is set

When generating the Altera PLL megafunction targeting Cyclone® V devices, the file appears to be generated correctly, but the log file generates this info message: Info (20…
www.altera.com/support/kdb/solutions/rd08232013_551.html - 2013-08-26

2013-08-22 110100 11.1 0 hotrst_exit Signal Inactive in Soft Reset Controller for Arria V Hard IP for PCI Express IP Core

The soft reset controller in the Arria V Hard IP for PCI Express IP Core does not assert the hotrst_exit signal when the LTSSM exits the hot reset state.
www.altera.com/support/kdb/solutions/fb142122.html - 2013-08-21

2013-08-20 0 0 Does the ALTASMI_PARALLEL megafunction support execution of the 4BYTEADDREX instruction for EPCQ256 configuration devices?

In the Quartus® II software version 13.0 SP1 and earlier, the ALTASMI_PARALLEL megafunction does not provide a way to issue the 4BYTEADDREX instruction to an EPCQ256 configura…
www.altera.com/support/kdb/solutions/rd08052013_658.html - 2013-08-20

2013-08-20 0 0 What is the active bit mapping of the Arria V GX Custom PHY configured to use the 8B10B block when channel reconfiguration is selected?

The active bit mapping of the Arria® V GX Custom PHY configured to use the 8B10B block when channel reconfiguration is selected is detailed below. Transmitter Parallel Interface …
www.altera.com/support/kdb/solutions/rd08152013_777.html - 2013-08-20

2013-08-21 0 0 AN 625: Stratix® V Device Design Guidelines: Known Issues

Issue 145244: Version 1.0 Guideline 53 for nIO_PULLUP is not correct.  The option to disable the internal pull-up resistors is not supported on Stratix V devices.  …
www.altera.com/support/kdb/solutions/rd08122013_422.html - 2013-08-20

2013-08-20 130000 13.0 0 Error: System.< system name >: "Hardware multiplication type" (muldiv_multiplierType) (EmbeddedMulFast) out of range. Valid ranges: [DSPBlock:DSP Block, LogicElementsFast:Logic Elements, NoneSmall:None]

Due to a problem in the Quartus®  II software version 13.0SP1 and QII13.0, this error may be generated by Qsys when the hardware multiplication type in Nio…
www.altera.com/support/kdb/solutions/rd08052013_128.html - 2013-08-20

2013-08-26 130001 13.0 SP1 0 Info (20034): Auto device selection is not supported for Stratix V device family. The default device, 5SGXEA7H3F35C3, is set

When generating the Altera PLL megafunction targeting Stratix® V devices, the file appears to be generated correctly, but the log file generates this info message: Info (20…
www.altera.com/support/kdb/solutions/rd08142013_815.html - 2013-08-20

2014-06-30 0 0 What output clock should I connect to the Native PHY IP when using a fPLL as a transceiver Tx PLL on Stratix V, Arria V, and Cyclone V transceiver devices?

The output clock used to connect to the Native PHY IP when using a fPLL as a transceiver Tx PLL on Stratix® V, Arria® V, and Cyclone® V transceiver devices will vary depending on w…
www.altera.com/support/kdb/solutions/rd07172013_635.html - 2013-08-20

2013-08-20 0 0 Does Altera comply with the California Proposition 65 Regulations?

Yes, Altera complies with the California Proposition 65 Regulations.  Altera® products do not contain any chemical substance found in the California Proposition 65 Regula…
www.altera.com/support/kdb/solutions/rd08152013_550.html - 2013-08-20

2013-10-31 120000 12.0 0 Why is NIOS II running slowly on my Cyclone V design?

Due to a problem in the Quartus® II software version 12.0 and 12.1, NIOS® II designs may run at a reduced maximum frequency when Embedded Multipliers or LE based Multipliers are se…
www.altera.com/support/kdb/solutions/rd08082013_62.html - 2013-08-20

2013-08-20 130000 13.0 0 Why does OpenCL node locked license not work with multiple ethernet port?

The OpenCL node locked license are generated for specific physical address.  The OpenCL node locked License also only works for the network interface named eth0.&nbs…
www.altera.com/support/kdb/solutions/rd06112013_373.html - 2013-08-20

2013-08-20 130000 13.0 0 What is the address of the "Write to the 'write' bit of the control and status register" in "Table 8: Using the Register-Based Reconfiguration Method to Reconfigure VOD Settings" of AN676?

"Table 8: Using the Register-Based Reconfiguration Method to Reconfigure VOD Settings" of AN676 incorrectly lists the Memory Map Address of the "Write to the 'write' bit of the con…
www.altera.com/support/kdb/solutions/rd08182013_831.html - 2013-08-20

2013-08-20 120000 12.0 0 Which pins are powered by the VCCRSTCLK_HPS supply?

The VCCRSTCLK_HPS supply is used to power the following pins in Arria® V and Cyclone® V SoC devices: HPS_CLK1HPS_CLK2 HPS_PORSEL HPS_nRST HPS_nPOR
www.altera.com/support/kdb/solutions/rd01182013_207.html - 2013-08-20

2014-04-20 0 0 AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions: Known Issues

Issue 133244: Version 2.0 Table 2 shows all bits of the C counter, M counter, and N counter registers are Read/Write. The bypass enable (bit 16) and odd division (bit 17) bits …
www.altera.com/support/kdb/solutions/rd08122013_746.html - 2013-08-20

2013-08-20 130000 13.0 0 Error: Clock Divider node 'inst|altera_xcvr_native_av:txcvr_top_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port.

You may encounter the error above in Cyclone® V and Arria® V transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk in…
www.altera.com/support/kdb/solutions/rd06262013_632.html - 2013-08-20

2013-08-20 130000 13.0 0 Error: Clock Divider node 'inst|altera_xcvr_native_sv:txcvr_top_inst|sv_xcvr_native:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port.

You may encounter the error above in Stratix® V and Arria® V GZ transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input por…
www.altera.com/support/kdb/solutions/rd06172013_580.html - 2013-08-20