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Last Modified Version Found Version Found Version Fixed Version Fixed Document Title, Description, URL
2014-07-08 0 0 Error (175006): Could not find path between source global or regional clock driver and the HMC

You may see the above error when using the DDR3 Hard Memory Controller in a Cyclone® V device if the number of MPFE ports selected in the DDR3 IP GUI exceeds the number of ports su…
www.altera.com/support/kdb/solutions/rd07032014_826.html - 2014-07-08

2014-07-08 0 0 Which voltage supply powers the DEV_OE and DEV_CLR pins in Stratix III and Stratix IV devices?

If the DEV_OE and/or DEV_CLR pin functions are enabled in designs targeting Stratix® III and Stratix IV devices, they are powered by the VCCPGM supply during configu…
www.altera.com/support/kdb/solutions/rd08132009_464.html - 2014-07-08

2014-07-08 120000 12.0 0 Error: Error writing sopcinfo report java.lang.OutOfMemoryError: Java heap space

You may see the following or similar error when generating a large design from Qsys. Error: Error writing sopcinfo report java.lang.OutOfMemoryError: Java heap space
www.altera.com/support/kdb/solutions/rd11152012_160.html - 2014-07-08

2014-07-08 130100 13.1 140000 14.0 Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface?

When comparing the DQ waveforms, you may notice that the measured steady-state read waveform amplitude exceeds the expected value simulated by the IBIS mod…
www.altera.com/support/kdb/solutions/rd05072014_995.html - 2014-07-08

2014-07-07 110100 11.1 140000 14.0 Arria V Hard IP for PCI Express IP Core Speed Grade Support

By default, the Quartus II software selects an Arria V GX -6 part for the Arria V Hard IP for PCI Express IP Core. However, the Arria V GX device only supports -4 and -5 speed gra…
www.altera.com/support/kdb/solutions/fb153645.html - 2014-07-07

2014-07-07 110100 11.1 130101 13.1
Update1
Arria V Hard IP for PCI Express IP Core Transmits Incorrect TS1 During Link Training

The Arria V Hard IP for PCI Express IP Core may send out corrupted TS1 during link training. When sending out corrupted TS1s, the Arria V Hard IP for PCI Express IP Core enters th…
www.altera.com/support/kdb/solutions/fb162810.html - 2014-07-07

2014-07-07 110100 11.1 130100 13.1 Speed Change Issue for Arria V Hard IP for PCI Express IP Core

The Arria V Hard IP for PCI Express IP Core may enter the LTSSM state Recovery.Rcvlock after a speed change from Gen1 to Gen2 or from Gen2 to Gen1.
www.altera.com/support/kdb/solutions/fb125536.html - 2014-07-07

2014-07-07 130100 13.1 0 Internal Error: Sub-system: FTM, File: /quartus/synth/ftm/ftm_arriav_atom_builder.cpp, Line: 484

Due to a problem in the Quartus® II software version 13.1, you may see this Internal Error when compiling a design that uses LPM_MULT.
www.altera.com/support/kdb/solutions/rd06262014_622.html - 2014-07-07

2014-07-07 110100 11.1 130100 13.1 Speed Change Issue for Cyclone V Hard IP for PCI Express IP Core

The Cyclone V Hard IP for PCI Express IP Core may enter the LTSSM state Recovery.Rcvlock after a speed change from Gen1 to Gen2 or from Gen2 to Gen1.
www.altera.com/support/kdb/solutions/fb125536_cv.html - 2014-07-07

2014-07-07 110100 11.1 130101 13.1
Update1
Cyclone V Hard IP for PCI Express IP Core Transmits Incorrect TS1 During Link Training

The Cyclone V Hard IP for PCI Express IP Core may send out corrupted TS1 during link training. After sending out corrupted TS1s, the Cyclone V Hard IP for PCI Express IP Core ente…
www.altera.com/support/kdb/solutions/fb162810_cv.html - 2014-07-07

2014-07-15 130103 13.1
Update3
0 Error (11692): Design cannot be fitted into HSSI strip. 2 pma_aux_blocks under reference clocks set: dup_3ch_tx_pll_refclk[0]

Due to a bug in the Quartus® II software version 13.1.3, you may see the Fitter error above when compiling for Arria® V devices.
www.altera.com/support/kdb/solutions/rd06202014_83.html - 2014-07-07

2014-07-10 0 0 Mismatches Between Some Serial CORDIC MATLAB and RTL Models I

For the serial CORDIC architecture with Phase Accumulator Precision and Angular Resolution both set to values less than or equal to 10, there can be mismatches between the outputs…
www.altera.com/support/kdb/solutions/spr333360.html - 2014-07-04

2014-07-04 0 0 Where can I get the preset files for Altera Cyclone V and Arria V SoC development boards?

The Qsys preset files for the Altera® Cyclone® V and Arria® V SoC development boards can be downloaded from the links below. These preset files can be used in Qsys to create a pr…
www.altera.com/support/kdb/solutions/rd05212014_438.html - 2014-07-04

2014-07-03 0 140000 14.0 How do I get the Regfield Block to work for all Avalon-ST Access Types?

In DSP Builder version 13.1 and earlier, the RegFiled block may work only for one particular bus access type. Pipelined reads are not allowed, so you have to hold the data and addr…
www.altera.com/support/kdb/solutions/rd07032014_253.html - 2014-07-03

2014-07-02 130100 13.1 140000 14.0 How can I implement HPS LOAN IO and confirm timing?

Final timing models for LOAN IO are included in the Quartus®  II software version 14.0, and can be used to confirm timing.  Preliminary timing models for LOAN IO are avai…
www.altera.com/support/kdb/solutions/rd04132014_234.html - 2014-07-02

2014-07-02 130100 13.1 0 Failed to read register CIOCONTROL on device CT_1_3

Due to a problem in SoCEDS version 13.1, this error may be seen in ARM® DS-5 Altera Edition from when targeting Cyclone® V SoC single core devices. 
www.altera.com/support/kdb/solutions/rd05202014_144.html - 2014-07-02

2014-07-02 130000 13.0 0 Which HPS SDRAM Controller command ports are associated with which AXI interfaces?

The Cyclone® V and Arria® V HPS SDRAM controller allows for up to 3 AXI™ interfaces.  The following shows the mapping of SDRAM controller command port to AXI interface read/wr…
www.altera.com/support/kdb/solutions/rd06252014_594.html - 2014-07-02

2014-07-04 130100 13.1 0 #error The Simple Socket Server example requires the simple_socket_server.h

Due to updates in the Triple-Speed Ethernet IP from version 12.0 to version 13.1, users may see the error below if using Nios II Ethernet Standard Design Example’s sopcinfo file do…
www.altera.com/support/kdb/solutions/rd04302014_188.html - 2014-07-02

2014-07-02 130100 13.1 140000 14.0 Why does my Cyclone IV GX Nios II design fail to boot up in V13.1

Due to a problem in the Quartus® II software version 13.1,  Nios® II designs targeting Cyclone IV GX devices using the EPCS IP may not boot correctly.
www.altera.com/support/kdb/solutions/rd03182014_477.html - 2014-07-02

2014-07-02 120101 12.1 SP1 130000 13.0 Why does the “sof2flash” command not working in Quartus II 12.1 sp1 for Cyclone II?

Due to a problem in the Quartus II software version 12.1 SP1,  sof2flash may fail for Nios II projects targeting Cyclone II devices using  EPCS.
www.altera.com/support/kdb/solutions/rd04232013_202.html - 2014-07-02

2014-07-02 130000 13.0 140000 14.0 How can I change the HPS-to-FPGA User Clocks or other HPS clocks in Qsys?

Due to a limitation of the Quartus® II software version 13.1, It is not possible to alter the HPS-to-FPGA user clocks  or other HPS clocks in Qsys. When you enable HPS-to-F…
www.altera.com/support/kdb/solutions/rd04082014_333.html - 2014-07-02

2014-07-02 140000 14.0 0 How can I migrate the Nios II processor /s core to an equivalent Nios II Gen 2 processor /f core ?

The Nios® II Gen 2 processor is released in Quartus® II software version 14.0 with 2 core variations, /e core and /f core. As the Nios II Gen 2 processor does not of…
www.altera.com/support/kdb/solutions/rd06272014_960.html - 2014-07-02

2014-07-04 130000 13.0 0 Error: nios2-convert-ide2sbt: command not found

This error will be generated by the Quartus® II software Version 13.0 and later, when converting IDE project to SBT by using “nios2-convert-ide2sbt”command. nios2-convert-ide2sbt.…
www.altera.com/support/kdb/solutions/rd04092014_957.html - 2014-07-02

2014-07-04 0 0 How can memory be reserved before booting Linux on the Soc?

In order to reserve memory to not be used by Linux running on the SoC Cortex-A9, the Linux kernel must be told what is the top of memory (highest addressable RAM address).  Al…
www.altera.com/support/kdb/solutions/rd06132014_165.html - 2014-07-02

2014-07-02 130000 13.0 140000 14.0 How do I build an Altera DS-5 project without semi-hosting?

Due to a problem in Altera SOS EDS version 13.0 and 13.1, the  Assembler code required to build a non semi-hosted application is missing.
www.altera.com/support/kdb/solutions/rd05232014_85.html - 2014-07-02

2015-01-20 0 0 Why is the voltage higher than expected on VREF*_HPS pins?

Prior to configuration by the Preloader software, the VREF pins within the HPS section of Arria® V and Cyclone® V SoC devices will be configured with a weak pullup. If the regulat…
www.altera.com/support/kdb/solutions/rd05272014_929.html - 2014-07-02

2014-07-04 130100 13.1 0 Linker Error: undefined reference to `ceilf'

When linking a custom HAL driver in the Quartus® II software version 13.1, a undefined reference linker error maybe seen to math.h functions such as ceilf() or floorf() althou…
www.altera.com/support/kdb/solutions/rd04292014_882.html - 2014-07-02

2014-07-04 130100 13.1 0 Why does the preloader cause a kernel panic while booting from FPGA (when CONFIG_PRELOADER_EXE_ON_FPGA == 1)?

When the preloader is configured to boot from FPGA (CONFIG_PRELOADER_EXE_ON_FPGA == 1), the preloader will skip the bridge configuration and not pass the bridge configuration infor…
www.altera.com/support/kdb/solutions/rd06092014_896.html - 2014-07-02

2014-07-04 0 0 How can I calculate Adjusted Peak Performance (APP) for the Cyclone V SoC?

As reference to the document of “A Practitioner’s Guide to Adjusted Peak Performance” by U.S. Department of Commerce, Bureau of Industry and Security (December 2006), Adjusted Peak…
www.altera.com/support/kdb/solutions/rd05192014_707.html - 2014-07-02

2014-07-10 130000 13.0 0 Where is the default location for Qsys generated On-chip memory .hex files?

The default location for Qsys on-chip memory .hex files is <qsys_top_filename>/sythesis/submodules/<qsys_top_filename_onchip_memory>.hex After generation of the Qsys …
www.altera.com/support/kdb/solutions/rd06152014_112.html - 2014-07-02

2014-07-01 0 0 Do the SerialLite II Design Examples on altera.com support VHDL?

The design examples for SerialLite II  IP core on altera.com (http://www.altera.com/support/examples/interfaces-peripherals/exm-seriallite-stratix-v.html) are supported f…
www.altera.com/support/kdb/solutions/rd05292014_814.html - 2014-07-01

2014-07-03 140000 14.0 0 Upgrading the FIR Compiler IP Core in the Quartus II Software Version 14.0 Generates a Cryptic Error Message

You see a cryptic error in the Quartus® II software version 14.0 when you open a design from a previous version of the Quartus II software. This errors occurs when the design …
www.altera.com/support/kdb/solutions/fb21215.html - 2014-07-01

2014-07-01 0 0 How can I migrate my Nios II processor design to the Nios II Gen 2 processor?

The Nios® II Gen 2 processor is introduced in the Quartus® II software version 14.0. A migration script is provided for users to migrate from the Nios II processor to the…
www.altera.com/support/kdb/solutions/rd06262014_201.html - 2014-07-01

2014-07-01 120100 12.1 0 Some RapidIO II IP Core Port 0 Capture CSRs Do Not Update Correctly

The RapidIO II IP core Port 0 Attributes Capture CSR (offset 0x348) and Port 0 Packet/Control Symbol Captures CSRs (offsets 0x34C, 0x350, 0x354, and 0x358) do not update correctly…
www.altera.com/support/kdb/solutions/fb174685.html - 2014-07-01

2014-07-01 130100 13.1 0 Why does the tx_path_delay_10g_data and tx_path_delay_1g_data signal descriptions refer to a data width of 16/22 for the Arria V and Stratix V devices in the Low Latency Ethernet 10G MAC User Guide?

Due to a mistake in "Table 5-16: IEEE 1588v2 Egress Transmit Signals" of the Altera® Low Latency Ethernet 10G MAC User Guide (PDF) the tx_path_delay_10g_data and tx_path_delay_1g…
www.altera.com/support/kdb/solutions/rd02282014_633.html - 2014-07-01

2014-07-01 130100 13.1 140000 14.0 How do I simulate the Stratix V PCI Express Gen3 PIPE Mode?

Software version 13.1 of the Arria® V GZ and Stratix® V Hard IP for PCI Express® Gen3 PIPE simulation only supports Synopsys (VCS) simulator. To use other simulators, ple…
www.altera.com/support/kdb/solutions/rd02242014_859.html - 2014-07-01

2014-07-01 130100 13.1 0 Why does the rx_latency_adj_10g and tx_latency_adj_10g signal descriptions refer to 1g for the Arria V and Stratix V devices in the Altera Transceiver PHY IP User Guide?

Due to a mistake in "Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs" of the Altera® Transceiver PHY IP Core User Guide (PDF) the rx_latency_adj_10g and …
www.altera.com/support/kdb/solutions/rd02282014_637.html - 2014-07-01

2015-01-21 130100 13.1 0 How do I run SerialLite III streaming mode simulation for advanced clocking mode?

The SerialLite III testbench example design generated with the IP core uses standard clocking mode (SCM) and default parameter settings. To run simulation in advance…
www.altera.com/support/kdb/solutions/rd05072014_796.html - 2014-07-01

2014-06-30 130100 13.1 140000 14.0 50G Interlaken and 100G Interlaken MegaCore Functions Upgrade to Quartus II Software v13.1 With Default Data Rate

If you upgrade a 50G Interlaken IP core instance or a 100G Interlaken IP core instance from a version that predates the Quartus II software v13.1 release, to the 13.1 version, usi…
www.altera.com/support/kdb/solutions/fb169110.html - 2014-06-30

2014-06-25 140000 14.0 0 IP appears unavailable in the 14.0 Quartus II software release when installed on Linux

If you install the Quartus® II software release version 14.0 on the Linux platform without any devices, some of the available IP might appear to be unavailable. When you insta…
www.altera.com/support/kdb/solutions/fb204051.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Re-Generation Fails for Arria V GZ Hard IP for PCIe Using MegaWizard Plug-In Manager

If you try to edit an existing Arria V GZ Hard IP for PCI Express variant using the version 13.1.1 of the MegaWizard Plug-In Manager, the MegaWizard does not recognize the variant…
www.altera.com/support/kdb/solutions/fb179149_avgz.html - 2014-06-30

2014-07-04 140000 14.0 140000 14.0 Riviera-PRO does not support verification IP VHDL BFMs

Aldec® Riviera-PRO™ Advanced Verification Platform versions prior to 2014.02 do not support verification IP VHDL bus functional models (BFMs). There is no response to VH…
www.altera.com/support/kdb/solutions/fb192539.html - 2014-06-30

2014-05-12 130100 13.1 140000 14.0 Transmit Path: CRC Insertion Must Be Turned On

For Low Latency Ethernet 10G MAC designs that turn on PTP 1-step clock support, you must enable CRC insertion. If you do not configure CRC insertion, you may get incorrect data fr…
www.altera.com/support/kdb/solutions/fb160653.html - 2014-06-30

2014-07-03 140000 14.0 0 Arria V and Cyclone V HPS Designs May Fail to Compile with NC-Sim

This problem affects Arria V And Cyclone V HPS interfaces. The NC-Sim simulator requires that each file contain a time scale directive. Some of the Altera Verilog or System Verilo…
www.altera.com/support/kdb/solutions/fb207090.html - 2014-06-30

2014-06-25 140000 14.0 0 Device family mismatch when upgrading the device for your IP core

In the Quartus® II software release version 14.0, the Upgrade IP Components dialog box displays the original target device for each IP core, and indicates any mismatch with yo…
www.altera.com/support/kdb/solutions/fb200763.html - 2014-06-30

2014-11-27 110100 11.1 130100 13.1 Hardware and software simulation results differ when using preadder mode with an unsigned signal

This simulation issue was found in the Quartus II software release version 13.0, but impacts versions 11.1 through 13.0. When you directly instantiate digital signal p…
www.altera.com/support/kdb/solutions/fb106250.html - 2014-06-30

2014-06-24 120000 12.0 140000 14.0 Maximum pending read values in clock crossing bridges for designs migrated from SOPC Builder to Qsys might cause an out of memory error

In a design migrated from SOPC Builder to Qsys, the clock crossing bridge might be parameterized with a large maximum pending reads value. The maximum value causes Qsys to attempt…
www.altera.com/support/kdb/solutions/fb57060.html - 2014-06-30

2014-06-30 0 0 Warning (10230): Verilog HDL assignment warning at <design>.v(<line number>): truncated value with size 32 to match size of target n

You may get this warning in the Quartus® II software when synthesizing an unsigned integer in Verilog HDL as shown in the below example: reg [8:0] COUNT;always @ (posedg…
www.altera.com/support/kdb/solutions/rd06102014_970.html - 2014-06-30

2014-06-30 130001 13.0 SP1 140000 14.0 Warning Message Indicates RapidIO IP Core Preliminary Support for Arria V, Cyclone V, and Stratix V Devices

The RapidIO MegaCore function v13.0 SP1 and later provides final support for Arria V, Cyclone V, and Stratix V devices. However, when your RapidIO MegaCore function targets one of…
www.altera.com/support/kdb/solutions/fb166724.html - 2014-06-30

2014-06-24 140000 14.0 0 ALTFP_EXP fails to compile when using VHDL

ALTFP_EXP fails to compile when using VHDL on the Arria® V, Cyclone® V, or Stratix® V devices.
www.altera.com/support/kdb/solutions/fb196219.html - 2014-06-30

2014-07-02 120000 12.0 0 Calibration Failure Occurs when RELEASE_CLEARS_BEFORE_TRI_STATES is On

This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products. UniPHY-based memory interfaces generated in the Quartus II software version 11.0 or later and targeting…
www.altera.com/support/kdb/solutions/fb40520.html - 2014-06-30

2014-06-30 0 0 Do Altera Quad Serial Configuration (EPCQ) devices support the subsector erase operation?

Yes, Altera® Quad Serial Configuration (EPCQ) devices do support the subsector erase operation.The operation code for subsector erase is b'0010 000.
www.altera.com/support/kdb/solutions/rd05212014_564.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II IP Core Logical/Transport Layer Error Detect Register Does Not Behave as Documented

The RapidIO II IP core Logical/Transport Layer Error Detect CSR (offset 0x308) should indicate detected errors only for error types that are enabled in the Logical/Transport Layer…
www.altera.com/support/kdb/solutions/fb167949.html - 2014-06-30

2014-07-04 130000 13.0 130100 13.1 Verilog and VHDL simulation error in Riviera-PRO: "# ALOG: Error: VCP2120 Syntax error in ITF file for unit..."

When compiling Verilog and VHDL simulation scripts in the Aldec® Riviera-PRO™ Advanced Verification Platform, the following error occurs: # ALOG: Error: VCP2120 Syntax e…
www.altera.com/support/kdb/solutions/fb104346.html - 2014-06-30

2014-06-30 0 130000 13.0 Why are corrupted data packets received at the Atlantic user interface when Retry-on-error option is enabled for priority packets in SerialLite II.

Due to an issue with the Altera® SerialLite II MegaCore function, you can receive corrupted data packets when the Retry-on-error option is enabled. This is due to the co…
www.altera.com/support/kdb/solutions/rd06012014_13.html - 2014-06-30

2014-07-11 130100 13.1 140000 14.0 altera_fp_functions compare function generates top level file without required port

When you create compare functions for the floating-point IP cores in the 13.1 Quartus® II software release, the top-level .vhd file is generated without the required "b" port.…
www.altera.com/support/kdb/solutions/fb172292.html - 2014-06-30

2014-07-04 130000 13.0 130100 13.1 Avalon-ST interface VHDL BFM simulations fail in Riviera-PRO

When simulating designs in the Aldec® Riviera-PRO™ Advanced Verification Platform, Avalon® Streaming (Avalon-ST) interface bus functional models (BFMs) fail with the…
www.altera.com/support/kdb/solutions/fb100238.html - 2014-06-30

2014-06-30 130001 13.0 SP1 0 Error (175001): Could not place Transmitter channel

Due to a bug in Quartus® II software versions 13.0 and 13.1, you may see the Fitter error above if you have two or more transceiver channels with data rates higher than 6.5536 Gbps…
www.altera.com/support/kdb/solutions/rd05292014_917.html - 2014-06-30

2014-07-03 140000 14.0 0 pll_sharing Warning Message May Appear

This problem affects UniPHY-based DDR3, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. When you create a new external memory interface in the Quartus II software, you may see th…
www.altera.com/support/kdb/solutions/fb203048.html - 2014-06-30

2014-06-24 140000 14.0 0 Quartus II software version 14.0 simulations containing Avalon Interrupt Source fail in Cadence NC-Sim version 13.10

The Quartus® II software release version 14.0 simulations containing the Avalon® Interrupt Source fail during the elaboration stage in Cadence® NC-Sim® version 13.…
www.altera.com/support/kdb/solutions/fb181346.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Has Incorrect Information About the Port 0 Error and Status CSR

According to the RapidIO II MegaCore Function User Guide, any of the following three link protocol violations causes the RapidIO II IP core input port to transition to the Input E…
www.altera.com/support/kdb/solutions/fb169618.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Re-Generation Fails for Stratix V Hard IP for PCIe Using MegaWizard Plug-In Manager

If you try to edit an existing Stratix V Hard IP for PCI Express variant using the version 13.1.1 of the MegaWizard Plug-In Manager, the MegaWizard does not recognize the variant …
www.altera.com/support/kdb/solutions/fb179149.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Simulation Fails for Cyclone V Hard IP for PCIe When Re-Generated Using MegaWizard Plug-In Manager

If you try to edit an existing Cyclone V Hard IP for PCI Express variant using the version 13.1. Update 1 of the MegaWizard Plug-In Manager, the model generation phase fails.
www.altera.com/support/kdb/solutions/fb171292_cv.html - 2014-06-30

2014-07-04 130000 13.0 130001 13.0 SP1 The 13.0 Quartus II software release issues a warning message for Cyclone V I/O pad placement

The 13.0 Quartus® II software release does not include the following two I/O restriction rules for the Cyclone® V device: The single-ended I/O to true differential I/O pla…
www.altera.com/support/kdb/solutions/fb117876.html - 2014-06-30

2014-06-30 0 0 Why does the HDL Design file fail to generate from my .bdf file?

Due to a problem in Quartus® II software version 13.1 and earlier, you may see the HDL Design file is not generated from a Block Design File (.bdf) file when you select File &…
www.altera.com/support/kdb/solutions/rd06182014_351.html - 2014-06-30

2014-06-30 120000 12.0 140000 14.0 CPRI IP Core RE Slave May Start Up or Reset in Master Clocking Mode

The value in the CPRI IP core CPRI_CONFIG register operation_mode field specifies whether the IP core is in master clocking mode or in slave clocking mode. The reset value of this…
www.altera.com/support/kdb/solutions/fb176416.html - 2014-06-30

2014-07-03 140000 14.0 0 Error When Simulating Stratix V MAC with XAUI PHY Design Example Using ModelSim-Altera Edition 10.1e

You will encounter the following fatal error message when attempting to simulate the Stratix V MAC with XAUI PHY design example using ModelSim-Altera version 10.1e: "# Fatal error…
www.altera.com/support/kdb/solutions/fb206391.html - 2014-06-30

2014-06-24 140000 14.0 0 Mentor Verification IP BFMs violate the AMBA AXI and ACE Protocol Specification

The Mentor® Verification IP (VIP) Altera® Edition AXI3™, AXI4™ and AXI4-Lite™ master bus functional models (BFMs) violate the AMBA® AXI and ACE Proto…
www.altera.com/support/kdb/solutions/fb201380.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Re-Generation Fails for Cyclone V Hard IP for PCIe Using MegaWizard Plug-In Manager

If you try to edit an existing Cyclone V Hard IP for PCI Express variant using the version 13.1.1 of the MegaWizard Plug-In Manager, the MegaWizard does not recognize the variant …
www.altera.com/support/kdb/solutions/fb179149_cv.html - 2014-06-30

2014-07-04 130000 13.0 130100 13.1 SOPC Builder generation failure errors: "mm_master_bfm_0: Generated HDL with parameters is not supported in the classic flow" and "mm_slave_bfm_0: Generated HDL with parameters is not supported in the classic flow"

In the Quartus® II software release version 13.0, SOPC Builder designs with verification IP master and slave bus functional models (BFMs) fail during system generation. The ge…
www.altera.com/support/kdb/solutions/fb96838.html - 2014-06-30

2014-06-25 140000 14.0 0 Compilation results in the Quartus II software release version 14.0 differ when using different num_parallel_processors .qsf values

In the Quartus® II software release version 14.0, if you compile a design using the quartus_advanced_physical_optimization Quartus II Settings File (.qsf), using different val…
www.altera.com/support/kdb/solutions/fb209248.html - 2014-06-30

2014-06-24 130000 13.0 130100 13.1 Deterministic Latency PHY IP Core fails VHDL simulation in Cadence NC-Sim

When simulating with VHDL in Cadence® NC-Sim®, the 13.0 Quartus® II software release of the Deterministic Latency PHY IP Core fails because the wrong parameter sequenc…
www.altera.com/support/kdb/solutions/fb129858.html - 2014-06-30

2014-07-02 140000 14.0 0 JESD204B IP Core Design Example Simulation Hang When Running in VCS/VCSMX Simulator

The JESD204B IP core design example simulation hangs when you run the simulation file using VCS or VCSMX simulator. This issue affects all versions that support the JESD204B IP co…
www.altera.com/support/kdb/solutions/fb206914.html - 2014-06-30

2014-07-03 120000 12.0 0 Limitations on Support for pre-11.1 UniPHY External Memory Interfaces

This problem affects all UniPHY-based external memory interfaces, including DDR2, DDR3, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. You cannot open and modify UniPHY-based ex…
www.altera.com/support/kdb/solutions/fb199597.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Claims Wrong Number of TX Maintenance Windows

According to the RapidIO II MegaCore Function User Guide, the RapidIO II IP core can be programmed with up to 16 TX Maintenance translation windows. However, the IP core can be pr…
www.altera.com/support/kdb/solutions/fb162605.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Error in Avalon-MM Master Write Transaction Burstcount Calculation

According to the RapidIO II MegaCore Function User Guide, in the table that lists the calculations for burstcount and byteenable on the Avalon-MM interface for a RapidIO write tra…
www.altera.com/support/kdb/solutions/fb164100.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 40-100GbE MAC and PHY IP Core MegaCore Function rx_recovered_clk Signal is Missing from Top Level Interface

If you turn on Synchronous Ethernet support in the 40-100GbE parameter editor with the Enable SyncE support parameter, the IP core is configured with two input reference clocks, o…
www.altera.com/support/kdb/solutions/fb165452.html - 2014-06-30

2014-06-25 140000 14.0 0 Migrating your Stratix V device design from the Quartus II software release version 13.1 to release version 14.0 generates error messages

When you upgrade your Stratix® V device design IP from the Quartus® II software release version 13.1 to release version 14.0, you might generate the following error messag…
www.altera.com/support/kdb/solutions/fb198233.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II IP Core Logical/Transport Layer Device ID Capture Register and Logical/Transport Layer Address Capture Register Do Not Update Correctly When I/O Logical Layer Slave Module Sets Illegal Transaction Decode

The RapidIO II IP core Logical/Transport Layer Device ID Capture CSR (offset 0x318) and Logical/Transport Layer Address Capture CSR (offset 0x314) do not update correctly when an …
www.altera.com/support/kdb/solutions/fb175403.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Incorrectly Indicates Receiving an IDLE2 or Change in Received CS Field Command Triggers an Interrupt

According to the RapidIO II MegaCore Function User Guide, if you set the Enable CMD changed interrupt bit in the LP-Serial Lane n Status 2 register (offsets 0x218, 0x238, 0x258, a…
www.altera.com/support/kdb/solutions/fb163538.html - 2014-06-30

2014-07-04 130100 13.1 130103 13.1
Update3
The 13.1 Quartus II software release generates the error "Unresolved defparam reference to "lcell_inst" in lcell_inst.lut_mask"

VHDL simulation of the ALTERA_PLL and ALTERA_PLL_RECONFIG IP cores generates the following error message: # ** Error: (vsim-10000) D:/build/13.1/58_acdsTO/acds/quartus/eda/sim_lib…
www.altera.com/support/kdb/solutions/fb158910.html - 2014-06-30

2014-06-24 130000 13.0 140000 14.0 ALTERA_MULT_ADD megafunction: missing variation file

The MegaWizard™ Plug-In Manager does not include a variation file when it generates an ALTERA_MULT_ADD megafunction.
www.altera.com/support/kdb/solutions/fb157527.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Does Not Document That Scrambling is Turned On By Default

By default, scrambling/descrambling is turned on in the RapidIO II IP core. That is, the default value of the Scrambling/descrambling enabled bit of the LP-Serial Lane n Status 4 …
www.altera.com/support/kdb/solutions/fb112829.html - 2014-06-30

2014-06-25 140000 14.0 0 Upgrading the Altera Soft Core JTAG I/O IP core generates a device family mismatch warning

Upgrading the Altera® Soft Core JTAG I/O IP core from the Quartus® II software release version 13.1 to version 14.0 or beyond generates a "device family mismatch" warning.…
www.altera.com/support/kdb/solutions/fb205717.html - 2014-06-30

2014-06-30 130104 13.1
Update4
0 What is the correct transceiver reference resistor (RREF) value for Arria 10 devices?

The correct transceiver reference resistor (RREF) value for Arria® 10 devices is 2.0 kOhm 1%. Due to a mistake in Arria 10 Pin Connection Guidelines document (PDF) this is incorre…
www.altera.com/support/kdb/solutions/rd06302014_323.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 40GbE MAC and PHY IP Core 40GBASE-KR4 Testbench Does Not Support Cadence NCSIM Simulator

The demonstration testbench for 40GBASE-KR4 variations of the 40- and 100-Gbps Ethernet MAC and PHY IP core cannot simulate successfully with the Cadence NCSIM simulator. The err…
www.altera.com/support/kdb/solutions/fb172581.html - 2014-06-30

2012-06-26 140000 14.0 0 pll_sharing Warning Message May Appear

This problem affects UniPHY-based DDR3, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. When you create a new external memory interface in the Quartus II software, you may see th…
www.altera.com/support/kdb/solutions/fb203048.html - 2014-06-30

2014-06-25 140000 14.0 0 Qsys device selection issues with the 14.0 Quartus II software release

The Qsys system integration tool has two issues with device selection: Qsys defaults to a “default” device when no device family is specified in the Quartus® II software relea…
www.altera.com/support/kdb/solutions/fb206352.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Does Not Explain sys_clk and Transceiver Reference Clock Constraints

The two RapidIO II IP core input clocks, sys_clk and tx_pll_refclk, must derive from a common clock source. If your design does not enforce this constraint, the IP core may experi…
www.altera.com/support/kdb/solutions/fb156613.html - 2014-06-30

2014-06-30 0 0 Why might an Arria V, Cyclone V or Stratix V device transceiver not work correctly when an fPLL is used as a Tx PLL as well as a general purpose PLL?

An Arria® V, Cyclone® V or Stratix® V device transceiver may not work correctly when an fPLL is used as a Tx PLL as well as a general purpose PLL if its VCO frequency is not correc…
www.altera.com/support/kdb/solutions/rd04032014_547.html - 2014-06-30

2014-06-25 140000 14.0 0 "Assign Base Addresses" causing memory overlap in Qsys

In Qsys, when you choose System > Assign Base Addresses, the software might assign overlapping base addresses and display an error message such as: slave0.s0(0x0..0xfff) overla…
www.altera.com/support/kdb/solutions/fb197718.html - 2014-06-30

2014-06-30 140000 14.0 0 100GbE IP Core Might Not Maintain Average Minimum Inter-Packet Gap of 12

If a 100GbE IP core variation has the following two register settings TX CRC insertion turned on (bit [0] of the CRC_CONFIG register at offset 0x123 is set) Enable TX preamble pa…
www.altera.com/support/kdb/solutions/fb203475.html - 2014-06-30

2014-06-30 130001 13.0 SP1 130100 13.1 Can a 9-transceiver channel Arria V GT device support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels?

No, a 9-transceiver channel Arria® V GT device cannot support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels. Due to a bug in the Quartus® II software v…
www.altera.com/support/kdb/solutions/rd06032014_339.html - 2014-06-30

2014-06-24 140000 14.0 0 Conduit BFM and Tri-State Conduit BFM simulations fail when using the mixed simulation language option

The Altera® Conduit bus functional model (BFM) and Tri-State Conduit BFM do not generate a VHDL simulation model when the mixed simulation language option is selected. Simulat…
www.altera.com/support/kdb/solutions/fb199253.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 CPRI IP Core Dynamic Clock Switching Does Not Work Correctly

CPRI IP core variations that target an Arria V, Cyclone V, or Stratix V device should support dynamic clock mode switching from master clocking mode to slave clocking mode, and fr…
www.altera.com/support/kdb/solutions/fb173086.html - 2014-06-30

2012-06-26 140000 14.0 0 Error When Simulating Stratix V MAC with XAUI PHY Design Example Using ModelSim-Altera Edition 10.1e

You will encounter the following fatal error message when attempting to simulate the Stratix V MAC with XAUI PHY design example using ModelSim-Altera version 10.1e: "# Fatal error…
www.altera.com/support/kdb/solutions/fb206391.html - 2014-06-30

2014-06-30 0 0 How do I decouple shared supply rails with very different noise, current, transient, and Feffective specifications?

Some Altera devices allow power supply rail sharing. For instance you may share the Stratix® V GX device VCC and VCCHSSI supplies which have very different specifications. The V…
www.altera.com/support/kdb/solutions/rd01092014_122.html - 2014-06-30

2014-07-07 140000 14.0 0 Nios II does not recognize the Qsys Address Span Extender windowed_slave interface as a reset vector location

In the Quartus® II software release version 14.0, if the Qsys system integration tool’s Address Span Extender slave control port is disabled, the Address Span Extender acts as…
www.altera.com/support/kdb/solutions/fb213947.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Does Not Explain How to Write to OUTSTANDING_ACKID Field of Port 0 Local AckId CSR

The RapidIO II MegaCore Function User Guide states that user software can write to the OUTSTANDING_ACKID field of the Port 0 Local AckID CSR (offset 0x148). However, this register…
www.altera.com/support/kdb/solutions/fb175405.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Erroneously Indicates link-response With port_status Value of Error Causes Fatal Error

The RapidIO II MegaCore Function User Guide states that when the IP core receives a link-response control symbol with port_status value of Error, the IP core output port error rec…
www.altera.com/support/kdb/solutions/fb171709.html - 2014-06-30

2014-07-04 130100 13.1 140000 14.0 13.1 Quartus II software compilations do not generate .mif

When upgrading the Quartus® II software to version 13.1 or beyond, or cleaning the database of your project, the software might not compile a revision that generates a .mif if…
www.altera.com/support/kdb/solutions/fb156420.html - 2014-06-30

2014-06-24 130000 13.0 130100 13.1 During GPIO characterization, 13.0 Quartus II software provides incorrect RT values for Cyclone V and Arria V devices

During general-purpose I/O (GPIO) characterization for the Cyclone® V and Arria® V devices, the default RTadjust[3:0] value in the Quartus® II software is 0000; this v…
www.altera.com/support/kdb/solutions/fb153487.html - 2014-06-30

2014-07-04 140000 14.0 140000 14.0 Incorrect simulations in ModelSim AE and SE versions 10.1d, 10.1e, and 10.2c

Mentor Graphics® ModelSim® Altera Edition (AE) version 10.1e does not correctly simulate always_comb and always_latch blocks when only some bits of the 2-D wires are read …
www.altera.com/support/kdb/solutions/fb204770.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Overstates Customer Testbench Transaction Types

According to the RapidIO II MegaCore Function User Guide, the customer testbench executes Type 9 (data streaming) transactions. However, this information is incorrect.
www.altera.com/support/kdb/solutions/fb142943.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Simulation Fails for Arria V GZ Hard IP for PCIe When Re-Generated Using MegaWizard Plug-In Manager

If you try to edit an existing Arria V GZ Hard IP for PCI Express variant using the version 13.1.1 of the MegaWizard Plug-In Manager, the model generation phase fails.
www.altera.com/support/kdb/solutions/fb171292_avgz.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 IP Compiler for PCI Express User Guide Indicates Continued Support of Devices and Flows No Longer Supported by the Quartus II Software

The IP Compiler for PCI Express User Guide indicates continued support for the following devices and development flows that are no longer supported in the Quartus II software: Arr…
www.altera.com/support/kdb/solutions/fb138018.html - 2014-06-30

2014-06-27 140000 14.0 0 Mozilla Firefox limitations for Quartus II Help

In the Quartus® II software release version 14.0, local installations of Quartus II Help do not work with Mozilla Firefox.
www.altera.com/support/kdb/solutions/fb213222.html - 2014-06-30

2014-05-12 130100 13.1 140000 14.0 Preamble Pass-through Mode Does Not Work with PFC Frames

Low Latency Ethernet 10G MAC designs with Enable preamble pass-through mode and Enable priority-based flow control (PFC) options turned on, will produce incorrect data or pause fr…
www.altera.com/support/kdb/solutions/fb166749.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II IP Core Might Send Packet With Wrong ackID After Recovery

After the RapidIO II IP core output port exits the RECOVER state, it might transmit a packet with the wrong ackID value.
www.altera.com/support/kdb/solutions/fb193877.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Simulation Fails for Arria V Hard IP for PCIe When Re-Generated Using MegaWizard Plug-In Manager

If you try to edit an existing Arria V Hard IP for PCI Express variant using the version 13.1 Update 1 of the MegaWizard Plug-In Manager, the model generation phase fails.
www.altera.com/support/kdb/solutions/fb171292_av.html - 2014-06-30

2014-07-03 140000 14.0 0 Simulation of ALTMEMPHY IP with Cyclone IV Devices Fails

This problem affects all ALTMEMPHY-based external memory interfaces targeting Cyclone IV devices. Simulation of an ALTMEMPHY-based external memory interface fails with the followi…
www.altera.com/support/kdb/solutions/fb210109.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 Some RapidIO II IP Core Capture Registers Do Not Update Correctly From User Logic

The Logical/Transport Layer Control Capture CSR (offset 0x31C) FTYPE and TTYPE fields and the Logical/Transport Layer Device ID Capture CSR (offset 0x318) fields should update wit…
www.altera.com/support/kdb/solutions/fb167952.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 Some RapidIO II IP Core Logical/Transport Layer Capture Registers Do Not Update for Some Maintenance Module Error Conditions

The RapidIO II IP core Logical/Transport Layer Device ID Capture CSR (offset 0x318) and Logical/Transport Layer Control Capture CSR (offset 0x31C) do not update correctly when the…
www.altera.com/support/kdb/solutions/fb174693.html - 2014-06-30

2014-06-24 140000 14.0 0 Tcl commands exec and auto_exeok do not work in the Quartus II software

In the Quartus® II software release version 14.0, the exec and auto_execok Tcl commands might not work if you include spaces in your Quartus II installation path.
www.altera.com/support/kdb/solutions/fb201817.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 40GbE MAC and PHY IP Core 40GBASE-KR4 Testbench Does Not Support Synopsys VCS Simulator

The demonstration testbench for 40GBASE-KR4 variations of the 40- and 100-Gbps Ethernet MAC and PHY IP core cannot simulate successfully with the Synopsys VCS simulator.
www.altera.com/support/kdb/solutions/fb172579.html - 2014-06-30

2014-06-27 140000 14.0 0 Browser limitations for Quartus II Help

In the Quartus® II software release version 14.0, some Quartus II Help features require you to disable pop-up blocking.
www.altera.com/support/kdb/solutions/fb213224.html - 2014-06-30

2014-06-30 90102 9.1 SP2 140000 14.0 CPRI IP Core RE Slaves Delay Update of cpri_tx_bfn Value

The value of the CPRI IP core cpri_tx_bfn output signal, which appears in bits [14:3] of the aux_tx_status_data output bus, should be the number of the current CPRI radio frame on…
www.altera.com/support/kdb/solutions/fb176470.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II IP Core Might Enter port_error State If RapidIO Lane is Noisy

When one or more RapidIO lanes are noisy, the RapidIO II IP core might enter the port_error state.
www.altera.com/support/kdb/solutions/fb193882.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II MegaCore Function User Guide Incorrectly Indicates User Can Turn Off Remote Transmit Emphasis Control

The RapidIO II MegaCore Function User Guide indicates that software can reset the REMOTE_TX_EMPH_ENABLE bit in the Port 0 Control 2 CSR (offset 0x154). However, this indication i…
www.altera.com/support/kdb/solutions/fb159838.html - 2014-06-30

2014-06-30 110000 11.0 140000 14.0 RapidIO User Guide Does Not Clarify That .sdc File Must Be Modified Manually in Case of Multiple RapidIO IP Core Instances

If you instantiate multiple RapidIO IP cores in your design, you must modify the Synopsys Design Constraints File (.sdc) to repeat the create_generated_clock statements for each I…
www.altera.com/support/kdb/solutions/fb180850.html - 2014-06-30

2014-06-25 140000 14.0 0 Some 14.0 Quartus II software release IP cores do not generate HDL files

If you install the Quartus® II software release version 14.0 in a directory with spaces in the file path, or if an IP core is generated into a directory with spaces in the fil…
www.altera.com/support/kdb/solutions/fb204093.html - 2014-06-30

2014-06-27 140000 14.0 0 The Symbol Editor context menu refers to the obsolete MegaWizard Plug-In Manager in the 14.0 Quartus II software release

The IP Catalog and parameter editor replace the MegaWizard™ Plug-In Manager in the Quartus® II software release version 14.0. However, the Symbol Editor context menu sti…
www.altera.com/support/kdb/solutions/fb209359.html - 2014-06-30

2014-05-12 140000 14.0 0 Unable to Successfully Trigger XON in Low Latency Ethernet 10G MAC

The Low Latency Ethernet 10G MAC MegaCore function cannot handle back-to-back triggering of XOFF/XON. This issue affects all versions that support Low Latency Ethernet 10G MAC.
www.altera.com/support/kdb/solutions/fb203311.html - 2014-06-30

2014-06-25 120100 12.1 130000 13.0 "PLL base data rate" errors in Arria V Transceiver Native PHY IP Core PLL megafunctions

In the 12.1 Quartus® II software release of the Arria® V Transceiver Native PHY IP Core, the megafunction generated design file displays a default phase-locked loop (PLL) …
www.altera.com/support/kdb/solutions/fb91618.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 RapidIO II IP Core Does Not Return ERROR Response Packet to MAINTENANCE Request with Illegal Size

When the RapidIO II IP core receives a MAINTENANCE request with an illegal size (rdsize not equal to 4’b1000 for a MAINTENANCE read request, or wrsize not equal to 4’b1000 for a M…
www.altera.com/support/kdb/solutions/fb167937.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Re-Generation Fails for Arria V Hard IP for PCIe Using MegaWizard Plug-In Manager

If you try to edit an existing Arria V Hard IP for PCI Express variant using the version 13.1.1 of the MegaWizard Plug-In Manager, the MegaWizard does not recognize the variant fi…
www.altera.com/support/kdb/solutions/fb179149_av.html - 2014-06-30

2014-06-30 130101 13.1
Update1
130102 13.1
Update2
Simulation Fails for Stratix V Hard IP for PCIe When Re-Generated Using MegaWizard Plug-In Manager

If you try to edit an existing Stratix V Hard IP for PCI Express variant using the version 13.1 Update 1 of the MegaWizard Plug-In Manager, the model generation phase fails.
www.altera.com/support/kdb/solutions/fb171292.html - 2014-06-30

2014-06-30 130100 13.1 140000 14.0 CPRI IP Core Demonstration Testbench Does Not Support Cadence NCSIM Simulator

The CPRI IP core demonstration testbench cannot simulate successfully with the Cadence NCSIM simulator.
www.altera.com/support/kdb/solutions/fb157550.html - 2014-06-30

2014-06-24 140000 14.0 0 fiftyfivenm_atoms_ncrypt.v cannot compile in Aldec Riviera-PRO

The Quartus® II software simulation model file fiftyfivenm_atoms_ncrypt.v cannot be compiled by Aldec® Riviera-PRO™ version 2013.10. This issue affects the Quartus&r…
www.altera.com/support/kdb/solutions/fb201816.html - 2014-06-30

2014-07-01 140000 14.0 0 JESD204B IP Core ed_synth Timing Failure (Arria V)

The JESD204B IP core design example has a hold time violation to the transceiver. This issue affects all versions that support the JESD204B IP core.
www.altera.com/support/kdb/solutions/fb201029.html - 2014-06-30

2014-06-30 90102 9.1 SP2 140000 14.0 Occasional CPRI IP Core May Stop Transmitting on the CPRI Link

In rare cases, the CPRI IP core may stop transmitting radio frames on the CPRI link due to deadlock in internal pointer re-synchronization. This issue does not manifest in simulat…
www.altera.com/support/kdb/solutions/fb176422.html - 2014-06-30

2014-06-30 120100 12.1 140000 14.0 RapidIO II IP Core Hangs After Receiving MAINTENANCE Read Response With DONE Status but No Payload

When the RapidIO II IP core receives a MAINTENANCE read response with DONE status but without a payload, the IP core should indicate an error. However, the IP core hangs. Refer al…
www.altera.com/support/kdb/solutions/fb167939.html - 2014-06-30

2014-06-25 0 0 ERROR: CB detected a CRC error between words 0 and 25000

If a .sof image is first loaded into the FPGA (using sof2flash or JTAG) when compression and CvP Update are enabled, the above error will be seen when…
www.altera.com/support/kdb/solutions/rd05192014_717.html - 2014-06-25

2014-06-25 0 0 What is the status of the General Purpose I/O pins during Configuration via Protocol(CvP) Init or CvP Update?

When performing CvP Init, once the periphery file is loaded, only the Hard IP for PCI Express is released from reset.  All other GPIOs are released after the core is loaded. C…
www.altera.com/support/kdb/solutions/rd06182014_53.html - 2014-06-25

2014-06-25 130000 13.0 0 Do I need to setup the Avalon-MM-to-PCI Express address translation tables when using 64-bit addressing for the Avalon-Memory Mapped Hard IP for PCI Express?

The Avalon-Memory Mapped Hard IP for PCI Express® supports 64-bit addressing. If you select 64-bit addressing, no address translation is necessary.As a consequence, the 'Avalon to …
www.altera.com/support/kdb/solutions/rd06162014_152.html - 2014-06-25

2015-01-21 130000 13.0 0 Why does 64-bit Addressing in the Avalon-Memory Mapped (Avalon MM) Hard IP for PCI Express not function properly for Cyclone V & Arria V?

Due to a problem in the RTL, the 64-bit addressing in the Hard IP for PCI Express® for Cyclone® V and Arria® V requires the following code changes.
www.altera.com/support/kdb/solutions/rd05272014_431.html - 2014-06-25

2014-06-24 130000 13.0 0 Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode

You may see the following error when you simulate the UniPHY based DDR3 controller in full calibration mode.# ** Fatal: Read data comes back but dynamic OCT ctr…
www.altera.com/support/kdb/solutions/rd01072014_650.html - 2014-06-24

2014-10-15 0 0 Why can't I connect to my EthernetBlaster II cable?

Following an upgrade to the firmware package, EBII_FW_14_136.tar.gz, for the EthernetBlaster II cable, you may find that you are unable to connect to the cable from Quartus® II pro…
www.altera.com/support/kdb/solutions/rd06242014_123.html - 2014-06-24

2014-06-23 0 0 Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_split_bits_utility.cpp, Line: 621
Bad mask!

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a Cyclone® IV or Cyclone V design using the Functional Safety Separatio…
www.altera.com/support/kdb/solutions/rd06232014_507.html - 2014-06-23

2014-06-23 130103 13.1
Update3
0 Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus II v13.1 with a preliminary timing model and constraints..

Due to a problem in the Quartus® II software version 13.1 Update 3, you may see the the following critical warning when compiling your Cyclone® V SOC HPS design…
www.altera.com/support/kdb/solutions/rd03102014_457.html - 2014-06-23

2014-07-02 120100 12.1 0 Error (10779): VHDL error at < filename.vhd >: expression is not constant.

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error message if you use a variable as an index for signal. For example : data(a dow…
www.altera.com/support/kdb/solutions/rd12122013_218.html - 2014-06-23

2014-06-20 0 0 Error: Can't place multiple pins assigned to pin location <pin>

You may observe this error message if you have a signal in your design that has been assigned to a Dual-Purpose pin, but you have not changed the appropriate Dual Pu…
www.altera.com/support/kdb/solutions/rd06052014_214.html - 2014-06-20

2014-06-19 130000 13.0 130100 13.1 Error (14024): Parameter "mem_if_tcwl" of instance "hmc_inst" has illegal value "TCWL_1" assigned to it. Possible parameter values are: "TCWL_8", "TCWL_7", "TCWL_6", "TCWL_5", "TCWL_4", "TCWL_3", "TCWL_2", "TCWL_0".

In the Quartus® II software version 13.0, you may receive this error message when compiling a design which contains the LPDDR2 UniPHY based IP.  This error occu…
www.altera.com/support/kdb/solutions/rd05132014_457.html - 2014-06-19

2014-06-18 0 0 Why does my Cyclone V Hard IP for PCI Express simulation get stuck at the L0 state when using Aldec Riviera-PRO or Aldec ActiveHDL?

The Cyclone® V Hard IP for PCI Express® simulation can get stuck in the L0 state because the encrypted simulation models are attempting to use a Quartus® II define statement t…
www.altera.com/support/kdb/solutions/rd04032014_424.html - 2014-06-18

2014-06-17 0 0 Are there any concern on DDR timing using Altera EMIF (External Memory Interface) IP if my design fails DCD (Duty Cycle Distortion) compliance testing?

If your design fails DCD compliance testing, system functionality still can be guaranteed over PVT (Process, Voltage and Temperature) if the following are true:…
www.altera.com/support/kdb/solutions/rd06092014_482.html - 2014-06-17

2014-06-16 0 0 Why isn't the chainout adder used by my inferred DSP?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see an adder implemented in registers rather than being absorbed into a DSP block. This occ…
www.altera.com/support/kdb/solutions/rd06162014_821.html - 2014-06-16

2014-06-29 0 0 Why does my Avalon Memory Mapped bus hang when accessing the transceiver reconfiguration controller in Arria V, Cyclone V and Stratix V devices?

Avalon® Memory Mapped accesses to the transceiver reconfiguration controller in the Arria® V, Cyclone® V, and Stratix® V, devices will hang if the accesses are made …
www.altera.com/support/kdb/solutions/rd04032014_314.html - 2014-06-16

2014-06-16 0 0 Why is Quartus II programmer checksum different than general checksum calculations of the .pof or .jic?

The Quartus® II programmer calculates the checksum using only the data which will be programmed to the configuration device. The programmer object file (.pof) or JTAG Ind…
www.altera.com/support/kdb/solutions/rd03312014_745.html - 2014-06-16

2014-06-13 130100 13.1 0 Why do I observe read errors with my UniPHY based memory controller IP after migrating the IP to a different version of the Quartus II software?

You must run the pin_assignment.tcl script after migrating the UniPHY based memory controller IP to a different version of the Quartus® II softwa…
www.altera.com/support/kdb/solutions/rd06032014_877.html - 2014-06-13

2014-06-11 0 0 How do I map the Quartus® II and IBIS-AMI model slew rate settings for Stratix® V GX and Arria® V GZ devices?

You can use the table below to map the Quartus® II and IBIS-AMI model slew rate settings for Stratix® V GX and Arria® V GZ devices. Quartus II Setting IBIS-AMI Settin…
www.altera.com/support/kdb/solutions/rd06092014_656.html - 2014-06-11

2014-06-11 0 0 What transceiver slew rate settings are allowed in the Quartus II software for Stratix V GX and Arria V GZ devices?

The following transceiver slew rate settings are allowed in the Quartus® II software for Stratix® V GX and Arria® V GZ devices. Protocol/Datarate Allowed Quartus II Settin…
www.altera.com/support/kdb/solutions/rd06092014_294.html - 2014-06-11

2014-06-10 0 0 Why doesn’t the TimeQuest Timing Analyzer remove all common clock path pessimism on my source synchronous output path?

The TimeQuest Timing Analyzer may not remove all common clock path pessimism (CCPP) in some cases, even when you turn on Enable common clock path pessimism removal. The TimeQuest T…
www.altera.com/support/kdb/solutions/rd05302014_545.html - 2014-06-10

2014-06-09 130100 13.1 0 Warning (332056): PLL cross checking found inconsistent PLL clock settings

You may encounter the above warning when compiling the XAUI PHY IP using Quartus® II software version 13.1 for Arria® V, Cyclone® V, and Stratix® V transceiver devices. This i…
www.altera.com/support/kdb/solutions/rd12262013_390.html - 2014-06-09

2014-06-06 130200 13.1
Arria 10
Edition
0 How does the Arria 10 device know if the configuration mode is Fast Passive Parallel (FPP) or Passive Serial (PS) when the MSEL pin setting is the same for both modes?

In Arria® 10 devices the MSEL pins encode whether the device is operating in a Passive configuration mode (FPP/PS) or an Active mode (Active Serial (AS)). There is no separat…
www.altera.com/support/kdb/solutions/rd06052014_67.html - 2014-06-06

2014-06-06 0 0 How can I use command line (quartus_pgm) to program a CFI flash device via the Parallel Flash Loader (PFL) megafunction in a MAX II or MAX V CPLD?

To use the command line interface to program a CFI flash device via the Parallel Flash Loader (PFL) megafunction in a MAX® II or MAX® V device, follow the …
www.altera.com/support/kdb/solutions/rd05122014_736.html - 2014-06-06

2014-06-06 0 0 Is the internal configuration oscillator in Cyclone III or Cyclone IV devices turned off once the device enters user mode?

By default, the configuration oscillator in Cyclone III or Cyclone IV devices is disabled once configuration and initialization is complete and the device has entered use…
www.altera.com/support/kdb/solutions/rd03302007_390.html - 2014-06-06

2014-06-05 130000 13.0 0 Is DDR2 SDRAM with HPS Hard Controller supported in Arria V SoC Devices?

No, Arria V SoC Devices do not support DDR2 SDRAM with an HPS Hard Memory Controller. The External Memory Interface Spec Estimator Tool incorrectly states that the Arria …
www.altera.com/support/kdb/solutions/rd08272013_227.html - 2014-06-05

2014-06-05 110001 11.0 SP1 110100 11.1 Warning (10230): Verilog HDL assignment warning at *instance_name*_write_datapath.v(118): truncated value with size to match size of target (1)

You may experience the above warning when compiling the DDR2 or DDR3 SDRAM Controller with UniPHY IP in Quartus II.  This warning occurs as Quartus II synthesized away so…
www.altera.com/support/kdb/solutions/rd03252014_634.html - 2014-06-05

2014-06-02 130000 13.0 0 Internal Error: Sub-system: SSC, File: /quartus/tsm/ssc/ssc_timing.cpp, Line: 93

Due to a problem in the Quartus® II software version 13.0 and later, you may see this error during synthesis if the design does not having any timing paths and Timing-Driven S…
www.altera.com/support/kdb/solutions/rd05282014_443.html - 2014-06-02

2014-06-02 120000 12.0 0 Internal Error: Sub-system: SIN, File: /quartus/tsm/sin/sin_micro_tnodes_dag.cpp, Line: 626

This error may be seen in the Quartus® II software version(s) 12.0sp2 and earlier when running the EDA Netlist Writer to create IBIS Models for designs targeting the Arria® V famil…
www.altera.com/support/kdb/solutions/rd12072012_144.html - 2014-06-02

2014-05-30 0 0 Is there a maximum configuration time specification for Passive Serial (PS) or Fast Passive Parallel (FPP) configuration modes?

There is no maximum configuration time specification for Passive Serial (PS) or Fast Passive Parallel (FPP) configuration modes.  Hence it is possible to pause DCLK durin…
www.altera.com/support/kdb/solutions/rd05292014_860.html - 2014-05-30

2014-06-01 0 0 Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

You may see this warning in the Quartus® II design software fitter report if a PLL which has the reconfiguration option enabled does not have a compensated clock specified.
www.altera.com/support/kdb/solutions/rd05232014_921.html - 2014-05-30

2014-05-29 130000 13.0 0 Why does Configuration via Protocol (CvP) fail to initiate core image update at PCIe Gen1 x1 in Cyclon V or Arria V?

Due to a problem in the Quartus® II software version 13.1 update 4 and earlier, the CvP may fail to initiate core image update showing time out error at PCI Express® Gen …
www.altera.com/support/kdb/solutions/rd05142014_39.html - 2014-05-29

2014-05-27 0 0 How to change the reset controller from hard reset to soft reset?

The HIP will use hard reset controller by default. Please use keyword "hip_hard_reset_hwtcl" in the PCIe core top level file, and then replace this parameter to '0'. This will chan…
www.altera.com/support/kdb/solutions/rd08302012_466.html - 2014-05-27

2014-05-27 0 0 Error (170084): Can't route signal "~GND" to atom "< dqs_oct_alignment~_Duplicate>"

The above error may appear when you use the Stratix® V ALTDQ_DQS2 Megafunction in the Quartus® II software version 13.1. The error is caused during the fitter stage…
www.altera.com/support/kdb/solutions/rd05062014_472.html - 2014-05-27

2014-05-27 0 0 Stratix V Device Handbook: Known Issues

Issue 187612: Chapter 7.External Memory Interfaces in Stratix V Devices (.PDF) (ver 2014.01.10, Jan 2014, 532 KB) Table 7-2 shows External Memory Interface Performance in Str…
www.altera.com/support/kdb/solutions/rd04232014_345.html - 2014-05-27

2014-05-27 0 0 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

You may see the critical warning above during the fitter stage when compiling the UniPHY-based memory controller IP. You may safely ignore this critical warning message.
www.altera.com/support/kdb/solutions/rd01282014_301.html - 2014-05-27

2014-08-03 0 0 Do additional power-up transient currents need to be added to the Early Power Estimator (EPE) or Power Play Power Analyzer (PPPA) reports for Stratix V devices?

No.  The transient currents at power-up are already included in the minimum current requirements in the EPE and PPPA tools for Stratix® V devices.  When th…
www.altera.com/support/kdb/solutions/rd03252014_294.html - 2014-05-23

2014-05-23 0 0 Why does execution of the KEY_VERIFY JTAG instruction return 0x0 (hex) after the tamper protection bit has been programmed in Stratix V, Arria V or Cyclone V devices?

The JTAG instruction, KEY_VERIFY is one of many non-mandatory JTAG instructions that are disabled when the tamper protection bit is enabled in&nb…
www.altera.com/support/kdb/solutions/rd04112014_482.html - 2014-05-23

2014-05-23 0 0 Can I place input differential clock or data pins in an I/O bank not powered by 2.5V VCCIO?

In Stratix® V, Arria® V, and Cyclone® V devices, the differential input buffer is powered by VCCPD which must be 2.5-V to support differential
www.altera.com/support/kdb/solutions/rd06252012_306.html - 2014-05-23

2014-05-19 110100 11.1 0 Why does the PowerPlay Early Power Estimator (EPE) show incorrect number of Hard Memory Controller (HMC) when the EPE imports the PowerPlay Early Power Estimator (.csv) file?

Due to a problem in the Quartus® II software version 11.1 and later, the EPE may show an incorrect number of HMCs when the EPE imports the .csv file. The Quart…
www.altera.com/support/kdb/solutions/rd03182014_858.html - 2014-05-19

2014-05-19 0 0 Can I use Hard Processor System (HPS) I/Os for the Logic Analyzer Interface?

The Logic Analyzer Interface does not support HPS I/Os. 
www.altera.com/support/kdb/solutions/rd05012014_686.html - 2014-05-19

2014-05-19 130100 13.1 0 Why is it not possible to drive out on pins that are reserved as bi-directional when performing post-configuration mode boundary scan testing on Arria V or Cyclone V devices?

Due to a problem in the Quartus® II software version 13.1, the output buffers of pins that are reserved as bidirectional are disabled in Arria® V or Cyclone® V …
www.altera.com/support/kdb/solutions/rd04282014_840.html - 2014-05-19

2014-05-16 0 0 Can the VCCLSENSE and GNDSENSE pins be left unconnected if not used on Arria 10 devices?

Yes, if the VCCLSENSE and GNDSENSE pins are not used on Arria® 10 devices, you can leave them unconnected.
www.altera.com/support/kdb/solutions/rd03312014_367.html - 2014-05-16

2014-05-15 110000 11.0 110100 11.1 RapidIO IP Core Might Lose TX Buffers During Resynchronization of ackID Value

If you resynchronize the ackID value for your RapidIO IP core instance, the IP core should reset the expected ackID value in the Port 0 Local AckID CSR at offset 0x148. The change…
www.altera.com/support/kdb/solutions/fb202053.html - 2014-05-16

2014-05-16 0 0 Why does the Early Power Estimator tool (EPE) report higher power than PowerPlay Power Analyzer (PPPA), when using ALTUFM_OSC in MAX II and MAX V devices?

When using the ALTUFM_OSC megafunction in MAX® II or MAX V devices, the EPE and Quartus® II PPPA power results may vary significantly, if the oscena port is hardcode…
www.altera.com/support/kdb/solutions/rd05082014_372.html - 2014-05-16

2014-05-16 0 0 Does varying the Junction Temperature (Tj) or Ambient Temperature (Ta) settings in the Quartus II software affect the overall power results in PowerPlay Power Analyzer (PPPA), for MAX II Industrial and Extended Temperature grade devices?

Varying Tj or Ta in the Operating Temperature conditions in the Quartus® II design software will not affect the overall power reported by PPPA when targeting Industrial a…
www.altera.com/support/kdb/solutions/rd05082014_157.html - 2014-05-16

2014-07-10 0 0 Can the CLKUSR pin be used as both a configuration pin and then a user I/O pin after the device enters user mode?

If you have enabled the CLKUSR pin function in your Quartus® II project, it cannot be used as user I/O once configuration is complete and the device has entered user…
www.altera.com/support/kdb/solutions/rd05152014_443.html - 2014-05-16

2014-05-16 0 0 Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI?

Altera® does not provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI. You can refer to the Input Signal Edge Rate Guidance (PDF) …
www.altera.com/support/kdb/solutions/rd03192014_573.html - 2014-05-16

2014-05-16 130100 13.1 0 Is there a known issue with the scandata port when using the ALTPLL_RECONFIG megafunction in the Quartus® II software version 13.1?

The scandata output port in the ALTPLL_RECONFIG megafunction has been inverted in the Quartus® II software version 13.1.
www.altera.com/support/kdb/solutions/rd05052014_157.html - 2014-05-16

2014-05-15 120100 12.1 0 RapidIO II IP Core Capture Registers Might Capture Wrong Information for Out-of-Order Maintenance Response Packet With Error

When the RapidIO II IP core Maintenance module receives a response packet with ERROR status, it captures information about the errored packet in the Error Management Extension Log…
www.altera.com/support/kdb/solutions/fb185168.html - 2014-05-16

2014-12-04 130001 13.0 SP1 0 How do I generate Configuration via Protocol (CvP) programming files for a Arria V or Cyclone V designs?

To generate CvP programming files for Arria® V or Cyclone® V CvP designs with Quartus® II software version 13.1 and earlier, follow the workaround/fix steps below: &…
www.altera.com/support/kdb/solutions/rd10162013_225.html - 2014-05-16

2014-05-15 130001 13.0 SP1 0 In Heavy Traffic, RapidIO IP Core Might Not Respond to Some NWRITE_R Packets

The RapidIO IP core might not transmit some NWRITE_R Response packets, when it is operating in heavy traffic, due to FIFO overflow.
www.altera.com/support/kdb/solutions/fb184807.html - 2014-05-16

2014-05-16 0 0 What type of memory technology is used in Altera Quad-Serial (EPCQ) configuration devices?

Altera® EPCQ devices employ NOR flash memory technology.
www.altera.com/support/kdb/solutions/rd01282014_625.html - 2014-05-16

2014-05-19 130100 13.1 0 How can I address known issues with the ALTASMI_PARALLEL megafunction in the Quartus II software version 13.1?

There are known issues with the read_status port and Read Device Dummy Clock function in the ALTASMI_PARALLEL megafunction, in the Quartus® II software version …
www.altera.com/support/kdb/solutions/rd05132014_481.html - 2014-05-16

2014-05-15 130001 13.0 SP1 0 RapidIO IP Core Does Not Support ILL_TRAN_TARGET Field of Logical/Transport Layer Error Detect CSR

The RapidIO IP core does not update the ILL_TRAN_TARGET field of the Logical/Transport Layer Error Detect CSR at offset 0x10800.
www.altera.com/support/kdb/solutions/fb137266.html - 2014-05-16

2014-05-15 120000 12.0 0 Some RapidIO IP Core Variations Do Not Assert mnt_s_readerror Correctly

The RapidIO IP core Maintenance module should assert the mnt_s_readerror output signal in response to a Read response packet with status ERROR. However, 2x and 4x IP core variatio…
www.altera.com/support/kdb/solutions/fb187952.html - 2014-05-16

2014-05-15 120101 12.1 SP1 0 Why is ODT asserted for more than one rank in my DDR3 UniPHY controller?

If you have a multi-rank DDR3 UniPHY controller generated in the Quartus® II software version 12.1SP1 or later, you may see the ODT signals for multiple ranks assert at the sa…
www.altera.com/support/kdb/solutions/rd04142014_400.html - 2014-05-15

2014-05-15 0 0 Do the UniPHY-based memory controllers support Short ZQ Calibration?

No, the UniPHY-based memory controllers do not support Short ZQ Calibration. The UniPHY-based controllers use DQS Tracking to adjust for small voltage and temperature variations. R…
www.altera.com/support/kdb/solutions/rd03032014_876.html - 2014-05-15

2014-05-15 0 0 Error: nofile(37): in protected region

You may experience the above error while simulating a VHDL-based DDR3 UniPHY memory controller design with ModelSim. When the DDR3 memory controller is generated in VHDL, all …
www.altera.com/support/kdb/solutions/rd12162013_881.html - 2014-05-15

2014-05-15 0 0 How do I specify different timing constraints for TimeQuest, Fitter, or Analysis & Synthesis?

To identify which executable is currently running you can use the $::TimeQuestInfo(nameofexecutable) command from within a Synopsys Design Constraints (.sdc) file. This method can …
www.altera.com/support/kdb/solutions/rd06062011_944.html - 2014-05-15

2014-05-15 130100 13.1 0 Error: The specified Memory clock frequency exceeds the Memory device speed grade of 533.333 MHz. Please increase the Memory device speed grade (in Memory Parameters tab) or decrease the Memory clock frequency.

You may see the above error when generating a Stratix IV DDR3 UniPHY controller in the Quartus® II software version 13.1 or later. There is a new frequency check in the MegaWizard™…
www.altera.com/support/kdb/solutions/rd03252014_367.html - 2014-05-15

2014-05-15 120100 12.1 0 Why do I see R105 warnings on the DDR3 reset paths when using the Design Assistant tool?

The Design Assistant tool will generate R105 warnings if it detects a reset signal that is generated in one clock domain and used in another clock domain. This warns the user …
www.altera.com/support/kdb/solutions/rd05012014_39.html - 2014-05-15

2014-07-04 130100 13.1 0 Which ARM SoC addresses report the status of the physical FPGA-to-HPS Interrupts (f2h_irq0 and f2h_irq1 signals)?

In the Altera SoC Hard Processor System (HPS), the raw status of the physical f2h_irq0 and f2h_irq1 interrupt signals can be read directly from the ARM® Generic Interrupt Controlle…
www.altera.com/support/kdb/solutions/rd04282014_511.html - 2014-05-15

2014-05-14 120101 12.1 SP1 0 Why does my altpcie_demo application display as "PCI Device" under "Other Devices" in the Windows Device Manager for the PCI Express Avalon-ST High-Performance Reference Design?

Due to a problem with the provided driver information file(.inf), the reference design Device ID does not match that expected by the driver and Message Signal Interrupts (MSIs…
www.altera.com/support/kdb/solutions/rd05082014_916.html - 2014-05-14

2014-05-14 0 0 How can I dynamically change the Stratix V Hard IP for PCIe configuration registers' content?

The Stratix® V Hard IP for PCI Express® configuration registers' content can be dynamically modified through the Hard IP Avalon® Memory-Mapped (Avalon-MM) reconfiguration inte…
www.altera.com/support/kdb/solutions/rd05072014_141.html - 2014-05-14

2014-05-14 110100 11.1 0 Why does the PCI Express Hard IP core not transistion through all the required hot reset LTSSM states in simulation?

Due to a problem in the soft reset controller, when hot reset is applied, the LTSSM does not go through every state expected when initiating hot resets.
www.altera.com/support/kdb/solutions/rd01072014_718.html - 2014-05-14

2014-10-10 0 0 How should I connect coreclkout_hip to pld_clk on Stratix V?

In the Stratix® IV Hard IP for PCI Express®, some configurations allowed the pld_clk to be driven from a PLL that was, in turn, derived from coreclkout_hip.  Th…
www.altera.com/support/kdb/solutions/rd05062014_528.html - 2014-05-14

2014-05-14 120100 12.1 0 RapidIO II IP Core Capture Registers Might Capture Wrong Information for Out-of-Order Non-Maintenance Response Packet With Error

When the RapidIO II IP core I/O slave module receives a response packet with ERROR status, it captures information about the errored packet in the Error Management Extension Logic…
www.altera.com/support/kdb/solutions/fb187964.html - 2014-05-14

2014-08-03 0 0 Error: dma_0_control_port_slave_translator.avalon_anti_slave_0: master without waitrequest must match parameters and ports of slave dma_0_control_port_slave_translator_avalon_anti_slave_0_agent.av

You will see this error when generating a 64-bit address Avalon® Memory-Mapped Hard IP for PCI Express® design with the Scatter Gather DMA (SGDMA) function.The error…
www.altera.com/support/kdb/solutions/rd04302014_603.html - 2014-05-14

2014-05-14 0 0 Why does the Stratix V Advanced Systems Development Kit fail to link up to L0?

Due to an error in the schematic, provided .pin and Quartus® II Settings File(.qsf) files, the PCI Express® reference clock is not assigned to the correct pins. This error&nbs…
www.altera.com/support/kdb/solutions/rd05012014_582.html - 2014-05-14

2014-06-23 0 0 How do I ensure cold-start operation for Enpirion EN53xxxx and EP53xxxx series devices?

You can ensure cold-start operation for Enpirion® EN53xxxx and EP53xxxx series devices by adding a delay on the ENABLE pin. This can be done by adding a 10-kR resistor between…
www.altera.com/support/kdb/solutions/rd04022014_824.html - 2014-05-14

2014-05-20 120101 12.1 SP1 0 Why do MSI's not work on my altpcie_demo application for the PCI Express Avalon-ST High-Performance Reference Design?

Due to a problem with the provided driver information file(.inf), the reference design Device ID does not match that expected by the driver and Message Signal Interrupts (MSIs…
www.altera.com/support/kdb/solutions/rd12102013_51.html - 2014-05-14

2014-05-12 130100 13.1 130102 13.1
Update2
RapidIO II IP Core Might Declare Loss of Scrambler Synchronization If Link Partner Has Different Reference Clock Source

If the RapidIO II IP core and its RapidIO link partner have independent reference clock sources, the RapidIO II IP core declares a scrambler synchronization error by setting bit […
www.altera.com/support/kdb/solutions/fb183580.html - 2014-05-13

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Set RESPONSE_VALID in Port 0 Link Maintenance Response CSR After Transmitting link-request reset-device Control Symbol

After the RapidIO II IP core sends a link-request reset-device control symbol on the RapidIO link, it should set the RESPONSE_VALID bit in the Port 0 Link Maintenance Response CSR…
www.altera.com/support/kdb/solutions/fb184795.html - 2014-05-13

2014-05-12 120100 12.1 130100 13.1 RapidIO II IP Core Might Send Truncated Data on Avalon-ST Pass-Through Interface if tt = 0

When a RapidIO II IP core sends data to the Avalon-ST Pass-Through interface in a transaction with Transport Type value 0, it truncates the payload to a multiple of eight bytes.
www.altera.com/support/kdb/solutions/fb193858a.html - 2014-05-13

2014-05-12 120100 12.1 0 RapidIO II IP Core Might Send Truncated Data on Avalon-ST Pass-Through Interface if tt = 1

When the RapidIO II IP core sends data to the Avalon-ST Pass-Through interface in a transaction with Transport Type value 1, it truncates the payload to a multiple of eight bytes.…
www.altera.com/support/kdb/solutions/fb193858b.html - 2014-05-13

2014-05-12 120100 12.1 0 RapidIO II IP Core Transmits Unintended link-request Control Symbols

Writing the value 3’b100 to the COMMAND field of the RapidIO II IP core Port 0 Link Maintenance Request CSR at offset 0x140 should cause the RapidIO II IP core to transmit a singl…
www.altera.com/support/kdb/solutions/fb183974.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Transmits link-response Control Symbols With Incorrect port_status Value

When the RapidIO II IP core transmits a link-response control symbol, it does not provide a correct value in the port_status field.
www.altera.com/support/kdb/solutions/fb184732.html - 2014-05-12

2014-05-12 120100 12.1 130100 13.1 RapidIO II IP Core Does Not Transmit NREAD Responses With Payload Size Less Than 16 Bytes

According to the RapidIO Protocol Specifications, Revision 2.2, the mimimum size of Read payload on the RapidIO link is eight bytes. However, the RapidIO II IP core does not trans…
www.altera.com/support/kdb/solutions/fb193869.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Support Write Transactions With Payload Size Below Maximum

The RapidIO II IP core should be able to handle NWRITE and NWRITE_R requests on the RapidIO link for all legal combinations described in Table 4-4 in Part 1: Input/Output Logical …
www.altera.com/support/kdb/solutions/fb187932.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Incorrectly Sets Illegal Transaction Decode Flag Instead of Unsupported Transaction Flag

In response to an incoming RapidIO read transaction with rdsize greater than 4’b1011 and address[0] set to 1, the RapidIO II IP core should set the Unsupported Transaction (UNSUPP…
www.altera.com/support/kdb/solutions/fb187928.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Drop Packets When STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE and DROP_PKT_ENABLE Bits Are Set

When the RapidIO II IP core Port 0 Control CSR (offset 0x15C) STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE and DROP_PKT_ENABLE fields are set, the port should discard all output packets unti…
www.altera.com/support/kdb/solutions/fb184792.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Support Streaming Data Packets with Device ID Width 16

The RapidIO II IP core does not support streaming data packets (packets with ftype value of 9) in variations with a 16-bit device width (packet tt value of 1).
www.altera.com/support/kdb/solutions/fb184789.html - 2014-05-12

2014-05-13 120100 12.1 0 Why is the VCCIO current estimation lower than expected for the Hard Memory Controller?

You may see lower than expected maximum VCCIO current in the PowerPlay Power Analyzer report for the banks which contain address/command pins which are controlled by a hard me…
www.altera.com/support/kdb/solutions/rd02032014_570.html - 2014-05-12

2014-05-12 130100 13.1 130103 13.1
Update3
RapidIO II IP Core Detects Corrupted Control Symbol If Link Partner Has Different Reference Clock Frequency

If the RapidIO II IP core and its RapidIO link partner have different reference clock frequencies, the RapidIO II IP core might detect a corrupted control symbol or a control symb…
www.altera.com/support/kdb/solutions/fb183585.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Declare Illegal Transaction Decode in Response to Malformed NWRITE_R Response Packet

When the RapidIO II IP core receives a malformed NWRITE_R response packet on the RapidIO link, it should declare an Illegal Transaction Decode by setting the ILL_TRAN_DECODE bit i…
www.altera.com/support/kdb/solutions/fb187948.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Responds Incorrectly to Received stomp Control Symbol

According to Part 6 of the RapidIO Protocol Specifications, Revision 2.2, when the RapidIO II IP core receives a stomp control symbol, it should enter the Input Retry Stopped stat…
www.altera.com/support/kdb/solutions/fb184787.html - 2014-05-12

2014-05-09 120000 12.0 0 40-100GbE IP Core User Guide Erroneously Indicates Pause Signals Are Unavailable in Variations Without Adapters

The 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide states that the 40-100GbE IP core pause control and generation signals are unavailable in IP core variations…
www.altera.com/support/kdb/solutions/fb204361.html - 2014-05-10

2014-05-09 130000 13.0 0 40-100GbE IP Core User Guide Describes IPG_DEL_PERIOD Register Incorrectly

The 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide describes the 40-100GbE IP core IPG_DEL_PERIOD register at offset 0x126 incorrectly. The user guide states …
www.altera.com/support/kdb/solutions/fb199633.html - 2014-05-10

2014-05-08 0 0 Which On-Chip Termination (OCT) setting is supported by the HiSPI I/O standard in Cyclone V devices?

HiSPi inputs in Cyclone® V devices support the "Differential" OCT assignment, similar to LVDS inputs.
www.altera.com/support/kdb/solutions/rd05062014_851.html - 2014-05-08

2014-05-13 130100 13.1 0 Why does the read_status port on the ALTASMI_PARALLEL megafunction not return the correct status?

Due to a problem in the Quartus® II software version 13.1, the read_status port of the ALTASMI_PARALLEL megafunction does not return the correct status on the dataout port.
www.altera.com/support/kdb/solutions/rd05062014_83.html - 2014-05-08

2014-05-07 130100 13.1 0 Simulation With Riviera-PRO May Fail to Initialize Under Certain Conditions

This problem affects all external memory interface products. If your design uses a VHDL simulation model with an Altera External Memory bus functional model (.BFM), simulation wit…
www.altera.com/support/kdb/solutions/fb187580.html - 2014-05-07

2014-05-07 120100 12.1 0 All Devices in Multirank Designs Must Enter and Exit Self-Refresh at the Same Time

This problem affects all external memory interface products. In multirank designs, you must ensure that all memory devices enter self-refresh at the same time, and exit self-refre…
www.altera.com/support/kdb/solutions/fb72361.html - 2014-05-07

2014-05-07 130100 13.1 0 Why does the Arria V GZ and Stratix V device Transceiver PLL Megawizard show a "Dynamic reconfiguration of ATX PLLs is not supported in the current release" message when you hover your cursor over the "Enable PLL reconfiguration" option in Quartus® II software version 13.1?

Due to a problem in the Quartus II software version 13.1 MegaWizard Plugin Manager, the Arria® V GZ and Stratix® V Transceiver PLL Megawizard™ shows a "Dynamic reconfiguration of A…
www.altera.com/support/kdb/solutions/rd01132014_769.html - 2014-05-07

2014-05-07 130100 13.1 0 Why does the Arria V GX and Cyclone V GX device Transceiver PLL Megawizard show a "Dynamic reconfiguration of ATX PLLs is not supported in the current release" message when you hover your cursor over the "Enable PLL reconfiguration" option in Quartus II software version 13.1?

Due to a problem in the Quartus® II software version 13.1 MegaWizard™ Plug-In Manager, the Arria® V GX and Cyclone® V GX device Transceiver PLL Megawizard shows a "Dynamic reconfig…
www.altera.com/support/kdb/solutions/rd01132014_734.html - 2014-05-07

2014-06-29 0 0 Why does the Quartus II software fail to fit more than four groups of 40G BaseKR IP into one side of a Stratix V device?

When you place more than four groups of 40G BaseKR IP on one side of a Stratix® V device, you might get the following error message: Error (175001): Could not place fractio…
www.altera.com/support/kdb/solutions/rd03272014_628.html - 2014-05-07

2014-06-29 120101 12.1 SP1 0 Why is the pll_powerdown port of the Stratix V device Transceiver Native PHY IP Core not removed when I enable the “Use external TX PLL” option?

Due to a problem in the Quartus® II software, the pll_powerdown port of the Stratix® V device Transceiver Native PHY IP Core is not removed when the “Use external TX PLL” option is…
www.altera.com/support/kdb/solutions/rd05042014_393.html - 2014-05-07

2014-06-29 130100 13.1 0 Critical Warning: parameter 'crcchk_init' of instance '...|sv_hssi_10g_rx_pcs_rbc' has illegal value '' assigned to it. Valid parameter values are: '(crcchk_int)'. Using value 'crcchk_int'

You may see the following warning message when implementing the Stratix® V device 10GBaser-R IP in Quartus® II software versions 13.1 and earlier. Info (10648): Verilog HDL D…
www.altera.com/support/kdb/solutions/rd04292014_918.html - 2014-05-07

2014-05-07 0 0 Why can’t I turn on the rx_clklow and rx_fref ports in the Transceiver Native PHY IP Core for of Arria V, Cyclone V, and Stratix V devices?

Due to a problem with the Altera Transceiver PHY IP Core User Guide (PDF), the rx_clklow and rx_fref ports are incorrectly listed as available on the Native PHY IP Core for Arria® …
www.altera.com/support/kdb/solutions/rd02092014_792.html - 2014-05-07

2014-06-29 130100 13.1 0 Why does the recommendation for the connection of the unused GXB_RX and GXB_REFCLK pins disagree between the Stratix V and Arria V GZ pin connection guidelines documents and the Quartus II software .PIN files?

Due to a problem in Quartus® II Software version 13.1 and earlier, the recommendation for connecting unused GXB_RX and GXB_REFCLK pins for Stratix® V and Arria® V GZ devi…
www.altera.com/support/kdb/solutions/rd03032014_448.html - 2014-05-07

2014-05-07 130100 13.1 0 Error: set_port_property sets an illegal FRAGMENT_LIST for port unused_rx_parallel_data

Due to a problem in Quartus® II software version 13.1 update 3 you may see this error when using an Arria® V device Transceiver Native PHY instance with the “Enable simpl…
www.altera.com/support/kdb/solutions/rd04092014_581.html - 2014-05-07

2014-06-29 0 0 Are there any recommendations when using more than one ATX PLL that run at the same Voltage Controlled Oscillator (VCO) frequency in Arria V GZ and Stratix V transceiver devices?

Yes, there are placement recommendations when using more than one ATX PLL that run at the same VCO frequency in Arria® V GZ and Stratix® V transceiver devices. For optimal ATX PL…
www.altera.com/support/kdb/solutions/rd03282014_193.html - 2014-05-07

2014-05-07 130100 13.1 0 Do Arria V GX devices support the Rate Match FIFO option when the word aligner is in manual alignment mode, and the PMA-PCS interface is 20 bits wide?

Yes, Arria® V GX devices support the Rate Match FIFO option when the word aligner is in manual alignment mode, and the PMA-PCS interface is 20 bits wide. Due to a mistake in Fi…
www.altera.com/support/kdb/solutions/rd03242014_198.html - 2014-05-07

2014-06-29 0 0 Can I invert the transciever Tx polarity with a signal port when using the Stratix V device, Native PHY IP, 10G PCS?

No, You cannot invert the transciever Tx polarity with a signal port when using the Stratix® V device, Native PHY IP, 10G PCS.
www.altera.com/support/kdb/solutions/rd01162014_412.html - 2014-05-07

2014-05-02 130104 13.1
Update4
0 Can the 128-bit Avalon-MM Txs slave interface of the Altera Hard IP for PCI Express handle read/write request with ByteEnable=0x01 ?

Due to a problem in the Quartus® II software version 13.1 and earlier, the 128-bit Avalon-MM® Txs slave interface of the Hard IP for PCI Express® cannot generate a correc…
www.altera.com/support/kdb/solutions/rd04172014_563.html - 2014-05-02

2014-04-30 130100 13.1 0 NicheStack TCP/IP Stack - Nios II Edition No Longer Supported

You might encounter problems using the NicheStack TCP/IP Stack - Nios II Edition. For example, you might see an error similar to the following: inet startup error: unable to find …
www.altera.com/support/kdb/solutions/fb172438.html - 2014-05-01

2014-12-23 130001 13.0 SP1 130100 13.1 Why is the PCI Express endpoint stuck in DETECT.QUIET when using the example Avalon-MM Qsys design?

The Avalon®-MM Stratix® V Hard IP for PCI® Express example design, which is available from the <install_dir>/ip/altera/altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ di…
www.altera.com/support/kdb/solutions/rd12312013_590.html - 2014-04-30

2014-04-30 130001 13.0 SP1 130100 13.1 Error in 'mdm/HDLImport' while executing C MEX S-function 'sGeneric', (mdlStart), at time 0.0.

You may receive the error message below when running a Simulink® simulation which includes the NCO Megacore® block using DSP Builder in an Arria® V design: Error in 'mdm…
www.altera.com/support/kdb/solutions/rd08072013_475.html - 2014-04-30

2014-04-30 120100 12.1 0 Why does alt_signaltap_run fail in MATLAB?

When alt_signaltap_run is run under MATLAB™, an "Assertion failed" pop-up window is displayed and MATLAB crashes when the pop-up is dismissed.
www.altera.com/support/kdb/solutions/rd12132013_803.html - 2014-04-30

2014-04-30 0 0 Warning (12283): Assignment INPUT_TERMINATION on transceiver refclk clk buf/pin is not supported

In Arria® V, Cyclone® V and Stratix® V devices the INPUT_TERMINATION assignment cannot be used on transceiver pins.
www.altera.com/support/kdb/solutions/rd04042013_231.html - 2014-04-30

2014-05-06 0 0 Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"

When recompiling the PCI Express® reference design supplied with AN465 the following error occurs: Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_s…
www.altera.com/support/kdb/solutions/rd02032014_790.html - 2014-04-30

2014-05-27 0 0 Parameter "rstctrl_tx_lc_pll_rstb_select" of instance "stratixv_hssi_gen3_pcie_hip" has illegal value "ch4_10_sel" assigned to it. Possible parameter values are: "NOT_ACTIVE", "CH4_OUT", "CH4_10_OUT", "CH1_OUT", "CH7_OUT".

This error can occur if the parameter force_hrc=1 is set in the Hard IP(HIP) for PCI Express® variant file. Typically this occurs if you are moving from a Gen 2 to Gen 3 …
www.altera.com/support/kdb/solutions/rd04232014_376.html - 2014-04-29

2014-04-28 0 0 How do I launch Transceiver Toolkit without launching the Quartus II software first?

You can not launch Transceiver Toolkit as a standalone application. Transceiver Toolkit can only be launched from the Quartus II® software GUI.
www.altera.com/support/kdb/solutions/rd04112014_654.html - 2014-04-28

2014-05-01 130000 13.0 130100 13.1 Broadcast Deinterlacer Fails to Launch

The Broadcast Deinterlacer MegaCore function in the Video and Image Processing Suite version 13.1 fails to launch. You cannot access the Broadcast Deinterlacer parameters through …
www.altera.com/support/kdb/solutions/fb160499.html - 2014-04-28

2014-04-28 0 0 Why does the Arria V GZ and Stratix V Hard IP for PCI Express Gen3 LTSSM periodically transition from L0 state to the Recovery state then back to L0 state?

A Gen3  Arria® V GZ and Stratix® V Hard IP  for PCI Express® instance may transition from L0 to Recovery and back again if the receive(RX) Physical Coding Sublayer(P…
www.altera.com/support/kdb/solutions/rd04242014_695.html - 2014-04-28

2014-04-28 130100 13.1 0 Error (21075): The junction temperature range value of '[-40 C, 100 C]' is illegal for the currently selected part.

In the Quartus® II software version 13.1, you may see this fitter error if you compile a design targetting a Max® V device in the industrial temperature range that was&nb…
www.altera.com/support/kdb/solutions/rd04152014_654.html - 2014-04-28

2014-05-12 130100 13.1 140000 14.0 Upgrade IP Window Display Incorrect ACDS Version Number for Altera Ethernet 10G MAC Design Examples

When you load any of the Ethernet 10G MAC design examples, the Upgrade IP Cores window displays incorrect current ACDS version. This issue does not have any impact on the version…
www.altera.com/support/kdb/solutions/fb200361.html - 2014-04-28

2014-04-28 130100 13.1 0 Manual Removal of Unsupported Families from VHDL DO File in Customer Testbench

For SerialLite II 13.1 designs using Arria II GX and Stratix IV GX devices, the customer testbench DO file includes obsolete device families. The obsoleted device families includ…
www.altera.com/support/kdb/solutions/fb182571.html - 2014-04-28

2014-05-01 130000 13.0 0 Audio Embed IP Design Transmits Unstable 3G Video Image

Designs using SDI Audio Embed IP core transmit unstable and flickering 3G video images. This issue affects all designs using the SDI Audio Embed MegaCore function version 13.1.
www.altera.com/support/kdb/solutions/fb184377.html - 2014-04-28

2014-05-01 130100 13.1 0 SDI II Does Not Assert Frame Locked Signal and Shows Invalid Receive Format When Receiving Certain Video Formats

The Serial Digital Interface (SDI) II MegaCore function does not assert the frame_locked signal and shows invalid rx_format signal when it receives certain video formats. This iss…
www.altera.com/support/kdb/solutions/fb183561.html - 2014-04-28

2014-04-29 130100 13.1 0 Why don't I get identical fitter results when my source files haven't changed?

Due to a problem in the Quartus® II software version 13.1, you may see that compiles with identical source files do not have identical fitter results if you are using the SignalTap…
www.altera.com/support/kdb/solutions/rd04222014_264.html - 2014-04-28

2014-05-01 130100 13.1 0 Certain Ports and Parameters Not Supported In SDI Audio IP Cores for 13.1

Version 13.1 of the SDI Audio Embed and Audio Extract MegaCore functions do not support certain ports and parameters. The following ports and parameters are not fully implemented.…
www.altera.com/support/kdb/solutions/fb175422.html - 2014-04-28

2014-04-25 130100 13.1 0 How should the DCLK and DATA pins be connected when using the HPS to configure the FPGA fabric in Arria V or Cyclone V SoC devices?

When configuring an Arria® V SoC or Cyclone® V SoC device through the HPS, the configuration DATA pins can be left unconnected. The DCLK pin should not be left uncon…
www.altera.com/support/kdb/solutions/rd04242014_804.html - 2014-04-25

2014-04-28 130000 13.0 0 No OpenCore Plus Feature for V Series

OpenCore Plus feature is not supported for SerialLite II designs that target Arria V, Cyclone V, and Stratix V devices. This issue will be fixed in a future version of the Serial…
www.altera.com/support/kdb/solutions/fb153676.html - 2014-04-25

2014-04-25 0 0 Error (169187): Following feature(s) of I/O pin <pin_name> has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location <pin_location>

Due to a problem in the Quartus® II software you may see this error message when the WEAK_PULL_UP_RESISTOR option is disabled in a project targeting Cyclone® IV…
www.altera.com/support/kdb/solutions/rd04072014_413.html - 2014-04-25

2014-04-17 130000 13.0 130100 13.1 "Port already in use" Error When Attempting to Connect DS-5 to Multiple USB Blaster Targets

The ARM DS-5 debugger supports connecting to only a single USB Blaster debug target at a time on a given host. If you attempt to launch multiple USB Blaster debug connections, DS-…
www.altera.com/support/kdb/solutions/fb145963.html - 2014-04-21

2014-04-16 130000 13.0 0 "FPGA programming might cause HPS boot error” Message While Programming SoC

When you program the FPGA portion of the SoC through the USB Blaster, the contents of the HPS SDRAM can corrupt the session. This noise might overwrite the operating system (OS) i…
www.altera.com/support/kdb/solutions/fb132225.html - 2014-04-18

2014-04-16 120100 12.1 0 Incorrect ACP IDs Listed in HPS Technical Reference Manual

The Hard Processor System Technical Reference Manual lists incorrect values for the HPS peripheral master input IDs in the Accelerator Coherency Port (ACP) ID mapper. The “HPS Per…
www.altera.com/support/kdb/solutions/fb169066.html - 2014-04-18

2014-04-23 0 0 Which Altera FPGA devices support EPCQ-L devices for Active Serial (AS) configuration?

EPCQ-L devices can only be used with Arria® 10 devices for Active Serial (AS) configuration. Older Altera® device families do not support EPCQ-L devices for AS confi…
www.altera.com/support/kdb/solutions/rd04162014_770.html - 2014-04-17

2014-04-17 0 0 Does connecting VCCIO to a different voltage to that stated in the Quartus II fitter report affect device reliability?

Altera® characterizes device operation under conditions consistent with the "Recommended Operating Conditions” that can be found in the respective devices datasheet.  Operatio…
www.altera.com/support/kdb/solutions/rd04082014_356.html - 2014-04-17

2014-04-16 0 0 Why is my Stratix IV Hard IP for PCI Express VHDL altpcierd_write_dma_requester_128.vhd different from its Verilog counterpart?

The Stratix IV® Hard IP for PCI Express® in VHDL has an inconsistency from its Verilog HDL counterpart. This inconsistency can cause errors in a PCIe design for certain a…
www.altera.com/support/kdb/solutions/rd02242014_414.html - 2014-04-16

2014-04-16 0 0 Warning (12192): "10GBASE-R PCS-PMA " does not support the OpenCore Plus Hardware Evaluation feature

You may receive the following messages when trying to generate an OpenCore Plus time limited SOF file for the 10GBASE-R PCS-PMA Etherent IP. Warning (12189): OpenCore Simulation-O…
www.altera.com/support/kdb/solutions/rd04092014_926.html - 2014-04-16

2014-04-16 0 0 How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stratix V devices?

To use the Hard IP for PCI Express® test bus in conjunction with SignalTap™ II, a register map, or general purpose IOs to observe the PIPE interface signals on Arria® V GZ a…
www.altera.com/support/kdb/solutions/rd03042014_402.html - 2014-04-16

2014-09-01 0 0 How do I view the external memory signals in my HPS SDRAM simulation?

The HPS simulation model does not use external memory pins to connect to the DDR2, DDR3 or LPDDR2  memory model. The actual memory model is created internally in the…
www.altera.com/support/kdb/solutions/rd04092014_381.html - 2014-04-15

2014-04-15 0 0 How do I fix the core setup timing violations when I bond two DDR3 hard memory controllers from the top edge to bottom edge of the FPGA device?

When you bond two DDR3 hard memory controllers (HMC) located on the top and bottom edges and use pll_afi_half_clk as the clock for the MPFE port, you may g…
www.altera.com/support/kdb/solutions/rd03112014_680.html - 2014-04-15

2014-04-30 0 0 Error: pcie_av_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"

This error will be seen when generating a testbench for the PCI Express® reference design supplied with AN456 in either Arria® V or Cyclone® V devices. This error is…
www.altera.com/support/kdb/solutions/rd04092014_108.html - 2014-04-15

2014-04-15 130200 13.1
Arria 10
Edition
0 Why do I see a NCSim simulation error when using the Arria 10 Hard IP for PCI Express?

You may see the error below in NCSim when using the Arria® 10 Hard IP for PCI Express®, due to a missing timescalencelab: *F,CUMSTS: Timescale directive missing on one or more modu…
www.altera.com/support/kdb/solutions/rd04112014_359.html - 2014-04-15

2014-04-15 130001 13.0 SP1 130103 13.1
Update3
Error (12012): Port direction mismatch for entity "altpcie_sv_hip_avmm_hwtcl:pcie_avgz_hip_avmm_0" at port "tlbfm_out[0]". Upper entity is expecting "Output" pin while lower entity is using "Input" pin.

This error may be seen when trying to compile an Arria® V GZ or Stratix® V Hard IP for PCI Express® for the Avalon® Memory Mapped Qsys component in VHDL.This problem is due to…
www.altera.com/support/kdb/solutions/rd04012014_517.html - 2014-04-15

2014-04-15 130100 13.1 0 When does the UniPHY DDR3 IP use an I/O standard of SSTL-15 Class II ?

When the UniPHY DDR3 PHY Settings tab "Memory Clock frequency" parameter is set above 800MHz, the default DDR3 interface signal I/O standard is set to SSTL-15 Class II to increase …
www.altera.com/support/kdb/solutions/rd11132013_424.html - 2014-04-15

2014-04-14 0 0 Error (170039): Cannot place RAM cells or portions of RAM cells in the design

Due to a problem in Quartus® II software version 13.1 and earlier, you may see this fitter error if you defined nesting reserved and non-reserved regions and floating LogicLoc…
www.altera.com/support/kdb/solutions/rd04082014_701.html - 2014-04-14

2014-04-14 110100 11.1 0 VHDL Postfit Simulation Not Supported for Arria V and Cyclone V Designs with Hard Memory Controller

This problem affects DDR2, DDR3, and LPDDR2 products using hard memory controllers. VHDL postfit simulation is not supported for Arria V and Cyclone V designs containing hard memo…
www.altera.com/support/kdb/solutions/fb119316.html - 2014-04-14

2014-04-14 0 0 Does the Stratix V device family support the Enable Beneficial Skew Optimization option?

No, the Stratix® V device family does not support the Enable Beneficial Skew Optimization option.
www.altera.com/support/kdb/solutions/rd04012014_513.html - 2014-04-14

2014-07-04 130100 13.1 0 Error May Occur When Generating Hard Memory Controller in Qsys

This problem affects DDR2 and DDR3 interfaces using the hard memory controller in Arria V or Cyclone V devices. When using Qsys to generate an Arria V or Cyclone V external memory…
www.altera.com/support/kdb/solutions/fb181874.html - 2014-04-14

2014-04-14 130100 13.1 0 Internal Error: Sub-system: HDB, File: /quartus/db/hdb//hdb_asgn.cpp, Line: 1571

Due to a problem in the Quartus® II software version 13.1 and later, you may see this Internal Error when compiling a design with a Quartus II Exported Partion File (.qxp)
www.altera.com/support/kdb/solutions/rd04012014_757.html - 2014-04-14

2014-04-14 0 0 Why does the Quartus II software incorrectly show “Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus II v13.1 with a preliminary timing model and constraints..”?

Due to a problem in the Quartus® II software version 13.1 Update 3 and later, you may see the the following critical warnings when compiling a Cyclone® V SoC HP…
www.altera.com/support/kdb/solutions/rd03172014_960.html - 2014-04-14

2014-04-11 0 0 Do the PowerPlay Early Power Estimators (EPE) which incorporate the Enpirion integrated solution add margin to the load current that is estimated?

Yes, EPEs which incorporate the Enpirion® integrated solution report the total summed currents with an additional 30% margin. Please see the tooltip on cell labelled “Lo…
www.altera.com/support/kdb/solutions/rd04102014_752.html - 2014-04-11

2014-04-11 0 0 Is it safe to ignore incomplete I/O assignment warning messages in the Quartus II software for Active Parallel configuration pins?

Yes, it is safe to ignore incomplete I/O assignment warning messages in the Quartus® II software, for dual purpose configuration pins that are used for Active …
www.altera.com/support/kdb/solutions/rd03312014_182.html - 2014-04-11

2014-04-09 120100 12.1 0 NativeLink Simulation of DDR2, DDR3, and LPDDR2 Interfaces Fails for ModelSim AE and ModelSim SE

This problem affects DDR2, DDR3, and LPDDR2 products. When you attempt to simulate a DDR2, DDR3, or LPDDR2 design using NativeLink with ModelSim or ModelSim-Altera, NativeLink fai…
www.altera.com/support/kdb/solutions/fb77918.html - 2014-04-09

2014-04-08 130100 13.1 0 Why does the tx_datak signal refer to received data for the Arria V, Cyclone V and Stratix V devices in the Altera Transceiver PHY IP User Guide?

Due to mistakes in "Table 9-12: Avalon-ST TX Interface Signals" and "Table 11-8: Avalon-ST TX Interface" of the Altera® Transceiver PHY IP Core User Guide (PDF) the tx_datak s…
www.altera.com/support/kdb/solutions/rd03032014_187.html - 2014-04-08

2014-04-08 130100 13.1 0 Why does the Arria 10 device Transceiver PHY User Guide (PDF) describe the tx_datak signal as '1' for a data word and '0' as a control word?

Due to a mistake in "Table 2-40: TX Standard PCS: Data, Control, and Clocks" of the Arria® 10 device Transceiver PHY User Guide (PDF) the tx_datak signal is described as being '1' …
www.altera.com/support/kdb/solutions/rd03032014_183.html - 2014-04-08

2014-04-07 0 0 How are the IO pins that migrate to NC configured by the Quartus II software, when compiling a design targeting Arria V, Cyclone V or Stratix V devices, with migration devices selected?

When compiling a design targeting Arria®  V, Cyclone®  V or Stratix®  V devices, with migration devices selected, IO pins that migrate to NC will be configured as …
www.altera.com/support/kdb/solutions/rd04042014_245.html - 2014-04-07

2014-04-07 120101 12.1 SP1 0 How do I disable the transceiver On-Chip-Termination (OCT) of the Stratix IV GT device 10GBase-R PHY IP?

You can disable the transceiver On-Chip-Termination (OCT) of the Stratix® IV GT device 10GBase-R PHY IP by following the steps below. Open the MegaWizard™ generated siv_xcvr_low…
www.altera.com/support/kdb/solutions/rd04102013_210.html - 2014-04-07

2014-04-07 130100 13.1 0 Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic.

You may encounter the following warnings with the XAUI PHY IP in Arria® V GZ and Stratix® V devices during the Quartus® II software version 13.1 compilation: Warning (12…
www.altera.com/support/kdb/solutions/rd12262013_338.html - 2014-04-07

2014-12-02 130100 13.1 0 Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria V GZ, and Stratix V GX/GT devices?

The tx_cal_busy signal will not assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ, and Stratix® V GX/GT devices. The tx_cal_busy s…
www.altera.com/support/kdb/solutions/rd03052014_988.html - 2014-04-07

2014-04-07 0 0 Error: Standard RX/TX PCS Parameter 'hd_pcs8g_digi_rx/tx_byte_deserializer' is set to an illegal value of 'en_bds/bs_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom.

You may see the following Quartus® II software fitter error when using the transceiver PHY instance and the “enable Byte Serializer/Deserializer with 16- and 20-Bit PMA-PCS Widths”…
www.altera.com/support/kdb/solutions/rd03172014_8.html - 2014-04-07

2014-04-07 0 0 Why is the input common mode voltage (VICM) of the Arria II GX dedicated transceiver refclk pins lower than the 1.1V device specification?

Due to a problem in the Quartus® II software version 13.1 and earlier, the input common mode voltage (VICM) of the Arria® II GX dedicated transceiver refclk pins with on-chip…
www.altera.com/support/kdb/solutions/rd02242014_573.html - 2014-04-07

2014-06-29 0 0 How can I enable transceiver polarity inversion in the 10GBASE-R PHY IP for Arria V GZ and Stratix V GX devices?

You can enable transceiver polarity inversion in the 10GBASE-R PHY IP for Arria® V GZ and Stratix® V GX devices by following the sequence below. Generate the 10GBase-R PHY …
www.altera.com/support/kdb/solutions/rd03272014_29.html - 2014-04-07

2014-04-04 100101 10.1 SP1 0 Why do I get this and similar warning messages in Qsys: pcie_internal_hip.rc_rx_analogreset must be exported, or connected to a matching conduit?

Starting in Quartus® II software version 10.1 SP1, there were changes to the implementation of the PCI Express® IP when using Qsys and SOPC Builder.  The changes implemented c…
www.altera.com/support/kdb/solutions/rd08182011_29.html - 2014-04-04

2014-04-04 0 0 ** Warning: nofile(37): in protected region.

You may experience the above warning while simulating a VHDL-based DDR3 UniPHY memory controller with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog an…
www.altera.com/support/kdb/solutions/rd12162013_873.html - 2014-04-04

2014-04-04 0 0 Is it possible to connect ADCGND directly to GND on Arria 10 devices, when the voltage sensor and temperature sensing diode features are not used?

No. ADCGND pins on Arria® 10 devices should be connected to a separate board ground plane from GND, or to GND via a proper isolation filter, even if t…
www.altera.com/support/kdb/solutions/rd03312014_553.html - 2014-04-04

2014-04-04 120101 12.1 SP1 0 Why do I see incorrect read data when using a Hard Memory Controller with multiple MPFE ports?

When performing write and read transactions to the hard memory controller (HMC) MPFE ports, you may observe that the read transactions are performed before the write transactions e…
www.altera.com/support/kdb/solutions/rd09242013_535.html - 2014-04-04

2014-04-04 110100 11.1 0 How do I constrain the Serial RapidIO IP core when implementing multiple instances in a Qsys system?

When you generate a Qsys system that contains the Serial RapidIO® IP, Qsys generates a (.tcl) script and Synopsys Design Constraint(.sdc) file for your IP. The .sdc file does not w…
www.altera.com/support/kdb/solutions/rd01302014_527.html - 2014-04-04

2014-06-18 0 0 How do I set up the environment variables so I can launch the Altera device development kit GUI?

The Altera® device development kit (Board Test System (BTS), CLK, and Power) GUIs heavy rely on the Quartus® II software version due to specific library requirements. Unlike o…
www.altera.com/support/kdb/solutions/rd01292013_416.html - 2014-04-04

2014-04-04 0 0 Why do I get warnings for my correctly configured PCI Express core in Qsys?

When instantiating a IP Compiler for PCI Express® core within Qsys, the following warnings can appear, even though the core is configured and connected correctly: Warning: System.…
www.altera.com/support/kdb/solutions/rd11172011_691.html - 2014-04-04

2014-04-04 0 0 Can alternative Ra/Rb resistor values be used instead of those recommended by Altera even if they derive the same ratio, when using Enpirion EN5364 or EN5322 devices?

No. Ra is part of the loopback circuitry of the Enpirion® EN5364 and EN5322 devices and therefore Altera® does not recommend deviating from the recommended resistor values that can…
www.altera.com/support/kdb/solutions/rd03312014_647.html - 2014-04-04

2014-04-04 100101 10.1 SP1 0 Why do I get the following warning message in Qsys: pcie_internal_hip.pice_core_clk cannot be both connected and exported?

Starting in Quartus® II software version 10.1 SP1, you may see this warning message, even though you are not both connecting and exporting these signals.  You may also see&nb…
www.altera.com/support/kdb/solutions/rd08182011_364.html - 2014-04-04

2014-04-04 0 0 When selecting "Use differential mode" in the ALTIOBUF megafunction and using differential SSTL or HSTL IO standards, will the output buffer be implemented as a true differential buffer?

No, differential SSTL or HSTL outputs can only be implemented as single-ended pseudo-differential outputs. However, SSTL and HSTL differential input buffers are…
www.altera.com/support/kdb/solutions/rd04032014_345.html - 2014-04-04

2014-04-04 130000 13.0 0 Why is the reported center DQS enable calibration result outside of the start - end range when the runtime calibration report is enabled for the HPS external memory controller?

Due to a probem in the HPS SDRAM Controller calibration algorithm generated by the Altera SoC Embedded Design Suite for Cyclone® V SoC and Arria® V SoC&nbs…
www.altera.com/support/kdb/solutions/rd02102014_671.html - 2014-04-04

2014-04-03 130100 13.1 0 WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU has no memories connected to its Avalon master(s)

Due to a problem in the Quartus® II software version 13.1, users cannot dynamically set the Address Span expander to be / not be visible as memory for the Nios® II i…
www.altera.com/support/kdb/solutions/rd03182014_17.html - 2014-04-03

2014-04-02 130100 13.1 0 How do I enable serial loopback in Serial RapidIO IP core?

In the Quartus® II software version 13.1 and earlier, the Serial RapidIO® IP core does not have a register or a port in top level module that enables serial loopback.
www.altera.com/support/kdb/solutions/rd03042014_469.html - 2014-04-02

2014-04-02 0 0 Why can't I observe any activity on the Triple Speed Ethernet MegaCore Function’s RGMII_OUT signals in the SignalTap II Logic Analyzer?

The RGMII_OUT registers are implemented using Alt DDIO_OUT atoms which cannot be observed using SignalTap™ as a routing path to the core is not possible. Hence it is not …
www.altera.com/support/kdb/solutions/rd03122014_936.html - 2014-04-02

2014-04-02 0 0 Why does my third-party PCI Express Bus Functional Model (BFM) flag invalid symbol after End of Data Stream (EDS) token?

The Arria® V GZ and Stratix® V Hard IP for PCI Express® may cause third party BFMs to flag invalid symbol after EDS for the following reason: When the Hard IP for PCI Ex…
www.altera.com/support/kdb/solutions/rd01302014_94.html - 2014-04-02

2014-04-02 0 0 Why does my Stratix V Hard IP for PCI Express in Gen3 configuration fail to link up to L0 after toggling pin PERST in simulation?

When simulating Stratix® V and Arria® V GZ Hard IP for PCI Express® as an Endpoint, the PCIe Hard IP can become stuck at Speed.Recovery if the Hard IP is reset …
www.altera.com/support/kdb/solutions/rd02242014_943.html - 2014-04-02

2014-04-02 130100 13.1 0 How do I connect aud_z signal from SDI Audio Extract MegaCore?

The aud_z signal from the Altera® Serial Digital Interface (SDI) Audio Extract MegaCore® is not required.   You can ignore this signal. 
www.altera.com/support/kdb/solutions/rd03122014_224.html - 2014-04-02

2014-04-02 0 0 What is the maximum payload size supported in Stratix V Hard IP for PCI Express?

Due to a documentation error, the table Dynamically Reconfigurable Registers in the Hard IP Implementation of the Stratix® V Hard IP for PCI Express® User Guide shows a 4096 byte m…
www.altera.com/support/kdb/solutions/rd03272014_687.html - 2014-04-02

2014-04-02 0 0 Line <line> : Invalid data rate! Cell value must be between 0.0 and 1434.0 Skipping!

You may see this error when importing a Quartus® II generated PowerPlay Early Power Estimator (EPE) File into the EPE tool version 13.1 and earlier, for a Stratix® V desi…
www.altera.com/support/kdb/solutions/rd04022014_893.html - 2014-04-02

2014-07-22 0 0 Why can't I simulate the Arria II IP Compiler for PCI Express in Quartus 13.1?

HardCopy® IV and Stratix® II support was removed from 13.1. You may see an error such as that shown below: # ** Error: (vlog-7) Failed to open design unit file "/tools/acds/1…
www.altera.com/support/kdb/solutions/rd04012014_271.html - 2014-04-02

2014-03-28 120100 12.1 0 Unexplained Errors After Compilation in Nios II Software Build Tools for Eclipse

After compiling a project with the Nios II Software Build Tools for Eclipse, you might encounter a <function/symbol> could not be resolved message, or unexpected error marke…
www.altera.com/support/kdb/solutions/fb91565.html - 2014-04-01

2014-03-28 130100 13.1 0 Example Code Error in Nios II Processor Reference Handbook, Application Binary Interface Chapter

In the Application Binary Interface chapter of the Nios II Processor Reference Handbook, Example 7-3 (“Returned struct is Larger than 8 Bytes”) contains a typographical error. *va…
www.altera.com/support/kdb/solutions/fb141549.html - 2014-04-01

2014-03-26 70201 7.2 SP1 100000 10.0 Windows Vista: Limited Support in Nios II EDS

The Quartus II software introduced Windows Vista (32-bit and 64-bit) support in version 7.2. However, 7.2SP1 and several ensuing releases of the Nios II Embedded Design Suite supp…
www.altera.com/support/kdb/solutions/spr257471.html - 2014-03-31

2014-03-31 130100 13.1 0 How do I specify the web browser in the Quartus II software version 13.1 and later?

In the Quartus® II software version 13.1 and later, the Tools > Options > Web Browser setting has been removed and the software uses the default web browser specifi…
www.altera.com/support/kdb/solutions/rd12132013_991.html - 2014-03-31

2014-03-31 0 0 Why are the assignments via altera_attribute not being applied correctly?

Due to a problem in the Quartus® II software version 13.1 and earlier, the Verilog HDL synthesis attribute may not be processed correctly if you were using pragma-style attributes.…
www.altera.com/support/kdb/solutions/rd03132014_457.html - 2014-03-31

2014-04-03 0 0 How do I resolve timing violations on the quarter rate to half rate clock transfer in my UniPHY-based DDR3 controller design?

When the UniPHY DDR3 controller in quarter rate mode is operated at or near the maximum frequencies specified in the External Memory Interface Spec Estimator Tool (HTML), you may s…
www.altera.com/support/kdb/solutions/rd03262014_301.html - 2014-03-31

2014-03-31 0 0 Internal Error: Sub-system: GIOQ, File: /quartus/edt/gioq/gioq_port.cpp, Line: 696

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when you double click on any port connection wire in a Block Design File (.bdf).
www.altera.com/support/kdb/solutions/rd02232014_760.html - 2014-03-31

2012-06-26 130001 13.0 SP1 130100 13.1 Spurious Error Messages from sopc2dts

When you are generating the device-tree source file (.dts) for an SoC HPS hardware design, you might see a large number of spurious error messages. The following list shows some …
www.altera.com/support/kdb/solutions/fb127751.html - 2014-03-31

2014-03-26 130100 13.1 130101 13.1
Update1
Introduction to the Hard Processor System Contains Incorrect Addresses

The Introduction to the Hard Processor System chapter of Volume 3: Hard Processor System Technical Reference Manual in the Arria V Device Handbook and Cyclone V Device Handbook co…
www.altera.com/support/kdb/solutions/fb167123.html - 2014-03-31

2014-03-31 130200 13.1
Arria 10
Edition
0 Error (12595): Design Assistant information: Design Assistant does not support current family.

Due to a Problem in the Quartus® II software version 13.1 A10, you may see the following error when you compile an Arria® 10 design with Design Assistant enabled. E…
www.altera.com/support/kdb/solutions/rd03252014_863.html - 2014-03-31

2014-03-27 130001 13.0 SP1 130100 13.1 Spurious Error Messages from sopc2dts

When you are generating the device-tree source file (.dts) for an SoC HPS hardware design, you might see a large number of spurious error messages. The following list shows some …
www.altera.com/support/kdb/solutions/fb127751.html - 2014-03-31

2014-03-31 0 0 Package effects when probing at the FPGA pin

When comparing signals probed at the memory device and the FPGA pins, it is observed on the oscilloscope that the signals at the FPGA pins have severe reflections when co…
www.altera.com/support/kdb/solutions/rd03182014_79.html - 2014-03-31

2014-03-31 0 0 Why does the fitter report display Use as programming pin for nCEO regardless of Dual purpose pin settings?

Due to a problem in the Quartus® II software, the fitter report the Dual Purpose and Dedicated Pins section incorrectly displays Use as programming pin for the …
www.altera.com/support/kdb/solutions/rd03102014_780.html - 2014-03-31

2014-03-26 130100 13.1 0 Many New Warnings in Altera HAL Code with GCC 4.7.3

Upgrading from GCC 4.1.3 to GCC 4.7.3 generates more warnings than before. You are likely to see more warning messages when compiling Altera’s BSP code.
www.altera.com/support/kdb/solutions/fb145297.html - 2014-03-28

2014-03-28 0 0 Why are interrupts not working in my PCI Express End Point

When using the Altera® IP Compiler for PCI Express®, interrupts will not work for all configurations of the IP, except for completer only single dword variants, if the CR…
www.altera.com/support/kdb/solutions/rd03282014_331.html - 2014-03-28

2014-03-28 110000 11.0 110100 11.1 Why does my PCI Express end point design, using legacy interrupts, send the "Deassert_INTA" message immediately after the “Assert_INTA” message, when signal Rxmirq_irq[n] is still asserted?

Due to a problem with the PCI Express® core implementation in the Quartus® II software, the Deassert_INTA message may be sent out shortly after the Assert_INTA message, while the R…
www.altera.com/support/kdb/solutions/rd10062011_172.html - 2014-03-28

2014-03-25 130000 13.0 0 DS-5 Not Installed with SoC EDS Installation on Linux

If the xterm package is not installed before installing SoC EDS, the DS-5 installation is not launched at the end of the SoC EDS installation on Linux.
www.altera.com/support/kdb/solutions/fb113913.html - 2014-03-27

2014-03-27 0 0 Why are RESPONSE packets from the RapidIO I/O Write Master dropped?

The RESPONSE packets to NWRITE_R packets may be dropped by the I/O Write Master within the RapidIO® MegaCore® function when there is insufficient bandwidth on the Transport Layer t…
www.altera.com/support/kdb/solutions/rd03242014_446.html - 2014-03-27

2014-04-01 0 0 Which exposed pads represent VCC or GND pads for a 148 pin QFN package?

The middle pad (Yellow) represents the ground pad while the side pad (Red) represents the  core VCC pad which is VCCINT.  
www.altera.com/support/kdb/solutions/rd11212012_540.html - 2014-03-25

2014-03-21 130100 13.1 130102 13.1
Update2
Memory Parameter Presets May Not Appear in Parameter Editor

This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products. When using the Quartus II software version 13.1, and targeting an Arria V, Cyclone V, or Stratix V devi…
www.altera.com/support/kdb/solutions/fb191203.html - 2014-03-24

2014-03-24 0 0 Why are there timing violations within my Altera PLL Reconfig megafunction?

The maximum frequency for the mgmt_clk and scanclk reconfiguration clock inputs for PLL reconfiguration are specified in the respective device datasheets for Stratix® V, Arria® V a…
www.altera.com/support/kdb/solutions/rd03242014_72.html - 2014-03-24

2014-03-21 0 0 How is the on-board USB-Blaster II powered?

The on-board USB-Blaster™ II solution is powered via your PCB JTAG header pin 4 and not the USB port on your computer.
www.altera.com/support/kdb/solutions/rd03292013_938.html - 2014-03-21

2014-06-06 0 0 How do I access the EPCQ configuration device on the Cyclone V GT FPGA Development Kit?

The MAX® V design provided with the Cyclone® V GT FPGA development kit does not allow you to access the EPCQ configuration device that is fitted …
www.altera.com/support/kdb/solutions/rd02112014_88.html - 2014-03-21

2014-04-20 120100 12.1 0 Is there a known issue with the mif file generated for PLL reconfiguration, for Arria V, Cyclone V and Stratix V devices?

Yes, when the Altera_PLL Megawizard is used to generate a Memory Initialization File (.mif) for Arria® V, Cyclone® V or Stratix® V devices, the generated file will contain the…
www.altera.com/support/kdb/solutions/rd02242014_46.html - 2014-03-21

2014-03-21 0 0 How do I download the latest version of the Board Skew Parameter Tool?

The 'Board Skew Parameter Tool' can be downloaded using the following link:Board Skew Parameter Tool (.HTML)This tool enables you to calculate the board skew parameter values requi…
www.altera.com/support/kdb/solutions/rd10232012_771.html - 2014-03-21

2015-03-02 130100 13.1 0 Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1

Due to a problem in the Quartus II software, the Quartus Programmer must be used to program EPCQ devices using a generated .jic file in order to enable 4 bytes …
www.altera.com/support/kdb/solutions/rd11192013_118.html - 2014-03-21

2014-07-31 0 0 Can I use a USB Blaster download cable for AES key programming?

For device families that support non-volatile AES key programming for design security, you will need to use either an EthernetBlaster, EthernetBlaster II or USB…
www.altera.com/support/kdb/solutions/rd01032008_684.html - 2014-03-21

2014-07-04 130000 13.0 0 What is the maximum baud rate on the HPS UART?

The Cyclone ® V Device Handbook contains conflicting information regarding the maximum baud rate regarding the internal UART.
www.altera.com/support/kdb/solutions/rd12132013_749.html - 2014-03-20

2014-03-20 130001 13.0 SP1 130100 13.1 Why can't I see any SDRAM Presets in QSYS Hard Processer System Megawizard?

Due to a problem in the Quartus® II software version 13.0SP1,  DDR presets are not visble in the SDRAM tab of the HPS megawizard.
www.altera.com/support/kdb/solutions/rd12102013_700.html - 2014-03-20

2014-03-20 90100 9.1 0 Why does my Nios II software crash unexpectedly when using MicroC/OS-II with Vectored Interrupt Controller(VIC) ?

The Vectored Interrupt Controller (VIC) is not currently supported for use with MicroC/OS-II  based systems.  The Nios II MicroC/OS-II multitasking kernel&…
www.altera.com/support/kdb/solutions/rd02162014_886.html - 2014-03-20

2014-03-20 0 0 Why does my Nios II processor simulation fail when the data cache line size is set to 4 bytes?

You may encounter a simulation failure with the Nios® II processor when the data cache line size is set to 4 bytes.  The failures you may observe are: Failing to dis…
www.altera.com/support/kdb/solutions/rd02172014_343.html - 2014-03-20

2014-03-20 90102 9.1 SP2 110000 11.0 Nios II Options Do Not Appear in Eclipse

When Nios® II SBT for Eclipse starts, the Nios II plugins might fail to load, resulting in the following symptoms: The Nios II perspective is not availab…
www.altera.com/support/kdb/solutions/rd08162011_378.html - 2014-03-20

2014-03-20 130100 13.1 0 How do I connect the detected_rate and detected_rate_in signals from the Serial Digital Interface (SDI) MegaCore?

The detected_rate signal is available when you generate the SDI MegaCore® in Transceiver Only configuration.The detected_rate_in signal is available when you generate t…
www.altera.com/support/kdb/solutions/rd03122014_306.html - 2014-03-20

2014-07-04 130000 13.0 0 Which clock is the reference clock for HPS Ethernet MDC clock?

The correct reference clock for HPS Ethernet clock is l4_mp_clk. The V HPS Address Map, emac->gmacgrp->GMII_Address->cr incorrectly states the CSR clock range select…
www.altera.com/support/kdb/solutions/rd03132014_729.html - 2014-03-20

2014-03-20 130000 13.0 130100 13.1 Why do I see errors when compiling the Video Sync Generator in Quartus II 13.0 and 13.0sp1.

Due to a problem in the Quartus® II software version 13.0 and 13.0sp1,  the Video Sync Generator component does not declare HDL parameters for Qsys systems generated in Verilo…
www.altera.com/support/kdb/solutions/rd11262013_466.html - 2014-03-20

2014-03-31 130100 13.1 0 Why don't I see the h2f_rst_n signal assert in HPS simulation?

Due to a problem in the Quartus® II software BFM simulation model, asserting the "h2f_rst_n" signal does not drive the "h2f_rst_n" signal. This causes unexpecte…
www.altera.com/support/kdb/solutions/rd02042014_881.html - 2014-03-20

2014-03-20 130000 13.0 130100 13.1 Why does the Lauterbach memory watch window display inconsistent values ?

Due to a problem in the Quartus II software version 13.0, the data display in the Lauterbach memory watch window is not consistent due to an arbitration logic bug that causes …
www.altera.com/support/kdb/solutions/rd03192014_964.html - 2014-03-20

2014-03-20 130100 13.1 0 Why doesn't the Frame Buffer IP generate a simulation model?

Due to a problem in the Quartus® II software for Linux version 13.1, the MegaWizard™ Plug-In Manager fails to generate a simulation model for the Frame Buffer IP and issues the fol…
www.altera.com/support/kdb/solutions/rd03062014_597.html - 2014-03-20

2014-03-20 0 0 Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_logical_physical_mapping.cpp, Line: 562

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error if your Arria® V design includes the Altera® Serial Digital Interface (SDI) II Megacor…
www.altera.com/support/kdb/solutions/rd03062014_292.html - 2014-03-20

2014-03-20 100000 10.0 100100 10.1 Run Configuration Cannot Find Imported Custom Makefile Project

After you import a project using the Import Custom Makefile for Nios II Software Build Tools Project option, the Nios II SBT fails to recognize the imported custom…
www.altera.com/support/kdb/solutions/rd08162011_501.html - 2014-03-20

2014-03-20 130000 13.0 0 Why do my make files fail in Altera ARM DS-5 on Windows?

If the ARM Development Studio™ 5 (DS-5™) Altera Edition Toolkit eclipse is launched from the DS-5 Windows Start Menu group,  any scripts or Makefiles will run in a DOS co…
www.altera.com/support/kdb/solutions/rd07042013_512.html - 2014-03-20

2014-03-19 110100 11.1 0 Error: System.DUT.config_tl/APPS.config_tl: Signal tl_cfg_sts has width 73 on DUT.config_tl, but has width 123 on APPS.config_tl

In Arria® V and Cyclone® V Hard IP for PCI Express reference designs, if you set the parameter 'Number of functions' to a value greater than one in the APPS (Altera's DMA) componen…
www.altera.com/support/kdb/solutions/rd03032014_155.html - 2014-03-19

2014-03-19 130100 13.1 0 Why is timing not closing in my Stratix V Hard IP for PCI Express on Quartus 13.1?

Timing may not closing in the Stratix® V Hard IP for PCI® Express because constraints are missing on internal clocks that are in separate domains.
www.altera.com/support/kdb/solutions/rd03052014_71.html - 2014-03-19

2014-04-10 130100 13.1 0 Why does the simulation script for the PCIe HIP chaining_dma example design fail?

Due to a problem in the Quartus® II software version 13.1, the simulation script generated for the PCIe HIP chaining_dma example design fails because it uses the Stratix® II and Ha…
www.altera.com/support/kdb/solutions/rd03052014_334.html - 2014-03-19

2014-03-13 120100 12.1 130000 13.0 Long Locking Time when Switching between HD and 3G in SDI II IP Core in Stratix V and Arria V Devices

A long locking time occurs when switching between high definition (HD) and third-generation (3G) in the serial digital interface (SDI) II core for Stratix V and Arria V devices.
www.altera.com/support/kdb/solutions/fb86360.html - 2014-03-14

2014-03-13 0 0 Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command

Information messages regarding clock uncertainty may be seen in some UniPHY IP applications. Info (332171): The following clock uncertainty values are less than the recommended val…
www.altera.com/support/kdb/solutions/rd01072013_565.html - 2014-03-13

2014-03-13 130000 13.0 130100 13.1 Cyclone V SoC and Arria V SoC Hard Processor System SDRAM calibration fails with the Quartus II software versions 13.1.1 and 13.1.2

When the HPS preloader is compiled from handoff files generated by the Quartus® II software versions 13.1.1 and 13.1.2, SDRAM calibration will fail immediately in Stage 1…
www.altera.com/support/kdb/solutions/rd02272014_719.html - 2014-03-13

2014-03-13 130100 13.1 0 Why does the Gen3 x8 AVMM 256-bit DMA design hang when the host attempts to perform two accesses in a row to the descriptor controller interface?

In Quartus® II software version 13.1, you may see the Hard IP for PCI Express® using Avalon® Memory-Mapped interface with DMA design crash if the descriptor controller in…
www.altera.com/support/kdb/solutions/rd03052014_175.html - 2014-03-13

2014-03-20 130100 13.1 0 Error (11802): Can't fit design in device.

You may encounter the following fitter error when compiling a 16-bit DDR3 hard memory controller design in a Cyclone® V A5 device with the Quartus II softw…
www.altera.com/support/kdb/solutions/rd03062014_997.html - 2014-03-13

2014-03-31 0 0 How can I re-host my DS 5 AE License?

DS-5 Altera Edition licenses are  'FIXED' and node-locked. If  you need to transfer your license to a new machine, you must ask ARM to do the 're-host'.&nb…
www.altera.com/support/kdb/solutions/rd02132014_454.html - 2014-03-12

2014-03-12 110001 11.0 SP1 130000 13.0 Why do I not see interrupts on the Scatter Gather DMA controller when writing zero to the MAX_DESCRIPTOR_PROCESSED field?

An issue has been identified in the Scatter Gather DMA that prevents the interrupt ocurring when MAX_DESC_PROCESSED field is set to 0.
www.altera.com/support/kdb/solutions/rd11082011_653.html - 2014-03-12

2014-03-12 130100 13.1 0 Can I use TK from System Console?

Yes, the TK libraries and functions can be used from System Console.
www.altera.com/support/kdb/solutions/rd01212014_911.html - 2014-03-12

2014-03-12 90100 9.1 0 Why can I not accelerate my floating point division using the Floating Point Divider Custom Instruction

There is currently a known issue where Nios® II Software Build tool for Eclipse (SBT4E) does not automatically add the "-mcustom-fpu-cfg=60-2" flag even if your design created wi…
www.altera.com/support/kdb/solutions/rd08222011_115.html - 2014-03-12

2014-06-29 130100 13.1 0 Error (12848): "REF10GCLK" is locked to right side. There is no HSSI strip on right side.

Due to a bug in the Quartus® II software version 13.1, you may see the Fitter error above.
www.altera.com/support/kdb/solutions/rd02092014_966.html - 2014-03-11

2014-03-11 130000 13.0 0 Warning: New Pin Type Dedicated Clock

You may see this message when generating a Boundary Scan Description Language (BSDL) file in the Quartus® II software, for your design. This message requires no action from t…
www.altera.com/support/kdb/solutions/rd03102014_341.html - 2014-03-11

2014-06-30 130001 13.0 SP1 0 Why doesn't the "set_parameter -name pma_bonding_master" Quartus Settings File (.qsf) assignment have an effect in the Quartus II software version 13.0sp1 for Arria V, Cyclone V, or Stratix V devices?

Due to a problem in the Altera® Transceiver PHY IP Core User Guide (PDF) version 2013.7.1, the "set_parameter -name pma_bonding_master" Quartus® Settings File (.qsf) assignment wil…
www.altera.com/support/kdb/solutions/rd10312013_951.html - 2014-03-11

2014-03-11 0 0 How do I use the CHANGE_EDREG instruction to simulate a CRC error in Stratix, Stratix II, Arria GX, and Cyclone II and later series devices?

You can download the contents required to create a crc.jam file and follow the instructions below to issue the CHANGE_EDREG instruction to simulate a CRC e…
www.altera.com/support/kdb/solutions/rd01152010_577.html - 2014-03-11

2014-03-10 0 0 How do I use the Configuration via Protocol (CvP) Update with Revision Flow in a source controlled environment?

To use the CvP Update with Revision Flow in a source controlled environment with multiple team members: 1) Create an archive (QAR) of the base revision which include…
www.altera.com/support/kdb/solutions/rd03042014_441.html - 2014-03-10

2014-03-10 120100 12.1 0 Internal Error: Sub-system: FTITAN, File: /quartus/fitter/ftitan/ftitan_expert.cpp, Line: 4431

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error in designs that implement the altlvds_rx megafunction with the Use External PLL option…
www.altera.com/support/kdb/solutions/rd03052014_169.html - 2014-03-10

2014-03-07 130100 13.1 0 Which device families have been removed from the Quartus II software starting with version 13.1?

The Quartus® II software version 13.1 no longer supports the following devices: MAX® 3000A, MAX 7000AE, MAX 7000S, MAX 7000B devices HardCopy II, HardCopy III, HardCopy IV (E/G…
www.altera.com/support/kdb/solutions/rd08252013_188.html - 2014-03-07

2014-11-03 110100 11.1 0 Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express?

The Qsys address translation for the CRA port on the Avalon®-MM Hard IP for PCI Express® is incorrect when using VHDL as the generation language.This problem do…
www.altera.com/support/kdb/solutions/rd03062014_662.html - 2014-03-07

2014-03-07 0 0 Why do a small number of GND pins in the pin-out files of Stratix V, Arria V or Cyclone V devices have IO bank designations, whilst the rest do not?

GND pins that have bank designations in the pin-out files of Stratix® V, Arria® V or Cyclone® V devices are defined as Programming Ground pins. They should be treated like all…
www.altera.com/support/kdb/solutions/rd03072014_712.html - 2014-03-07

2014-03-04 0 0 How do I modify the UniPHY example driver to run continuously?

By default, the driver only runs once when you use the UniPHY example project. To make the driver run continuously, modify the driver file at the location "<variation_name&…
www.altera.com/support/kdb/solutions/rd09262013_405.html - 2014-03-04

2015-03-03 130000 13.0 0 In Qsys why are the Triple Speed Ethernet IP core clock names not described in the User Guide?

The Triple Speed Ethernet User Guide describes the clock names used in the MegaWizard® configuration. Qsys uses the following clock names: control_port_clock_…
www.altera.com/support/kdb/solutions/rd02102014_389.html - 2014-03-04

2014-03-11 130100 13.1 0 How do I simulate bi-directional signals with dynamic OCT with the Quartus® II software generated IBIS file ?

For software versions before Quartus II 13.1, the flow for simulating the input side of a bidirectional pin with dynamic on chip termination (OCT) is described in solution :http://…
www.altera.com/support/kdb/solutions/rd02142014_604.html - 2014-03-04

2014-03-04 0 0 When using the Stratix V Hard IP for PCI Express, why is the No Command Completed Support (bit 18) of the Slot Capability Register incorrectly set?

Due to a problem in the Stratix® V Hard IP for PCI® Express, this bit is incorrectly set.
www.altera.com/support/kdb/solutions/rd02212014_517.html - 2014-03-04

2014-03-03 100000 10.0 130100 13.1 Error: add_fileset_file: No such file C://qsys/_p0_sequencer_rom.hex

Due to a problem in the Quartus II software version 10.0 and later, the generation of a UniPHY core may error out with the above message. Error: add_fileset_file: No such file C:/…
www.altera.com/support/kdb/solutions/rd05242013_29.html - 2014-03-03

2014-07-04 0 0 Error : exception in thread java.lang.outOfMemoryError: java heap space

You may receive this error message when running System Console, due to the memory requirements of System Console exceeding the maximum heap size allocated to the Java VM. When…
www.altera.com/support/kdb/solutions/rd07022013_686.html - 2014-03-03

2014-02-28 0 0 Can the unencrypted peipheral image for use with CvP be used when the anti-tamper bit is set?

When using Configuration via Protocol (CvP) Initialization mode, the periphery image generated by the Convert Programming Files tool is unencrypted.When the anti-tamper bit is set …
www.altera.com/support/kdb/solutions/rd02242014_962.html - 2014-02-28

2014-02-28 100100 10.1 0 How do I force an update of the configuration RAM in a MAX II or MAX V device following programming using Real-time ISP?

When MAX® II and MAX V devices are reprogrammed using a JAM file where Real-Time ISP has been enabled, the configuration RAM of the MAX device is not updated following program…
www.altera.com/support/kdb/solutions/rd02122014_737.html - 2014-02-28

2014-02-28 0 0 Why does my third-party PCI Express BFM report an error for TX EIOS to Electrical Idle (TTX-IDLE-SET-TO-IDLE) timing violation?

When simulating the Altera® Hard IP for PCI Express® as endpoints with third-party BFMs, a simulation error may be reported for the time between sending out EIOS and entering Elect…
www.altera.com/support/kdb/solutions/rd12052013_482.html - 2014-02-28

2014-02-28 130100 13.1 0 ERROR: The attributes for bit 'rdynamic_sw' have illegal conflicting values

Due to a problem in the Stratix® V and Arria® V GZ HSSI PMA model, you may see this reported error when simulating the Hard IP for PCI Express® with the QuestaSim® or NC-Sim® …
www.altera.com/support/kdb/solutions/rd02282014_373.html - 2014-02-28