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Last Modified Version Found Version Found Version Fixed Version Fixed Document Title, Description, URL
2014-03-10 0 0 How do I use the Configuration via Protocol (CvP) Update with Revision Flow in a source controlled environment?

To use the CvP Update with Revision Flow in a source controlled environment with multiple team members: 1) Create an archive (QAR) of the base revision which include…
www.altera.com/support/kdb/solutions/rd03042014_441.html - 2014-03-10

2014-03-10 120100 12.1 0 Internal Error: Sub-system: FTITAN, File: /quartus/fitter/ftitan/ftitan_expert.cpp, Line: 4431

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error in designs that implement the altlvds_rx megafunction with the Use External PLL option…
www.altera.com/support/kdb/solutions/rd03052014_169.html - 2014-03-10

2014-04-20 110100 11.1 0 Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express?

The Qsys address translation for the CRA port on the Avalon®-MM Hard IP for PCI Express® is incorrect when using VHDL as the generation language.This problem do…
www.altera.com/support/kdb/solutions/rd03062014_662.html - 2014-03-07

2014-03-07 130100 13.1 0 Which device families have been removed from the Quartus II software starting with version 13.1?

The Quartus® II software version 13.1 no longer supports the following devices: MAX® 3000A, MAX 7000AE, MAX 7000S, MAX 7000B devices HardCopy II, HardCopy III, HardCopy IV (E/G…
www.altera.com/support/kdb/solutions/rd08252013_188.html - 2014-03-07

2014-03-07 0 0 Why do a small number of GND pins in the pin-out files of Stratix V, Arria V or Cyclone V devices have IO bank designations, whilst the rest do not?

GND pins that have bank designations in the pin-out files of Stratix® V, Arria® V or Cyclone® V devices are defined as Programming Ground pins. They should be treated like all…
www.altera.com/support/kdb/solutions/rd03072014_712.html - 2014-03-07

2014-03-04 130000 13.0 0 In Qsys why are the Triple Speed Ethernet IP core clock names not described in the User Guide?

The Triple Speed Ethernet User Guide describes the clock names used in the MegaWizard® configuration. Qsys uses the following clock names: control_port_clock_…
www.altera.com/support/kdb/solutions/rd02102014_389.html - 2014-03-04

2014-03-04 0 0 How do I modify the UniPHY example driver to run continuously?

By default, the driver only runs once when you use the UniPHY example project. To make the driver run continuously, modify the driver file at the location "<variation_name&…
www.altera.com/support/kdb/solutions/rd09262013_405.html - 2014-03-04

2014-03-11 130100 13.1 0 How do I simulate bi-directional signals with dynamic OCT with the Quartus® II software generated IBIS file ?

For software versions before Quartus II 13.1, the flow for simulating the input side of a bidirectional pin with dynamic on chip termination (OCT) is described in solution :http://…
www.altera.com/support/kdb/solutions/rd02142014_604.html - 2014-03-04

2014-03-04 0 0 When using the Stratix V Hard IP for PCI Express, why is the No Command Completed Support (bit 18) of the Slot Capability Register incorrectly set?

Due to a problem in the Stratix® V Hard IP for PCI® Express, this bit is incorrectly set.
www.altera.com/support/kdb/solutions/rd02212014_517.html - 2014-03-04

2014-07-04 0 0 Error : exception in thread java.lang.outOfMemoryError: java heap space

You may receive this error message when running System Console, due to the memory requirements of System Console exceeding the maximum heap size allocated to the Java VM. When…
www.altera.com/support/kdb/solutions/rd07022013_686.html - 2014-03-03

2014-03-03 100000 10.0 130100 13.1 Error: add_fileset_file: No such file C://qsys/_p0_sequencer_rom.hex

Due to a problem in the Quartus II software version 10.0 and later, the generation of a UniPHY core may error out with the above message. Error: add_fileset_file: No such file C:/…
www.altera.com/support/kdb/solutions/rd05242013_29.html - 2014-03-03

2014-02-28 0 0 Why does my third-party PCI Express BFM report an error for TX EIOS to Electrical Idle (TTX-IDLE-SET-TO-IDLE) timing violation?

When simulating the Altera® Hard IP for PCI Express® as endpoints with third-party BFMs, a simulation error may be reported for the time between sending out EIOS and entering Elect…
www.altera.com/support/kdb/solutions/rd12052013_482.html - 2014-02-28

2014-02-28 0 0 Can the unencrypted peipheral image for use with CvP be used when the anti-tamper bit is set?

When using Configuration via Protocol (CvP) Initialization mode, the periphery image generated by the Convert Programming Files tool is unencrypted.When the anti-tamper bit is set …
www.altera.com/support/kdb/solutions/rd02242014_962.html - 2014-02-28

2014-02-28 130100 13.1 0 ERROR: The attributes for bit 'rdynamic_sw' have illegal conflicting values

Due to a problem in the Stratix® V and Arria® V GZ HSSI PMA model, you may see this reported error when simulating the Hard IP for PCI Express® with the QuestaSim® or NC-Sim® …
www.altera.com/support/kdb/solutions/rd02282014_373.html - 2014-02-28

2014-02-28 100100 10.1 0 How do I force an update of the configuration RAM in a MAX II or MAX V device following programming using Real-time ISP?

When MAX® II and MAX V devices are reprogrammed using a JAM file where Real-Time ISP has been enabled, the configuration RAM of the MAX device is not updated following program…
www.altera.com/support/kdb/solutions/rd02122014_737.html - 2014-02-28

2014-02-27 130202 13.1
Arria 10
Edition
Update 2
0 Low Latency 40-100GbE IP Core PTP Module Causes Arria 10 IP Core to Malfunction

If your Low Latency 40-100GbE IP core variation targets an Arria 10 device, the PTP module causes the IP core to malfunction. This issue applies only to Low Latency 40-100GbE IP c…
www.altera.com/support/kdb/solutions/fb181330.html - 2014-02-28

2014-02-27 0 0 Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design. Rule C103: Gated clock does not feed at leas…
www.altera.com/support/kdb/solutions/rd02262014_41.html - 2014-02-27

2014-02-27 0 0 Rule C101: Gated clock should be implemented according to the Altera standard scheme

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design.  Rule C101: Gated clock should be imple…
www.altera.com/support/kdb/solutions/rd02262014_834.html - 2014-02-27

2014-02-27 120100 12.1 130000 13.0 Error (15700): Termination calibration block atom "|altera_mem_if_oct_stratixv:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout

You may see the following error when you compile your design when the "Rapid recompile" option is enabled. "Error (15700): Termination calibration block atom "<your_in…
www.altera.com/support/kdb/solutions/rd06052013_224.html - 2014-02-27

2014-02-27 0 0 Rule C105: Clock signal should be a global signal

You may see the following warnings when running the Design Assistant tool in Quartus II software on your compiled HPS design. Rule C105: Clock signal should be a global …
www.altera.com/support/kdb/solutions/rd02262014_16.html - 2014-02-27

2014-02-25 130000 13.0 130001 13.0 SP1 Functions Missing From Math Library

If you build a custom embedded math library with the -mhw-mulx switch, and no other options, the Software Build Tools generate an incomplete library. Some functions, such as pow()…
www.altera.com/support/kdb/solutions/fb127626.html - 2014-02-27

2014-02-26 0 0 What is the voltage diagram for the Schmitt trigger input standard and how does it relate to VIL and VIH specifications?

A  Schmitt trigger input standard allows input buffers to respond to slow input edge rates with a fast output edge rate. Most importantly, Schmitt triggers provide hysteresis …
www.altera.com/support/kdb/solutions/rd02112014_672.html - 2014-02-26

2014-02-24 0 0 Why does Quartus II re-run Analysis and Elaboration when opening the RTL viewer?

Due to a problem in Quartus® II Software, when you open netlist viewers from the Tasks pane, Analysis and Elaboration is run before opening the design in the RTL vie…
www.altera.com/support/kdb/solutions/rd02212014_350.html - 2014-02-24

2014-02-21 100000 10.0 110100 11.1 Incorrect information about Embedded C++

The Embedded Design Handbook contains the following incorrect statement about C++ support: The HAL supports only the standard Embedded C++ subset of the full C++ language. C++ pr…
www.altera.com/support/kdb/solutions/spr361482.html - 2014-02-24

2014-02-21 100000 10.0 0 BSP Not Updated for Memory Size Changes in SOPC Builder

If you change the size of a memory in SOPC Builder, and you have a BSP previously created with v9.1 or earlier, the memory region sizes are no longer correct. Regenerating the BSP…
www.altera.com/support/kdb/solutions/spr332637.html - 2014-02-24

2014-02-21 60100 6.1 70200 7.2 Hardware Accelerators Remain After Deleting the Software Project

If a system contains C2H accelerators, deleting the software project that defines the accelerators does not remove the accelerators from the hardware system, and the accelerator l…
www.altera.com/support/kdb/solutions/spr189600.html - 2014-02-24

2014-02-21 110002 11.0 SP2 120000 12.0 Nios II Application Properties Settings Not Saved

If the active configuration is not selected on the Nios II Application Properties page, you can not save the settings set in the Nios II Application Properties page. The active co…
www.altera.com/support/kdb/solutions/fb31565.html - 2014-02-24

2014-02-21 100000 10.0 100001 10.0 SP1 Error Building Imported Project: ‘target pattern contains no %’

If your application or library makefile uses an absolute path and is generated with the GCC 3 toolchain, and you import it to the version 10.0 Nios II SBT for Eclipse using the GC…
www.altera.com/support/kdb/solutions/spr341302.html - 2014-02-24

2014-02-24 0 0 Why does Qsys fail to generate any HDL files?

Qsys will fail to generate any HDL files if a Qsys component has a name that is illegal in either VHDL or Verilog HDL. For example in VHDL a name that ends in an underscore is ille…
www.altera.com/support/kdb/solutions/rd02212014_243.html - 2014-02-24

2014-02-21 120000 12.0 0 Is it possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix V, Arria V or Cyclone V devices?

No it is not possible to  dynamically enable or disable Global Clock (GCLK) or Regional clock  (RCLK) networks that drive fPLLs in Stratix® V, Arria® V or Cyclone® V devi…
www.altera.com/support/kdb/solutions/rd02122014_616.html - 2014-02-21

2014-02-19 110000 11.0 130100 13.1 Error 129001 Compiling HPS Component

When compiling an HPS design, you might see an error message similar to the following: Error (129001): Input port DATAIN on atom \ "hps_qsys:u0|hps_qsys_hps_0:hps_0|hps_qsys_hps_0…
www.altera.com/support/kdb/solutions/fb82901.html - 2014-02-20

2014-02-19 130001 13.0 SP1 0 SoC EDS Installation Error with Previous Version of DS-5

Before you install the SoC Embedded Design Suite (EDS), you must uninstall all previous versions of DS-5. If you do not uninstall a previous DS-5 version, the SoC EDS installation…
www.altera.com/support/kdb/solutions/fb128134.html - 2014-02-20

2014-02-19 120100 12.1 0 Bus Failure using FPGA-to-SDRAM Interface

When trying to access SDRAM through the SoC’s FPGA-to-SDRAM interface, your design might experience a bus failure, resulting in either of the following symptoms: The FPGA-to-SDRAM…
www.altera.com/support/kdb/solutions/fb110286.html - 2014-02-20

2014-02-19 130202 13.1
Arria 10
Edition
Update 2
0 Low Latency 40-100GbE IP Core Reserved Register Accesses Hang

If you attempt to access a reserved register in the Low Latency 40-100GbE IP core through its Avalon-MM control and status interface, the transaction might not complete. More prec…
www.altera.com/support/kdb/solutions/fb181384.html - 2014-02-20

2014-02-19 130000 13.0 130100 13.1 Segmentation Fault When Registering GPIO Interrupt Handler

In the Linux implementation included with the Golden System Reference Design, if you attempt to register an interrupt handler for a nonexistent GPIO device, you will see error mes…
www.altera.com/support/kdb/solutions/fb117780.html - 2014-02-20

2014-02-19 120100 12.1 130101 13.1
Update1
SoC HPS Interface to LPDDR2 is Unsupported

LPDDR2 memory is unsupported for the Arria V SoC and Cyclone V SoC in certain releases of the Quartus II software.
www.altera.com/support/kdb/solutions/fb154450.html - 2014-02-20

2014-02-19 130202 13.1
Arria 10
Edition
Update 2
0 Low Latency 40-100GbE IP Core VHDL Model Cannot Simulate Correctly

If you generate a VHDL model for a Low Latency 40-100GbE IP core, it cannot simulate correctly.
www.altera.com/support/kdb/solutions/fb181334.html - 2014-02-20

2014-02-19 130000 13.0 130001 13.0 SP1 SDRAM ECC Disabled in Preloader

Qsys cannot generate a DDR interface in the HPS component with ECC enabled. If you try to specify such an interface, the result is an interface with no ECC. Depending on the inter…
www.altera.com/support/kdb/solutions/fb108175.html - 2014-02-20

2014-02-19 120100 12.1 0 Debug APB Model Instance Does Not Exist in Testbench

When you simulate the HPS component, if the debug APB interface is enabled and you attempt to reference it in your testbench, you see an error message indicating that the debug AP…
www.altera.com/support/kdb/solutions/fb100506.html - 2014-02-20

2014-02-19 130000 13.0 130100 13.1 U-Boot Times Out During FPGA Programming

On the Cyclone V SoC HPS, U-Boot might time out without completing, and report an error code of -6, indicating that the FPGA control block cannot obtain valid data. This can happe…
www.altera.com/support/kdb/solutions/fb114045.html - 2014-02-20

2014-02-19 0 0 How can I choose my own reset pin location for npor when using the soft reset controller for the Hard IP for PCI Express?

To use your own reset pin location for npor first ensure that you are using the soft reset controller by checking that hip_hard_reset_hwtcl parameter is set to …
www.altera.com/support/kdb/solutions/rd02132014_196.html - 2014-02-19

2014-02-18 0 0 Why can’t I merge PLLs for two different instances of the ALTMEMPHY IP?

ALTMEMPHY calibration uses PLL reconfiguration to update PLL phases. Thus, dynamic PLL reconfiguration is required. Since each ALTMEMPHY interface must be calibrated separatel…
www.altera.com/support/kdb/solutions/rd04112013_81.html - 2014-02-18

2014-02-18 0 0 WARNING: Attempting to read from uninitialized location

You may experience the above warning when running a dual rank DDR3 simulation. This warning occurs during the memory initilialization and calibration process. Uninit…
www.altera.com/support/kdb/solutions/rd01082014_306.html - 2014-02-18

2014-03-04 130000 13.0 0 * Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v

You may see the above error when simulating your DDR3 UniPHY controller with ModelSim. The cause of the error is the ordering of the compilation libraries in the ModelSim vsim elab…
www.altera.com/support/kdb/solutions/rd01212014_488.html - 2014-02-18

2014-02-13 0 0 What are the minimum memory clock frequencies supported by the UniPHY External Memory Interface IP ?

The minimum frequencies are defined either by the relevant JEDEC® standard or by component features of the FPGA device used to implement the External Memory Interface IP. If too lo…
www.altera.com/support/kdb/solutions/rd01032014_294.html - 2014-02-13

2014-02-13 110000 11.0 0 How do I implement the half rate bridge option for connection to a full rate memory controller ?

While using the Quartus® II software  versions before 11.0, the half rate bridge option was a selectable parameter in the memory controller IP megawizard. While using&nbs…
www.altera.com/support/kdb/solutions/rd01062014_253.html - 2014-02-13

2014-02-13 0 0 How do I set the DDR3 UniPHY memory controller timing parameters from the External Memory vendor DDR3 datasheet ?

The External Memory Interface Handbook Volume 2, Section I, Chapter 9, "Implementing and Parameterizing Memory IP" has details on how to select the timing parameters but the d…
www.altera.com/support/kdb/solutions/rd01282014_876.html - 2014-02-13

2014-02-13 0 0 Can the address pins be swapped on my DDR2 or DDR3 UniPHY controller?

No, the address (mem_a) and bank address (mem_ba) signals are used for programming the mode registers in the DDR2 or DDR3 memory device during initialization. Swapping around …
www.altera.com/support/kdb/solutions/rd12182013_515.html - 2014-02-13

2014-09-01 0 0 Where can I find the pre-configuration and post-configuration BSDL file generation customizer for Stratix IV GX, Stratix IV GT, Stratix IV E, Arria II GX, and HardCopy® III devices?

For Stratix® IV GX, Stratix IV GT, Stratix IV E, Arria® II GX, and HardCopy® III devices the BSDL file pre-configuration and post-configuration generation is now generated and cust…
www.altera.com/support/kdb/solutions/rd10132010_113.html - 2014-02-12

2014-02-11 120100 12.1 130000 13.0 Invalid pin multiplexing configurations in HPS Qsys systems for Cyclone V SoC devices

If you create a hard processor system (HPS) in Qsys that targets a Cyclone V SoC device with the U19 package and a 484 pin count, the following peripheral pin multiplexing paramet…
www.altera.com/support/kdb/solutions/fb73715.html - 2014-02-11

2014-02-10 130100 13.1 0 Why does the Qsys interconnect has a buswidth mismatch on the burstcount signal?

Due to a problem in the Quartus® II software version 13.1, Qsys may incorrectly generate the bitwidth of burstcount signal when the Avalon-MM component uses the…
www.altera.com/support/kdb/solutions/rd02052014_584.html - 2014-02-10

2014-02-10 130100 13.1 0 Why does Design Assistant not report a rule violation when my design uses a PLL locked signal as an asynchronous reset signal?

Due to a problem in the Quartus® II software version 13.1 and earlier, Design Assistant does not report a rule violation when the locked signal of a PLL is connected directly to th…
www.altera.com/support/kdb/solutions/rd12042013_325.html - 2014-02-10

2014-02-10 120000 12.0 130000 13.0 How do I set a phase shift in degrees in the ALTPLL megafunction?

Due to a problem in the Quartus® II version 12.1 SP1 and earlier, you may see the phase shift is not applied in the ALTPLL megafunction when using the wizard. This problem occ…
www.altera.com/support/kdb/solutions/rd01122014_158.html - 2014-02-10

2014-02-13 0 0 What are the supported VCCIO and VCCPD voltage combinations for IO banks with LVDS inputs and/or outputs in Stratix V, Arria V and Cyclone V devices?

The following table illustrates supported VCCIO and VCCPD combinations for IO banks with LVDS inputs and/or outputs in Stratix®  V, Arria®  V and Cyclone®  V de…
www.altera.com/support/kdb/solutions/rd01312014_45.html - 2014-02-07

2014-02-07 0 0 What are the AC voltage levels that Quartus® II uses for UniPHY DDR3 and DDR3L tDS and tIS set up derating ?

The AC voltage levels depend on the value set in the Memory Parameters tab -> Memory Device Speed Grade. This speed grade and the AC voltage level shown below should be used to…
www.altera.com/support/kdb/solutions/rd01032014_56.html - 2014-02-07

2014-02-07 0 0 How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled?

When using ALTLVDS_RX in external PLL mode with DPA enabled in Quartus® II software versions 12.1 and later, you will receive an error in Analysis and Synthesis as shown below: Er…
www.altera.com/support/kdb/solutions/rd07192013_460.html - 2014-02-07

2014-02-07 0 0 What are the AC voltage levels that Quartus® II uses for DDR2 and LPDDR2 tDS and tIS set up derating ?

The AC voltage levels depend on the value set in the Memory Parameters tab -> Memory Device Speed Grade and are shown below. DDR2AC250 for speed grades 200.0  & 266.66…
www.altera.com/support/kdb/solutions/rd01032014_110.html - 2014-02-07

2014-08-19 130200 13.1
Arria 10
Edition
140000 14.0 Internal Error in Chip Planner/LogicLock during EMIF/PHYLite Compilation

If you use the Quartus II software Arria 10 Edition v13.1 to compile a design containing an external memory interface (EMIF) or PHYLite interface, the following error message migh…
www.altera.com/support/kdb/solutions/fb180575.html - 2014-02-07

2014-02-07 120101 12.1 SP1 130100 13.1 Timing Closure for Hard LPDDR2 Interfaces May Not be Robust in Cyclone V SoC Devices

This problem affects LPDDR2 products. Hard LPDDR2 interfaces targeting Cyclone V SoC devices may have difficulty achieving timing closure.
www.altera.com/support/kdb/solutions/fb98435.html - 2014-02-07

2014-02-06 130100 13.1 0 TOD Synchronizer Does Not Recognize Qsys-Generated Parameter Value

The TOD synchronizer in IEEE 1588v2 designs, using Triple Speed Ethernet, 10GbE MAC, or Low Latency Ethernet MAC, does not recognize certain Qsys-generated parameter values. When…
www.altera.com/support/kdb/solutions/fb166971.html - 2014-02-07

2014-02-07 130000 13.0 0 How should I place the QDRII/QDRII+ mem_cq and mem_cq_n pins in Arria V GX/GT/ST/SX devices?

From the device pinout file, there is only one pin location available for both mem_cq and mem_cq_n pins. For these Arria V devices complementary strobes are not supported, so …
www.altera.com/support/kdb/solutions/rd01232014_943.html - 2014-02-07

2014-02-07 130000 13.0 0 What is the difference between ‘Number of ranks per slot’ and ‘Number of chip-selects per device/DIMM’ for DDR3 RDIMM and LRDIMM?

For RDIMMs, a minimum of two chip select (CS) signals are required per RDIMM. This is necessary for RDIMM memory device programming. A single or dual rank RDIMM configuration …
www.altera.com/support/kdb/solutions/rd11122013_19.html - 2014-02-07

2014-02-06 0 0 How can I share On Chip Termination (OCT) calibration blocks if my design exceeds the maximum available?

All I/O banks with the same VCCIO can share one OCT calibration block. If your design exceeds the maximum number of available blocks, you can try and direct the Quartus® …
www.altera.com/support/kdb/solutions/rd01142014_259.html - 2014-02-06

2014-02-06 0 0 Does Altera comply with ISO 17025?

ISO 17025 is a standard for testing and calibration laboratories to set up and adhere to quality management systems. This standard does not apply to a semiconductor …
www.altera.com/support/kdb/solutions/rd01292014_726.html - 2014-02-06

2014-02-06 130100 13.1 0 Error (15629): Atom "comb~6" is dependent on unconnected input ports

You may see the error when instantiating the Altera® PLL Reconfiguration IP and enabling physical synthesis in the Quartus® II software.
www.altera.com/support/kdb/solutions/rd01212014_425.html - 2014-02-06

2014-02-05 0 0 Arria V GZ and Stratix V PCI Express Hard IP does not reject coefficient requests properly

If the Arria® V GZ or Stratix® V Hard IP for PCI Express® receives an illegal coefficient request from a link partner during either equalization phase 2 or 3, the IP…
www.altera.com/support/kdb/solutions/rd01302014_235.html - 2014-02-05

2014-02-05 130100 13.1 0 Cadence NCSim VHDL Compilation Error for Low Latency Ethernet 10G MAC

The Cadence NCSim VHDL simulator may cause compilation error for Low Latency Ethernet 10G MAC designs. The simulator library mapping in the Qsys .spd file shows the following erro…
www.altera.com/support/kdb/solutions/fb156992.html - 2014-02-05

2014-02-05 130100 13.1 0 Does the Hard IP for PCI Express for the Avalon-MM interface with DMA support out of order completions?

When the Hard IP for PCI Express® read DMA module receives out-of-order completions, the DMA can, in certain instances, flag the descriptor completion signal too early,&n…
www.altera.com/support/kdb/solutions/rd01302014_355.html - 2014-02-05

2014-02-05 110000 11.0 0 Preamble Pass Through Mode in 10-Gbps Ethernet MAC Does Not Meet Average IPG

10GbE MAC designs with the Enable preamble pass-through mode option turned on, the average inter-packet gap (IPG) is set to 16 instead of 12. Your designs will have lower throughp…
www.altera.com/support/kdb/solutions/fb176924.html - 2014-02-05

2014-02-05 130100 13.1 130100 13.1 Are there any problems with version 13.1 of the JNEye tool when modelling the receiver of Arria 10 GX/T devices?

Yes, due to a bug in Quartus® II software version 13.1 of the JNEye tool, you may see a problem with the modelling of the receivers in Arria® 10 GX/T devices. Modelling effectiv…
www.altera.com/support/kdb/solutions/rd01132014_397.html - 2014-02-05

2014-02-05 130100 13.1 0 Why do the Arria V GZ and Stratix V Hard IP for PCI Express exit hot reset early?

The Arria® V GZ and Stratix® V Hard IP for PCI Express® exit the LTSSM state Hot Reset immediately when the soft reset controller is being used. This causes the Hard IP to exit hot…
www.altera.com/support/kdb/solutions/rd01302014_386.html - 2014-02-05

2014-02-05 0 0 Does the Stratix V Hard IP for PCI Express support Gen3 Phase 2 and Phase 3 equalization in simulation?

The auto generated Stratix® V Hard IP for PCI Express® test bench Root Port bus functional model (BFM) bypasses Gen3 Phase 2 and Phase 3 Equalization. If using a third-p…
www.altera.com/support/kdb/solutions/rd12182013_166.html - 2014-02-05

2014-02-05 130000 13.0 0 How do I implement an 8b/10b Encoder-Decoder function?

In designs targeting Arria® II GZ, Arria V, Cyclone® V and Stratix® V, refer to the Advanced Synthesis Cookbook(PDF). For earlier device families use the Altera® 8B10B Encoder-Dec…
www.altera.com/support/kdb/solutions/rd12222013_503.html - 2014-02-05

2014-02-05 130200 13.1
Arria 10
Edition
0 Low Latency Ethernet 10G MAC Designs Using Arria 10 May Fail Timing

Large designs for Low Latency Ethernet 10G MAC using Arria 10 devices may fail setup timing.
www.altera.com/support/kdb/solutions/fb156881.html - 2014-02-05

2014-02-05 130100 13.1 0 Triple Speed Ethernet with 1000BASE-X and SGMII PCS Designs Receive Wrong Number of Preamble Bytes

Triple Speed Ethernet designs using SGMII PCS and 1000BASE-X protocol will receive wrong number of preamble bytes. For 1000BASE-X protocol, the encoding of Idle periods /I2/ is …
www.altera.com/support/kdb/solutions/fb162858.html - 2014-02-05

2014-02-05 120002 12.0 SP2 0 Why are all nodes ending with *sync*/*s0* incorrectly set to set_false_path in my project when using the CPRI MegaCore Function?

Starting from Quartus® II software version 12.0, when you generate a Common Public Radio Interface(CPRI) IP in your design, an “altera_cpri.sdc” file is generated au…
www.altera.com/support/kdb/solutions/rd12112013_829.html - 2014-02-05

2014-03-31 110100 11.1 0 Why is the address translation incorrect for the Serial RapidIO Avalon-MM ports?

The address translation to the Avalon®-MM slave ports on the Serial RapidIO® MegaCore will be incorrect when using VHDL generation within Qsys. Qsys always uses vectors with …
www.altera.com/support/kdb/solutions/rd02032014_394.html - 2014-02-05

2014-02-05 0 0 Does the Stratix V Hard IP for PCI Express support L0s and L1 states?

The Stratix® V Hard IP for PCI Express® does not support the L0s or L1 states.
www.altera.com/support/kdb/solutions/rd12172013_99.html - 2014-02-05

2014-02-05 130100 13.1 0 Pause and PFC Frames Still Generated When Transmit Path is Re-Enabled

The Low Latency Ethernet 10G MAC still services Pause and PFC frame requests after the transmit path is disabled and re-enabled. The requested Pause and PFC frames will be generat…
www.altera.com/support/kdb/solutions/fb154406.html - 2014-02-05

2014-02-05 0 0 Why do I get the following error messages when building the Linux open source Configuration via Protocol driver provided by Altera?

When building the Altera® example Linux Configuration via Protocol(CvP) driver the following error messages may occur: altera_cvp.c: In function ‘altera_cvp_wait_for_bit’:alt…
www.altera.com/support/kdb/solutions/rd02042014_622.html - 2014-02-05

2014-02-05 0 0 How do I disable the scrambler for PCI Express simulations?

To disable scrambling in PCI Express® simulations do the following: 1. Open <work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/altpcie_tbed_s…
www.altera.com/support/kdb/solutions/rd12172013_276.html - 2014-02-05

2014-02-03 0 0 How do I perform VHDL simulation for the altchip_id megafunction?

The Quartus® II software version 13.1 and earlier only has VHDL simulation support for the altchip_id megafunction for the Modelsim simulator.A Verilog HDL simulation model fo…
www.altera.com/support/kdb/solutions/rd01292014_9.html - 2014-02-03

2014-02-03 0 130100 13.1 Why does the Quartus II software ignore the power up values for my inferred RAM?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, the power up values of RAM inferred from raw logic may be incorrect. This problem is specific to cases w…
www.altera.com/support/kdb/solutions/rd01272014_323.html - 2014-02-03

2014-06-24 0 0 Internal Error: Sub-system: TIS, File: /quartus/tsm/tis/tis_physical_timing_stratixv_lab.cpp, Line: 161

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error during the fitter stage of compilation of your Arria® V, Cyclone® V or Strati…
www.altera.com/support/kdb/solutions/rd01292014_563.html - 2014-02-03

2014-02-03 0 0 Error (213035): Configuration device CFI_XXXMb/NAND_XXXMb is illegal -- specify a legal configuration device

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when using the quartus_cpf command to generate a Programmer Object File(.pof). This er…
www.altera.com/support/kdb/solutions/rd01302014_177.html - 2014-02-03

2014-01-31 0 0 Do LVDS receivers in Altera devices have on-chip dc-biasing resistors?

No, LVDS receivers in Altera® devices do not have on-chip dc-biasing resistors. If you are AC-coupling between an LVDS transmitter and an LVDS receiver in an Altera devic…
www.altera.com/support/kdb/solutions/rd01292014_586.html - 2014-01-31

2014-01-29 0 0 Why is there an increase in measured transceiver VCCL_GXB and VCCR_GXB current for a design compiled in Quartus II software versions 13.0, 13.0sp1. 13.1, and 13.1sp1 for Cyclone V, Arria V, and Stratix V transceiver devices?

Due to a bug in Quartus® II software versions 13.0, 13.0sp1. 13.1, and 13.1sp1 you may see an increase in measured transceiver VCCL_GXB and VCCR_GXB current for Cyclone® V, Arria® …
www.altera.com/support/kdb/solutions/rd01172014_109.html - 2014-01-29

2014-01-29 0 0 How do I confirm if a hardware failure on my design using an Arria V or Cyclone V Altera Development Kit is caused by any known device issue?

When operating designs with an Arria® V or Cyclone® V Altera Development Kit, you may observe failures which may be related to known device issues: Example: Phase Alignment …
www.altera.com/support/kdb/solutions/rd08292013_462.html - 2014-01-29

2014-01-29 0 0 How do I set the Marvel 88E1111 Ethernet PHY on the Stratix IV E FPGA Development Kit to GMII mode?

The hardware default setting of Stratix® IV E FPGA Development Kit is incorrectly set to Serial Gigabit Media Independent Interface (SGMII) mode. The Marvel 88E1111 Ethernet P…
www.altera.com/support/kdb/solutions/rd07082013_58.html - 2014-01-29

2014-01-29 130100 13.1 0 Possible Error When Simulating EMIF Designs in VHDL Using ModelSIM AE

This problem affects DDR2, DDR3, DDR4, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. If you are running the Quartus II software version 13.1 Arria 10 Edition or 13.1 Arria 10 E…
www.altera.com/support/kdb/solutions/fb170129.html - 2014-01-29

2014-01-28 0 0 Why does my Configuration via Protocol (CvP) design hang the PCIe bus after a CvP core fabric load?

The PCIe® bus can hang when using the CvP Update with Revision Flow if any partitions that are used for CvP become empty. The choices in the Quartus® II software when creating…
www.altera.com/support/kdb/solutions/rd08282013_832.html - 2014-01-28

2014-01-28 130100 13.1 0 Why does the Arria V VHDL PCI Express example design fail to simulate in the Synopsys VCS simultion tool?

Due to a problem in the Quartus® II Software version 13.1, errors may be seen when simulating the VHDL PCI Express Qsys example design using the autogenerated simulation scripts fo…
www.altera.com/support/kdb/solutions/rd01062014_191.html - 2014-01-28

2014-01-31 0 0 Do the LED_AN or LED_LINK signals of Triple Speed Ethernet IP Core reflect the copper link status when the IP Core is in SGMII MAC mode?

No, LED_AN / LED_LINK signals or AUTO_NEGOTIATION_COMPLETE / LINK_STATUS registers do not reflect the copper link status but SGMII link status.
www.altera.com/support/kdb/solutions/rd01262014_695.html - 2014-01-28

2014-01-28 130001 13.0 SP1 130100 13.1 Why do I get a fatal error when installing the Quartus II software version 13.0?

Due to a problem in the Quartus® II installer, you may see this error during installation.  
www.altera.com/support/kdb/solutions/rd08012013_389.html - 2014-01-28

2014-01-28 0 0 Why does my altsyncram based memory fail to initialize correctly when using the $readmemh function during simulation in the ModelSim simulator?

The readmemh function may fail to correctly initialize your altsyncram based memories during simulation if your top level testbench includes the initialization of any other si…
www.altera.com/support/kdb/solutions/rd01272014_86.html - 2014-01-28

2014-04-10 130100 13.1 0 Why am I still getting a Critical Warning about Simultaneous Switching Noise (SSN) and crosstalk even though I am following the SSN and crosstalk reduction guidelines?

Due to a problem in the Quartus® II software version 13.1 you may see the critical warning shown below, even though you have followed the Knowledge Base solution ID: rd1010201…
www.altera.com/support/kdb/solutions/rd01142014_182.html - 2014-01-27

2014-01-27 130100 13.1 0 Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_module_av.cpp, Line: 6805

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error if your design targets an Arria® V ES or Cyclone® V ES device and have Config…
www.altera.com/support/kdb/solutions/rd01272014_852.html - 2014-01-27

2014-01-27 120001 12.0 SP1 120100 12.1 Why are there two different setup relationships for timing paths to the altera_reserved_tdo port in the TimeQuest Timing Analyzer?

Due to a problem in the Quartus® II software version 12.0 SP1 and later, you may see two different relationships for timing paths to the altera_reserved_tdo port. This problem occu…
www.altera.com/support/kdb/solutions/rd12132013_236.html - 2014-01-27

2014-01-27 130100 13.1 0 Internal Error: Sub-system: NVD, File: /quartus/nlv/nvd/nvd_vdiimpl.cpp, Line: 2827

Due to a problem in the Quartus® II software version 13.1, you may see this error when launching the RTL viewer.
www.altera.com/support/kdb/solutions/rd01072014_681.html - 2014-01-27

2014-01-27 0 0 When does the Parallel Flash Loader (PFL) IP assert the flash_nreset signal?

The flash_nreset signal will be asserted in any of the following cases:(1) The device with the PFL design is powered up or configured.(2) The pfl_nreset in…
www.altera.com/support/kdb/solutions/rd01082014_747.html - 2014-01-27

2014-01-27 120100 12.1 0 Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_lut.cpp, Line: 464

Due to a problem in the Quartus® II software version 12.1 and later, you may see this internal error if Rapid Recompile is enabled while using the Incremental Compilation flow.
www.altera.com/support/kdb/solutions/rd12122013_270.html - 2014-01-27

2014-01-22 130001 13.0 SP1 0 No Cyclone V Device Support for 10-Gbps Ethernet MAC Version 13.1 SP1

10GbE MAC version 13.0 Service Pack 1 fails to meet timing when used with Cyclone V devices. This issue will be fixed in a future version of the 10GbE MAC MegaCore function.
www.altera.com/support/kdb/solutions/fb129479.html - 2014-01-24

2014-01-22 110100 11.1 0 PCI Testbench Uses Clear-Text VHDL and Verilog HDL Files

The PCI Compiler user guide wrongly states that the PCI testbench uses open source VHDL and Verilog HDL files. The PCI testbench uses clear-text files.
www.altera.com/support/kdb/solutions/fb116621.html - 2014-01-24

2014-01-22 130000 13.0 130001 13.0 SP1 Broadcast Deinterlacer Hardware Issues

The behaviour of the Broadcast Deinterlacer for cadenced input sequences and some progressive input sequences is 'undefined' when tested in hardware. This issue is fixed in versi…
www.altera.com/support/kdb/solutions/fb117815.html - 2014-01-24

2014-01-21 130000 13.0 130100 13.1 During simulation of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, l8_rx_fcs_error goes to 'X' when l8_rx_fcs_valid is '1'

Due to a problem in the 40- and 100-Gbps Ethernet MAC and PHY MegaCore® Function, l8_rx_fcs_error may go to “X” when l8_rx_fcs_valid goes to '1'.
www.altera.com/support/kdb/solutions/rd01082014_743.html - 2014-01-21

2014-01-21 130100 13.1 0 ncelab: *F,CUMSTS: Timescale directive missing on one or more modules

The Hard IP for PCI Express® auto-generated ncsim_setup.sh file is missing the timescale option.This problem can result in the Cadence® NC-Sim® simulator generating the follow…
www.altera.com/support/kdb/solutions/rd01052014_603.html - 2014-01-21

2014-01-21 120100 12.1 120101 12.1 SP1 Why does the Hard IP for PCI Express downtrain from Gen3 x8 to Gen3 x1 in simulation?

Due to a problem in the Quartus II software version 12.1 and earlier, the Stratix V Hard IP for PCI Express testbench downtrains from Gen3 x8 to Gen3 x1.This problem only affe…
www.altera.com/support/kdb/solutions/rd04272013_81.html - 2014-01-21

2014-01-21 0 0 Is there a Linux based PCIe demonstration application?

Application Note 456 uses a Windows-based PCIe demonstration application.
www.altera.com/support/kdb/solutions/rd01072014_495.html - 2014-01-21

2014-03-12 130100 13.1 0 Why does the Stratix V Hard IP for PCI Express fail to complete DMA transactions when using the Descriptor Control interface?

Due to a problem of Altera® Descriptor Controller IP, simultaneous DMA read and write operations with the Stratix® V Hard IP for PCI Express® for Avalon Memory-Mapped Int…
www.altera.com/support/kdb/solutions/rd01152014_734.html - 2014-01-21

2014-01-20 0 0 How do I fully remove Common Clock Path Pessimism for my edge aligned Source-Synchronous Output Interface?

Due to a problem in the Quartus® II software version 13.1 and earlier, the TimeQuest™ Timing Analyzer removes an insufficient amount of Common Clock Path Pessmism (CCPP) for edge a…
www.altera.com/support/kdb/solutions/rd01172014_985.html - 2014-01-20

2014-01-20 0 0 Internal Error: Sub-system: PUTIL, File: /quartus/power/putil/putil_cyclonev_hssi_info.cpp, Line: 610

Due to a problem in the Quartus® II software version 13.1, you may see this Internal Error while running the PowerPlay Power Analyzer.
www.altera.com/support/kdb/solutions/rd12312013_236.html - 2014-01-20

2014-02-19 130000 13.0 130001 13.0 SP1 bsp-generate-files Hangs when Generating Preloader on Windows

When you attempt to generate preloader files by running bsp-generate-files on a Windows command line, the tool might fail to generate the preloader files, and hang without exiting…
www.altera.com/support/kdb/solutions/fb115815.html - 2014-01-20

2014-01-20 120100 12.1 130100 13.1 Why does the Quartus II software give a fatal error after adding post-fit nodes in the SignalTap II Logic Analyzer?

Due to a problem in the Quartus® II software version 12.1 and later, you may see a fatal error after adding post-fit nodes to the SignalTap™ II Logic Analyser in your Str…
www.altera.com/support/kdb/solutions/rd11042013_965.html - 2014-01-20

2014-01-20 0 0 Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/arriav_arch/arriav_ram_netlist_routines.c, Line: 5520

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error when compiling a design that contains invalid physical width for WY…
www.altera.com/support/kdb/solutions/rd01152014_308.html - 2014-01-20

2014-05-02 130100 13.1 0 Is there SoC Hardware Library (HWLIB) support for QSPI, I2C, or ECC in SoC EDS 13.1?

Yes, SoC Hardware Library (HWLIB) APIs for QSPI, I2C, and ECC are available in SoC EDS version 13.1 via an update patch.
www.altera.com/support/kdb/solutions/rd01072014_376.html - 2014-01-20

2014-01-20 100000 10.0 0 How can I check the results of the RAM bit Reservation settings in Cyclone III designs?

To check the results of the RAM bit reservation settings in Cyclone® III designs, follow these steps: 1. Locate the RAM in the Resource Property Editor 2. Check the Connecti…
www.altera.com/support/kdb/solutions/rd11122013_785.html - 2014-01-20

2014-01-20 130100 13.1 0 Why do I see different timing in the Quartus II timing report and the TimeQuest timing analyzer?

Due to a problem in the Quartus® II software version 13.1, you may see the timing reported in the Quartus II software timing report is different from the timing…
www.altera.com/support/kdb/solutions/rd12022013_526.html - 2014-01-20

2014-01-20 130001 13.0 SP1 0 Why is the latency of my DSP block incorrect?

Due to a problem in the Quartus® II software version 13.0 SP1, you may see this problem if you synthesize your design using a 3rd party synthesis tool and use the DSP input registe…
www.altera.com/support/kdb/solutions/rd11012013_370.html - 2014-01-20

2014-01-15 130000 13.0 130100 13.1 Possible Read/Write Errors for DDR2 and DDR3 Hard Memory Controllers on Arria V and Cyclone V Devices at Low Vcc and Extreme Temperatures

This problem affects DDR2 and DDR3 products. The hard memory controller on Arria V GX, Arria V GT, Arria V SoC, Cyclone V GX, Cyclone V GT, and Cyclone V SoC devices might exhibit…
www.altera.com/support/kdb/solutions/fb153997.html - 2014-01-15

2014-08-26 130200 13.1
Arria 10
Edition
0 ALTFP_MATRIX and ALTFP_MATRIX_INV Megafunctions Do Not Work

In the Quartus II software v13.1 Arria 10 Edition, the ALTFP_MATRIX and ALTFP_MATRIX_INV Megafunctions do not work.
www.altera.com/support/kdb/solutions/fb154187.html - 2014-01-15

2014-01-14 0 0 Why does the DQS Delay reported in the TimeQuest Timing Analyzer for my altdq_dqs2 based design not match my requested phase shift?

Due to a problem in the Quartus® II software versions 13.1 and earlier, you may see an incorrect DQS phase shift reported in the TimeQuest™ Timing Analyzer when the clock used…
www.altera.com/support/kdb/solutions/rd12202013_243.html - 2014-01-14

2014-06-29 110100 11.1 0 How should I connect the MIF address bus between the reconfiguration controller and MIF ROM when word addressing is used in Stratix V GX devices?

MIF addressing is dependent upon the mode selected by bit 1 of address offset 0x1 detailed in the "Streamer Module Internal MIF Register Offsets" table of the PHY IP User…
www.altera.com/support/kdb/solutions/rd05212012_921.html - 2014-01-14

2014-01-13 0 0 Is there a guideline and checklist for debugging calibration failure

Yes. You can find the guideline and checklist located in the altera wiki page to help you to troubleshoot the calibration failure prior seeking assistance from factory application…
www.altera.com/support/kdb/solutions/rd11142011_834.html - 2014-01-13

2014-01-13 0 0 How do I improve timing when I process an Engineering Change Order (ECO)?

To improve timing when processing an ECO, ensure that you turn on the Optimize Timing for ECOs option (Settings > Fitter Settings > More Settings). You will get th…
www.altera.com/support/kdb/solutions/rd12042013_902.html - 2014-01-13

2014-01-13 0 0 Why does my Arria V design fail to route even though the device is not fully utilized?

Due to a problem in the Quartus® II software version 13.1 and earlier,  you may see that your Arria® V design fails to route when the device is not fully utilized. This p…
www.altera.com/support/kdb/solutions/rd12182013_569.html - 2014-01-13

2014-01-13 0 0 Internal Error: Sub-system: SGN, File: /quartus/synth/sgn/sgn_hier_connector.cpp, Line: 6144

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error if your SystemVerilog HDL design uses an unpacked array.
www.altera.com/support/kdb/solutions/rd01082014_490.html - 2014-01-13

2014-05-08 0 0 What is the HUB IP Configuration Register definition for the Virtual JTAG Megafunction?

The HUB IP Configuration Register definition for bits 7:0 is incorrect in table 9 of the Virtual JTAG Megafunction (sld_virtual_jtag) user guide (PDF).
www.altera.com/support/kdb/solutions/rd12312013_401.html - 2014-01-13

2014-01-13 130001 13.0 SP1 0 What is the maximum operating frequency for an external memory interface using the custom PHY?

The supported maximum global clock network frequency specification is 717 MHz for the fastest speed grade Stratix® V devices. Therefore, the maximum achievable frequence for&n…
www.altera.com/support/kdb/solutions/rd09302013_592.html - 2014-01-13

2014-01-13 130000 13.0 0 How do I select which modules I want to install from the command line?

Run the QuartusSetup-<version> file, for example QuartusSetup-13.0.0.152.exe or QuartusSetup-13.0.1.232.run with either the --enable-components switch or with the --disable-c…
www.altera.com/support/kdb/solutions/rd11012013_249.html - 2014-01-13

2014-01-13 0 0 Error (10430): VHDL Primary Unit Declaration error at <location>: primary unit "<name>" already exists in library "<name>"

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a design after you have generated your Qsys system. This error can occu…
www.altera.com/support/kdb/solutions/rd01072014_599.html - 2014-01-13

2014-01-13 120100 12.1 0 Is there an issue after hard memory controller design without specific INI file being programmed on Arria V ES device ?

Design using Arria V ES with hard memory controller compiles fine in quartus and you can program the board successfully. However the design will have problem to work prop…
www.altera.com/support/kdb/solutions/rd11112013_746.html - 2014-01-13

2014-03-31 130100 13.1 0 How do I regenerate the Stratix V IP for PCIe?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see the following error when you regenerate the IP for PCIe if you have opened the IP wizar…
www.altera.com/support/kdb/solutions/rd11252013_629.html - 2014-01-13

2014-01-13 0 0 Why does my Cyclone IV design have minimum pulse width violations related to the ALTINT_OSC megafunction?

Due to a problem in the Quartus® II software versions 13.1 and earlier, the ALTINT_OSC megafunction incorrectly allows the clock to be set at 100MHz in the MegaWizard™ Pl…
www.altera.com/support/kdb/solutions/rd12182013_337.html - 2014-01-13

2014-01-13 130100 13.1 0 Why does my RTL inferred RAM use more registers in the Quartus II software version 13.1 than in previous versions?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see a reduced number of registers when inferring a RAM from raw logic with non-zero power-up valu…
www.altera.com/support/kdb/solutions/rd01032014_990.html - 2014-01-13

2014-01-13 130100 13.1 0 Why does System Console fail to launch?

Due to a problem in the Quartus® II software version 13.1, system console may fail to launch. You may see one of the following error messages: Cannot load library: C:/alter…
www.altera.com/support/kdb/solutions/rd01072014_949.html - 2014-01-13

2014-01-13 0 0 Why does the TimeQuest Timing Analyzer only analyze the path from clock to output for the ALTDDIO_OUT megafunction?

The ALTDDIO_OUT megafunction uses a multiplexer where the select pin is driven with a clock signal, and the inputs are two registers with a 1 and 0 connected to the data pins. This…
www.altera.com/support/kdb/solutions/rd12102013_365.html - 2014-01-13

2014-01-30 0 0 How can I generate the Altera_PLL IP using a script or the command line interface?

In order to generate the Altera_PLL IP from the command line interface, the ip-generate utility can be used.  
www.altera.com/support/kdb/solutions/rd12182013_862.html - 2014-01-10

2014-05-08 0 0 How do I ensure low skew between the two pins that make up an emulated LVDS output on MAX V devices?

MAX® V devices support emulated LVDS outputs using the LVDS_E_3R I/O standard.  If the LVDS_E_3R I/O standard is applied to an output, the Quartus® II software will infer…
www.altera.com/support/kdb/solutions/rd12312013_237.html - 2014-01-10

2014-05-08 0 0 What is the part marking format for MAX V devices in the M100 package?

Due to the small size of the M100 package used by MAX® V devices, the top-side marking format is different to the standard BGA marking format.The following text is shown in the cen…
www.altera.com/support/kdb/solutions/rd12312013_718.html - 2014-01-10

2014-05-08 0 0 Why is the read data misaligned when using the ALTASMI_PARALLEL megafunction?

The dataout[] port from the ALTASMI_PARALLEL megafunction will be misaligned when reading from EPCQ devices if the number of dummy cycles set in the EPCQ non-volatile configuration…
www.altera.com/support/kdb/solutions/rd12312013_813.html - 2014-01-10

2014-01-10 130001 13.0 SP1 0 Error(177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL

You may get this error message if you assign your input clock signal to a dedicated clock pin location and make a global clock (GCLK) assignment to th…
www.altera.com/support/kdb/solutions/rd12162013_361.html - 2014-01-10

2014-01-09 0 0 How can I observe the PIPE interface signals of Stratix IV, Cyclone V and Arria V GX PCIe HIP using Signaltap II?

If you want to use Signaltap™ II to observe the PIPE interface signals of the Stratix® IV, Cyclone® V and Arria® V GX Hard IP for PCI Express®, please set test_in[11:8] of the PCIe…
www.altera.com/support/kdb/solutions/rd12122010_690.html - 2014-01-09

2014-01-09 130100 13.1 0 Can I create false path constraints for paths contained in the file altpcie_reconfig_driver.sv?

Yes, the three paths that you can false path in the Quartus II software version 13.1 are: adce_off_r adce_on_rr resetpld_sync_r The syntax below can be added into a…
www.altera.com/support/kdb/solutions/rd12162013_581.html - 2014-01-09

2014-02-21 0 0 Why does my Cadence NCSim Cyclone V PCIe simulation fail to complete, getting stuck at L0?

Due to an issue when simulating the Cyclone® V Hard IP for PCI Express® using Cadence® NCSim®  the simulation models must be updated.
www.altera.com/support/kdb/solutions/rd01072014_38.html - 2014-01-08

2014-01-08 130100 13.1 0 Why does my 40GBASE-KR4 MAC+ PHY example design fail to simulate in VCS?

When executing the run_vcs.sh simulation script generated by software version 13.1 of the 40GBASE-KR4 IP example design, the simulation will fail to compile, with th…
www.altera.com/support/kdb/solutions/rd12122013_551.html - 2014-01-08

2014-02-10 0 0 Why does my Cadence NCSIM Arria V PCIe simulation fail complete getting stuck in L0 and timeout?

Due to an issue when simulating the Arria® V Hard IP for PCI Express® using Cadence® NCSim®  the simulation models must be updated.
www.altera.com/support/kdb/solutions/rd12272013_814.html - 2014-01-08

2014-01-08 130100 13.1 0 Arria II GX CPRI IP Core Verilog HDL Variations at 4.915 Gbps Experience Data Transfer Failure on Antenna/Carrier Interface 17 in Simulation

If you generate a Verilog HDL model for a CPRI IP core variation with a data rate of 4.915 Gbps that targets an Arria II device and transfers data through 18 or more enabled anten…
www.altera.com/support/kdb/solutions/fb153722.html - 2014-01-08

2014-01-08 120000 12.0 0 Why does my Configuration via Protocol (CvP) design fail link training and not load the core image when I use a SOF from a Quartus II software version 13.0 or lower in CvP Initialization mode?

There is a known issue with the Convert Programming files conversion of the SRAM Object File (.sof) from Quartus® II software version 12.0 through 12.1sp1. The "Disable EPCS ID che…
www.altera.com/support/kdb/solutions/rd12132013_345.html - 2014-01-08

2014-07-04 130100 13.1 0 How can I enable timing support for HPS Loaner I/O in the Quartus II version 13.1?

Timing support for Loaner I/O is not available by default in the Quartus® II software version 13.1.  However a patch is available to add this functionality.
www.altera.com/support/kdb/solutions/rd01082014_212.html - 2014-01-08

2014-01-08 130100 13.1 0 Why do I get the following error message after updating IP Compiler for PCI Express to version 13.1?

The error is related to the used of fixed address translation table. Error (10198): Verilog HDL error at altpciexpav_stif_a2p_vartrans.v(121): part-select direction is opposite fr…
www.altera.com/support/kdb/solutions/rd11192013_370.html - 2014-01-08

2014-01-08 100000 10.0 0 Why does the Quartus II software crash during the EDA Netlist Writer for designs targeting Stratix V devices?

Due to a problem in the Quartus® II software version 13.1 and earlier, the EDA Netlist Writer may crash for designs targeting Arria® V, Cyclone® V and Stratix® V devices. This…
www.altera.com/support/kdb/solutions/rd04122013_471.html - 2014-01-08

2014-05-02 130100 13.1 0 Why do I see high memory usage during the FPGA compilation stage of OpenCL kernels?

Due to a problem in the OpenCL SDK version 13.1,  high memory usage may be seen during the FPGA compilation stage of OpenCL kernels.
www.altera.com/support/kdb/solutions/rd01072014_228.html - 2014-01-07

2012-06-26 110000 11.0 0 Gen3 Hard IP for PCI Express Erroneously Reports Malformed TLP Error

In rare circumstances a corrupted End of Data Stream (EDS) token may be reported as a Malformed TLP Error instead of a Framing Error. This problem only affects Stratix V and Arria…
www.altera.com/support/kdb/solutions/fb174378.html - 2014-01-07

2014-01-07 130000 13.0 0 ** Error: Unresolved defparam somewhere**

This error can occur when simulating Cyclone® V, Arria® V, and Stratix® V transceiver designs if the "altera_mf" library is placed before the "altera_mf_ver" library in your s…
www.altera.com/support/kdb/solutions/rd07172013_482.html - 2014-01-07

2014-01-07 120101 12.1 SP1 0 Why does the Quartus II software not create transceiver MIF files for Cyclone®, Arria® V, and Stratix® V devices with "advanced" or "inital" support?

Cyclone® V, Arria® V,and Stratix® V transceiver dynamic reconfiguration MIF files are only generated by the Quartus® II software for devices with full programming file support.
www.altera.com/support/kdb/solutions/rd07172013_727.html - 2014-01-07

2014-01-07 110000 11.0 0 Gen3 Hard IP for PCI Express Erroneously Reports Malformed TLP Error

In rare circumstances a corrupted End of Data Stream (EDS) token may be reported as a Malformed TLP Error instead of a Framing Error. This problem only affects Stratix V and Arria…
www.altera.com/support/kdb/solutions/fb174378.html - 2014-01-07

2014-01-06 0 0 Why does PCIe core transmit corrupted TLP when using Descriptor Data interface with MSI?

When using the PCIe® Incremental Compile Module(ICM) for the Descriptor/Data interface and a MSI transaction is sent while a TLP is being transmitted. This TLP will get corrupted o…
www.altera.com/support/kdb/solutions/rd07152011_543.html - 2014-01-06

2014-01-06 0 0 How do I run a Quartus II compilation on Windows and simulate the results on Linux?

If you use a Cadence or Synopsys simulation tool that only works on Linux, but do not want to install the Quartus® II software on your Linux machine, you can download and install…
www.altera.com/support/kdb/solutions/rd10082013_758.html - 2014-01-06

2014-01-06 120101 12.1 SP1 0 Why does the ALTECC decoder simulation have glitches when the parity bit is incorrect?

In the Quartus II software version 12.1 SP1 and later, on the output of the ALTECC decoder megafunction you may see glitches on the parity bit for all single-bit errors.&…
www.altera.com/support/kdb/solutions/rd04262013_335.html - 2014-01-06

2014-01-06 0 0 Why is the captured register waveform in SignalTap II Logic Analyzer inverted from the expected signal value?

You may see this behavior when you tap post-fit nodes in the SignalTap™ Logic Analyzer if the register has been implemented with NOT gate push back. This is the correct behavi…
www.altera.com/support/kdb/solutions/rd12092013_388.html - 2014-01-06

2014-01-06 120100 12.1 130000 13.0 Why is the resoure usage for mixed-width dual-port memory incorrectly reported?

Due to an problem in the Quartus® II software version 12.1, you may see the reported resource usage reported as twice the correct value. This problem does not …
www.altera.com/support/kdb/solutions/rd12122013_879.html - 2014-01-06

2014-01-06 130000 13.0 130001 13.0 SP1 Why does the SignalTap II Logic Analyzer trigger before the advanced trigger condition has been met?

Due to a problem in the Quartus® II software version 13.0, you may see the SignalTap™ II Logic Analyzer trigger immediately rather than when the advanced trigger condition is met. …
www.altera.com/support/kdb/solutions/rd11082013_189.html - 2014-01-06

2014-01-06 120100 12.1 0 Internal Error: Sub-system: BAL, File: /quartus/synth/bal/bal_ec_balancer.cpp, Line: 1463

Due to a problem in the Quartus® II software version 12.1 and later, you may see this error during Analysis & Synthesis when compiling designs with high RAM Block usage.…
www.altera.com/support/kdb/solutions/rd11072013_978.html - 2014-01-06

2014-01-06 0 0 Internal Error: Sub-system: FPP, File: /quartus/periph/fpp/fpp_cell.cpp, Line: 97

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this Internal Error in your Arria® V, Cyclone® V or Stratix® V design. This error occur…
www.altera.com/support/kdb/solutions/rd01032014_404.html - 2014-01-06

2014-05-19 120100 12.1 0 Why does the Quartus II programmer fail to program the Encyption Key Programming file?

Due to a problem in Quartus® II software, when you program the Encyption Key Programming (.ekp) file to Stratix® V, Arria® V or Cyclone® V device using Quartus II pr…
www.altera.com/support/kdb/solutions/rd11182013_331.html - 2014-01-06

2014-08-27 130001 13.0 SP1 0 Why do I see setup time violation on my I/O paths in the Quartus II software version 13.0 SP1?

You may see setup time violations on your I/O paths that use Hard Memory Controller (HMC) pins as I/O pins on Cyclone® V devices in the Quartus® …
www.altera.com/support/kdb/solutions/rd07302013_370.html - 2014-01-03

2013-12-26 110100 11.1 130100 13.1 CPRI MegaCore Function User Guide Missing Description of map_tx_start_mode field in CPRI_MAP_CONFIG register

The CPRI IP core CPRI_MAP_CONFIG register includes a map_tx_start_mode field at bit [5], starting in the CPRI IP core v11.1 release. However, the CPRI MegaCore Function User Guide…
www.altera.com/support/kdb/solutions/fb139293.html - 2013-12-27

2014-09-30 130100 13.1 0 Critical Warning (11887): The following pin <data pin> was placed in a reserved GND location. This may cause decreased performance for HMC. Altera recommends the pin location to be grounded

The following critical warning may appear after the fitter stage an unused data pin is placed on a reserved hard memory controller (HMC) GND pin. Cri…
www.altera.com/support/kdb/solutions/rd12222013_194.html - 2013-12-26

2013-12-26 0 0 Why does the DDR3 hard memory controller with UniPHY return invalid read data after the individual multi-port front end port is reset?

Due to a problem in the Quartus® II software, the DDR3 hard memory controller with UniPHY may return invalid read data after an individual multi-port front end (MPFE) port is reset…
www.altera.com/support/kdb/solutions/rd12192013_688.html - 2013-12-26

2013-12-20 0 0 Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device?

The center PLLs at the bottom only have access to one PHYCLK network in the Stratix® V device.
www.altera.com/support/kdb/solutions/rd12032013_135.html - 2013-12-20

2014-01-30 0 0 Critical Warning: DDR Timing requirements not met

When an external memory interface with UniPHY is implemented with manual board skew delays, the following warnings in the TimeQuest Timing Analyzer tool ma…
www.altera.com/support/kdb/solutions/rd08202013_747.html - 2013-12-20

2013-12-19 0 0 Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface?

The use of the afi_rlat signal is not supported for PHY-Only designs.
www.altera.com/support/kdb/solutions/rd10232013_167.html - 2013-12-19

2013-12-17 0 0 How does UniPHY-based DDR3 controller assert the refresh command for multiple chip selects interface?

The UniPHY-based memory controller does not issue the refresh command to all the chips of a multi-chip memory device or DIMM on the same clock cycle. For examp…
www.altera.com/support/kdb/solutions/rd12102013_134.html - 2013-12-17

2013-12-17 110100 11.1 0 Why does my PCIe link get stuck in the Detect state for Stratix IV and Arria II devices?

Due to an issue in the PCIe® Hard IP PMA, the link may get stuck in the Detect.Active state. This is due to the transceiver receiver detect logic not returning a PHYSTATUS pulse on…
www.altera.com/support/kdb/solutions/rd12112013_165.html - 2013-12-17

2013-12-17 0 0 Why does the error "relocation truncated to fit: R_NIOS2_CALL26" happen when Nios II code is placed in separate memory locations ?

This error happens when functions are located in a memory location more than 256MB apart from the main memory because the Nios II compiler uses the call instruction …
www.altera.com/support/kdb/solutions/rd09302013_702.html - 2013-12-17

2013-12-17 0 0 Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os

The following critical warning may appear when you use the ALTDDIO_IN megafunction to implement a non-memory interface in a Cyclone® III or Cyclone IV device and if the p…
www.altera.com/support/kdb/solutions/rd12102013_417.html - 2013-12-17

2013-12-17 0 0 Does the UniPHY-based DDR3 controller support dual-slot, quad-rank DDR3 RDIMM or UDIMM?

No, the UniPHY-based DDR3 controller does not support dual-slot, quad-rank DDR3 RDIMM or UDIMM. You can only generate and simulate this controller with this configuration.
www.altera.com/support/kdb/solutions/rd12102013_178.html - 2013-12-17

2013-12-17 0 0 Error (15700): Termination calibration block atom "<variation name>|altera_mem_if_oct_stratixv:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout

This error may appear in the Quartus® II software for your Qsys design if the On-Chip Termination (OCT) port is not exported.
www.altera.com/support/kdb/solutions/rd11262013_89.html - 2013-12-17

2013-12-16 120100 12.1 0 What is the purpose of the HPS SoC out1_n and out2_n signals?

When routing the output of the HPS UART to the FPGA, extra signals (out1_n and out2_n) are generated.  Due to a problem the functionality of out1_n and out2_n is not…
www.altera.com/support/kdb/solutions/rd08122013_191.html - 2013-12-16

2013-12-16 130000 13.0 0 Why does my Stratix IV Nios II design achieve a lower FMax in Quartus II 13.0 and later?

Due to a problem in the Quartus® II software version 13.0 and later,  Nios® II designs using DSP block multipliers targeting Stratix® III and IV devices may achieve a lower FM…
www.altera.com/support/kdb/solutions/rd11272013_702.html - 2013-12-16

2013-12-16 130100 13.1 130101 13.1
Update1
40GbE MAC and PHY IP Core MAC RX Statistics Registers Might Not Be Readable in 40GBASE-KR4 Variations

If you turn on statistics counters in your 40GBASE-KR4 40GbE IP core variation, and try to read an RX statistics counter, the read data might originate in a KR4-specific register …
www.altera.com/support/kdb/solutions/fb165476.html - 2013-12-16

2013-12-16 130100 13.1 0 How can I make the HPS SPI Master SS signal stay low for the whole transaction period?

Some SPI Slaves may require the SPI Master to hold the SS line low during the whole SPI transaction period. The HPS SPI Master can be configured to function in that manner wit…
www.altera.com/support/kdb/solutions/rd11212013_857.html - 2013-12-16

2013-12-16 130001 13.0 SP1 0 Where is the GNU documentation for Quartus 13.0 and 13.1

Due to a problem in the Quartus® II software version 13.0 and 13.1,  GNU documentation may not be present in the /nios2eds/documents/gnu-tools folder.
www.altera.com/support/kdb/solutions/rd12042013_964.html - 2013-12-16

2013-12-16 0 0 Why doesn't my HPS JTAG work, but my FPGA JTAG works?

The FPGA JTAG does not require an external clock source other than TCK clock. However the HPS JTAG requires an external clock source derived from the EOSC1 pin.  The…
www.altera.com/support/kdb/solutions/rd09182013_168.html - 2013-12-16

2013-12-19 130200 13.1
Arria 10
Edition
0 Design Examples Do Not Work in DSP Builder Standard Blockset

In DSP Builder standard blockset version 13.1 Arria 10 edition, only the Arria 10 design examples are available.
www.altera.com/support/kdb/solutions/fb148104.html - 2013-12-12

2013-12-12 130200 13.1
Arria 10
Edition
0 Error (13221): You must regenerate the IP component instantiated in file so that it targets the project device family;

The Quartus II software may generate the following error because MegaCore generated HDL does not target the same device family as you set for the project.Error (13221): You must r…
www.altera.com/support/kdb/solutions/fb169230.html - 2013-12-12

2014-09-02 0 0 Why does the MAX_ERROR LED illuminate red on my Altera development kit?

You may see that the MAX_ERROR LED illuminates red after you power up your Altera® development kit.  This is not board failure.  Many Altera development kits ha…
www.altera.com/support/kdb/solutions/rd12052013_88.html - 2013-12-12

2013-12-12 120002 12.0 SP2 120100 12.1 Why does my LVDS interface fail hold timing in Cyclone V 300GT devices in the Fast 0C timing corner?

Due to a problem in the Quartus® II software version 12.0 SP2 and earlier, you may see these timing violations in your Cyclone® V 300GT design. There is an problem with t…
www.altera.com/support/kdb/solutions/rd11192013_103.html - 2013-12-12

2013-12-13 130200 13.1
Arria 10
Edition
0 Error: Can't find dependent libraries sGeneric was not found inside Quartus. Please reinstall DSP Builder

When you run DSP Builder standard blockset version 13.1 and 13.1 Arria Edition, MATLAB may generate this error because of an DSP Builder installation problem.
www.altera.com/support/kdb/solutions/fb160990.html - 2013-12-12

2013-12-11 0 0 What does "GND+", "GND*" or "GXB_GND*" mean in the All Package Pins of fitter report?

You may see "GND+", "GND*" or "GXB_GND*" in the list of All Package Pins.  This list is shown in Fitter/Resource Section under Compilation Report or <design name>.f…
www.altera.com/support/kdb/solutions/rd12032013_227.html - 2013-12-11

2013-12-11 0 0 What is the default value for the block protection bits in serial and quad-serial configuration (EPCS and EPCQ) devices?

The block protection bits in serial configuration device (EPCS/EPCQ) are set to '0' by default. When any of the block protection bits are set to '1', the relevant ar…
www.altera.com/support/kdb/solutions/rd11282013_106.html - 2013-12-11

2013-12-11 0 0 Does the exposed pad of an EQFP package contribute to thermal dissipation?

The exposed pad on EQFP packages is a ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity only and not for…
www.altera.com/support/kdb/solutions/rd12042013_126.html - 2013-12-11

2013-12-11 0 130100 13.1 What is the correct C counter location assignment to be used when performing PLL Dynamic Phase Shifting with the Altera_PLL megafunction for 28nm devices?

In Quartus® II software versions  13.0sp1 and earlier, you must specify the C counter value (cnt_sel) based on the physical counter index, to select the counter to…
www.altera.com/support/kdb/solutions/rd08222013_973.html - 2013-12-11

2013-12-13 0 0 Why does the EDA netlist writer not create a valid netlist for gate-level simulation of the V-Series 28 nm Hard IP for PCI Express MegaCore Function?

The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.
www.altera.com/support/kdb/solutions/rd12102013_720.html - 2013-12-11

2013-12-11 0 0 Why are the fPLL C counters not updated correctly when dynamically reconfiguring an Altera_PLL using the Altera_PLL_Reconfig IP?

When using Altera_PLL_Reconfig, the translation logic from C logical counter to C physical counter may map incorrectly in the Quartus® II software versions 13.1 and earlier, causin…
www.altera.com/support/kdb/solutions/rd12162012_872.html - 2013-12-11

2013-12-11 0 0 How do I enable compression when generating programming files using the Convert Programming Files utility?

To enable compression when generating programming files using the Convert Programming Files utility in the Quartus® II software, follow the steps below : (1) After adding .so…
www.altera.com/support/kdb/solutions/rd12042013_483.html - 2013-12-11

2013-12-11 0 0 Can I assert the nConfig signal directly after terminating a Partial Reconfiguration process?

Yes, you can assert the nConfig signal directly after terminating a Partial Reconfiguration process.However you should ensure that you toggle PR_CLK for an additional 20 clock…
www.altera.com/support/kdb/solutions/rd12032013_239.html - 2013-12-11

2013-12-11 0 0 What is the write non-volatile configuration register (NVCR) cycle time specificatiion, for the quad-serial configuration devices (EPCQ)?

When you write to the NVCR, the device initiates a self-timed write NVCR cycle immediately after the nCS signal is driven high.  The self-timed write NVCR cycle ti…
www.altera.com/support/kdb/solutions/rd12052013_792.html - 2013-12-11

2013-12-11 130001 13.0 SP1 0 Why do I get illegal pin location assignment when I change the target device of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore example design?

When you change the target device of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore® example design, you must remove all the location assignments when prompted. However, you wi…
www.altera.com/support/kdb/solutions/rd12112013_418.html - 2013-12-11

2013-12-11 130100 13.1 0 Error (11924): Bank <bank number> has conflicting VCCIO settings

Due to a problem in the Quartus® II software version 13.1, you will see this error message when assigning a differential input or bidirectional pin in a bank where VCCIO is less…
www.altera.com/support/kdb/solutions/rd11172013_677.html - 2013-12-11

2013-12-11 0 0 Where can I find the BSDL file for a Cyclone III EP3C5U256C8N device?

The IEEE 1149.1 Compliant Boundary-Scan Description Language (BSDL) files for Cyclone® III devices are located on the Cyclone III Device Family BSDL Files webpage. For the Cyclone …
www.altera.com/support/kdb/solutions/rd04202011_536.html - 2013-12-11

2013-12-11 130001 13.0 SP1 0 What is the correct device part number used on the Arria V GX FPGA Starter Kit?

The correct device part number used on the Arria® V GX FPGA Starter kit is 5AGXFB3H4F35C4N This is incorrectly shown as 5AGXFB3H4F35C5N in the followi…
www.altera.com/support/kdb/solutions/rd10112013_488.html - 2013-12-11

2013-12-11 130000 13.0 0 Error (175001): Could not place path required to route a signal from PLD core to the I/O pin

You may see this error in the Quartus® II software versions 13.0 and 13.1 when using Arria® V or Cyclone® V SoC devices.  This error occurs when you use Hard Processor System …
www.altera.com/support/kdb/solutions/rd11182013_646.html - 2013-12-11

2014-02-10 130000 13.0 130100 13.1 Why do the write, sector_erase or bulk_erase operations of ALTASMI_PARALLEL perform incorrectly?

Due to a problem in Quartus® II software versions 13.0 and 13.0sp1, the ALTASMI_PARALLEL doesn't conduct the correct sequence when the write, sector_erase or bulk_erase&n…
www.altera.com/support/kdb/solutions/rd12092013_489.html - 2013-12-11

2013-12-11 130001 13.0 SP1 0 Why is the enable_dpa_fifo parameter set to "UNUSED" in the generated file even if you enabled the DPA feature in the ALTLVDS_RX MegaWizard

You will see following parameter definition in the MegaWizard™ generated file although you already enabled DPA feature in ALTLVDS_RX "ALTLVDS_RX_component.enable_dpa_fifo…
www.altera.com/support/kdb/solutions/rd11212013_158.html - 2013-12-11

2013-12-10 0 0 Why are there duplicates for the differential signals in the Pin Planner after I run the <variation name>_pin_assignments.tcl file?

Due to a problem in the Quartus® II software Pin Planner tool, some differential signals may appear twice in the Pin Planner for the UniPHY-based memory controller. For example, me…
www.altera.com/support/kdb/solutions/rd11192013_181.html - 2013-12-10

2013-12-10 0 0 How do I calculate the ECC for DDR3 UniPHY based controller?

The error correction code (ECC) calculation for UniPHY-based memory contollers is based on the Hamming Coding scheme. The Hamming Coding scheme derives the parity bits and app…
www.altera.com/support/kdb/solutions/rd04092013_850.html - 2013-12-10

2013-12-10 130001 13.0 SP1 0 Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY?

Due to a problem in the Quartus® II software version 13.1 and earlier, when using the hard memory controller with UniPHY, there might be a tWPRE timing violation when viewing the s…
www.altera.com/support/kdb/solutions/rd11282013_288.html - 2013-12-10

2013-12-10 130001 13.0 SP1 0 What is the maximum burst length for the hard memory controller?

The maximum burst length is 128 in the hard memory controller. If you require a wider width, it is recommended to use an adapter.
www.altera.com/support/kdb/solutions/rd12092013_826.html - 2013-12-10

2013-12-10 130100 13.1 0 Why is the "Additional CK/CK# phase" option grayed out inside the MegaWizard GUI for the Stratix V device?

The "Additional CK/CK# phase" option is grayed out in the MegaWizard™ GUI because custom phase shifts for the memory clock is not supported for that device and protocol. The Strati…
www.altera.com/support/kdb/solutions/rd10282013_814.html - 2013-12-10

2013-12-10 0 0 Critical Warning (308019): (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme.

When running the Design Assistant tool in the Quartus® II software, the following critical warning message may appear: Critical Warning (308019): (Critical) Rule C101: Gated clock…
www.altera.com/support/kdb/solutions/rd11202013_901.html - 2013-12-10

2013-12-10 130001 13.0 SP1 0 Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller?

When running an RTL simulation for the UniPHY-based hard memory controller in Arria® V or Cyclone® V device, you may find local_cal_success go high but local_init_done st…
www.altera.com/support/kdb/solutions/rd11242013_620.html - 2013-12-10

2013-12-09 0 0 How do I address hold time violations for paths where destination register is implemented inside a dedicated DSP block in Arria V devices?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see hold violations in Arria® V designs for paths where the source register is implemented using a st…
www.altera.com/support/kdb/solutions/rd12022013_628.html - 2013-12-09

2013-12-09 0 0 How do I report net delay violations?

To display net delay timing reports, run the report_net_delay command. The TimeQuest timing analyzer does not report net delay violations by default.  
www.altera.com/support/kdb/solutions/rd11152013_841.html - 2013-12-09

2013-12-09 0 0 Why do I see a Fatal Error in the Quartus II software after routing my Stratix III PLL output directly to a device output pin?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see a fatal error if you connect a Stratix® III PLL clock output directly to a device outpu…
www.altera.com/support/kdb/solutions/rd12022013_718.html - 2013-12-09

2013-12-09 0 0 Error:286034 Cannot find Memory Initialization File or Hexadecimal (Intel-Format) File db/<name>.hdl.mif

Due to a problem in the Quartus® II software version 13.1, you may see this error message when you compile a revision whose name is different than the project name.
www.altera.com/support/kdb/solutions/rd12052013_480.html - 2013-12-09

2013-12-09 130001 13.0 SP1 0 Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_power_region.cpp, Line: 2351

Due to a problem in the Quartus® II software version 13.0 SP1 and later, you may see this error if your design contains the following line in the Quartus II Settings File (.qs…
www.altera.com/support/kdb/solutions/rd10222013_699.html - 2013-12-09

2013-12-09 130100 13.1 0 Error (12921): Please run Analysis and Synthesis (quartus_map) without the --recompile option before requesting Rapid Recompile Analysis & Synthesis

You may see this error message if you run Rapid Recompile for unsupported device families. Currently Rapid Recompile only supports Stratix® V devices.
www.altera.com/support/kdb/solutions/rd12032013_538.html - 2013-12-09

2013-12-09 130000 13.0 0 Internal Error: Sub-system: HDB, File: /quartus/db/hdb/hdb_inst_name.cpp, Line: 1613

Due to a problem in the Quartus® II software version 13.0 and later, you may see this internal error during the Fitter if your design has location assignments f…
www.altera.com/support/kdb/solutions/rd11252013_357.html - 2013-12-09

2013-12-09 0 130100 13.1 Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_titan_atom_visitor_main.cpp, Line: 1966
Atom type not supported by PVA

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this Internal Error while running the PowerPlay Power Analyzer. 
www.altera.com/support/kdb/solutions/rd11172013_38.html - 2013-12-09

2013-12-04 130200 13.1
Arria 10
Edition
0 Riviera-PRO Crashes When Compiling Altera PHYLite for Memory Megafunction HDL File

If, in the Quartus II software version 13.1a10 or later, you created an Altera PHYLite for memory megafunction example design and perform simulation using Riviera-PRO 2013.06, the…
www.altera.com/support/kdb/solutions/fb148228.html - 2013-12-06

2013-12-06 130001 13.0 SP1 0 Why does PCI Express link training fail intermittently ?

Due to a bug, you may see link training failure with the Hard IP for PCI Express® IP Core due to the transmission of corrupted TS1s. The Hard IP core LTSSM state cycles between the…
www.altera.com/support/kdb/solutions/rd11192013_905.html - 2013-12-06

2013-12-05 100000 10.0 130100 13.1 Cyclone IV GX CPRI IP Cores at Data Rates Above 0.6144 Gbps Have Wrong TX Transceiver Clock Connection

In CPRI IP core variations that target a Cyclone IV GX device and that run at a CPRI line rate of 1.2288, 2.4576, or 3.072 Gbps, the TX transmitter reference clock input signal is…
www.altera.com/support/kdb/solutions/fb143483.html - 2013-12-05

2013-12-10 130001 13.0 SP1 130100 13.1 Issue with Configuration Space Bypass Mode Qsys Example Design for Arria V GZ Hard IP for PCI Express IP Core

The Configuration Space Bypass Mode Qsys example design for the Arria V GZ Hard IP for PCI Express IP does not work in the Quartus II 13.0 SP1 release. A required file, altera_pci…
www.altera.com/support/kdb/solutions/fb132607_a5gz.html - 2013-12-05

2013-12-05 110100 11.1 130001 13.0 SP1 CvP Update Not Available at Gen2 Rate for the Arria V Hard IP for PCI Express IP Core

You cannot use the Configuration via Protocol (CvP) update mode at the Gen2 data rate for the Arria VHard IP for PCI Express IP Core.
www.altera.com/support/kdb/solutions/fb125216.html - 2013-12-05

2013-12-04 120101 12.1 SP1 130100 13.1 Arria V GT CPRI IP Cores at Data Rate 9.8 Gbps Do Not Provide Transceiver Status on gxb_rx_pll_locked and gxb_rx_freqlocked Signals

In CPRI IP core variations that target an Arria V GT device and that run at a CPRI line rate of 9.8 Gbps, the transceiver status output signals gxb_rx_pll_locked and gxb_rx_freqlo…
www.altera.com/support/kdb/solutions/fb148889.html - 2013-12-05

2013-12-05 110100 11.1 130000 13.0 Cyclone V Hard IP for PCI Express IP Core May Fail Link Training

The Cyclone V Hard IP for PCI Express IP Core may fail link training and remain in the Detect.Quiet state. This failure is caused by an incomplete reset of the TX PMA which result…
www.altera.com/support/kdb/solutions/fb113954.html - 2013-12-05

2013-12-05 130000 13.0 130001 13.0 SP1 Gen2 Link Issues for Cyclone V Hard IP for PCI Express IP Core

Gen2 links experience a high error rate for the Cyclone V Hard IP for PCI Express IP Core.
www.altera.com/support/kdb/solutions/fb134347.html - 2013-12-05

2013-12-05 100100 10.1 130100 13.1 Configuration Via Protocol (CvP) Not Working for Arria V GZ Hard IP for PCI Express x2 Variants

Arria V GZ Hard IP for PCI Express variants using CvP and x2 configuration fail during link training initialization.
www.altera.com/support/kdb/solutions/fb99538.html - 2013-12-05

2013-12-05 130001 13.0 SP1 130100 13.1 Issue with Configuration Space Bypass Mode Qsys Example Design for Stratix V Hard IP for PCI Express IP Core

The Configuration Space Bypass Mode Qsys example design for the Stratix V Hard IP for PCI Express IP does not work in the Quartus II 13.0 SP1 release. A required file, altera_pcie…
www.altera.com/support/kdb/solutions/fb132607.html - 2013-12-05

2013-12-04 130100 13.1 0 Demonstration Testbench for Some CPRI IP Core Verilog HDL Variations Fails Simulation of HDLC Functionality

If you generate a Verilog HDL model for a CPRI IP core variation that has a data rate of 4.915 Gbps, 6.144 Gbps, or 9.8 Gbps and targets an Arria V GZ, Arria V GT, or Stratix V de…
www.altera.com/support/kdb/solutions/fb153794.html - 2013-12-05

2013-12-05 120101 12.1 SP1 130000 13.0 Link Training Failure in Arria V Avalon-MM Hard IP for PCI Express Due To Incorrect PMA Settings

Version 12.1 SP1 of the Quartus II software specifies incorrect values for many pre-emphasis and VOD settings, resulting in link training failures. This issue affects all Arria V …
www.altera.com/support/kdb/solutions/fb103502.html - 2013-12-05

2013-12-04 120100 12.1 0 Why do I experience intermittent link up problems when using the Stratix V or Arria V GZ Hard IP for PCI Express Gen 2 core?

There is an issue when using the Stratix® V or Arria V GZ Hard IP for PCI Express® IP core, where the link does not consistently come up.  This issue is seen when the cor…
www.altera.com/support/kdb/solutions/rd07232013_512.html - 2013-12-04

2013-12-03 130100 13.1 0 Arria V, Cyclone V, and Stratix V CPRI IP Core Autorate Negotiation Testbench Fails Simulation in the Synopsys VCS MX Simulator

CPRI IP core variations that target an Arria V, Cylcone V, or Stratix V device fail simulation with the autorate negotiation testbench in the Synopsys VCS MX simulator. Following …
www.altera.com/support/kdb/solutions/fb154656.html - 2013-12-04

2013-12-04 0 0 Why is my Avalon-MM mode PCI Express core not resetting my logic correctly?

When using the Avalon Memory  Mapped Interface version of the Hard IP for PCI® Express core, "reset_status" interface signal is "Active Low".NOTE: with Avalon Streaming I…
www.altera.com/support/kdb/solutions/rd11282013_15.html - 2013-12-04

2013-12-04 130102 13.1
Update2
0 Arria 10 Hard IP for PCI Express IP Core Support for x2 Variants

The Arria 10 Hard IP for PCI Express user guides indicate that x2 support is generally unavailable. However, x2 support is available for almost all configurations. The exception i…
www.altera.com/support/kdb/solutions/fb157200.html - 2013-12-04

2013-12-04 130100 13.1 0 CPRI IP Core Demonstration Testbench Does Not Support Aldec Riviera-PRO Simulator

The CPRI IP core demonstration testbench cannot simulate successfully with the Aldec Riviera-PRO simulator.
www.altera.com/support/kdb/solutions/fb158226.html - 2013-12-04

2013-12-04 130102 13.1
Update2
0 Arria 10 Gen3 x2 Example Design Simulation Issue

The Arria 10 Gen3 x2 example design might timeout when performing an MSI DMA Read and issue the following error message: INFO: 109129 ns TASK:chained_dma_test INFO: 109129 ns …
www.altera.com/support/kdb/solutions/fb157170.html - 2013-12-04

2013-12-04 0 0 Critical Warning: parameter 'invalid_code_flag_only' of instance '...|av_hssi_8g_rx_pcs_rbc' has illegal value '' assigned to it.

You may see the following synthesis message when implementing the Arria® V Hard IP for PCI® Express in Quartus® II software versions 13.1 and earlier. Info (10648): …
www.altera.com/support/kdb/solutions/rd12022013_509.html - 2013-12-04

2013-12-04 0 130100 13.1 Error (175001): Could not place Hard IP Error (10104): Unable to find a path between I/O pad and PINPERST port of PCI Express Hard IP.

Quartus® II software reports this fitter error when you make an incorrect nPERSTL* pin to PCI Express Hard IP location assignment in Cyclone® V devices.Pin nPERSTL0 is associa…
www.altera.com/support/kdb/solutions/rd12042013_909.html - 2013-12-04

2013-12-04 130001 13.0 SP1 130100 13.1 Example Design for Avalon-MM 256-Bit Hard IP for PCI Express Not Working

The example design for the Avalon-MM 256-Bit Hard IP for PCI Express does not work in simulation or hardware for 13.0 SP1.
www.altera.com/support/kdb/solutions/fb131587.html - 2013-12-04

2013-12-03 130200 13.1
Arria 10
Edition
0 50G Interlaken MegaCore Function User Guide Provides Insufficient Information to Connect Arria 10 TX PLL

According to the 50G Interlaken MegaCore Function User Guide, user logic should drive the tx_pll_locked input signal to an Arria 10 100G Interlaken IP core with the logical AND of…
www.altera.com/support/kdb/solutions/fb171345b.html - 2013-12-03

2013-12-03 130001 13.0 SP1 0 Error: Please specify correct phase shifts

You may encounter this error when instantiating the Altera_PLL megafunction with certain output clock phase shift settings. For example, an ALTLV…
www.altera.com/support/kdb/solutions/rd07042013_614.html - 2013-12-03

2013-12-03 130200 13.1
Arria 10
Edition
0 40-100GbE MAC and PHY IP Core Fails Attempted Update to Quartus II Software v13.1 Arria 10 Edition

Designs that contain a 40- and 100-Gbps Ethernet Mac and PHY IP core fail the IP upgrade process in the Quartus II software v13.1 Arria 10 Edition. This IP core does not support t…
www.altera.com/support/kdb/solutions/fb165629.html - 2013-12-03

2013-12-03 130200 13.1
Arria 10
Edition
0 100G Interlaken MegaCore Function User Guide Provides Insufficient Information to Connect Arria 10 TX PLL

According to the 100G Interlaken MegaCore Function User Guide, user logic should drive the tx_pll_locked input signal to an Arria 10 100G Interlaken IP core with the logical AND o…
www.altera.com/support/kdb/solutions/fb171345a.html - 2013-12-03

2013-12-03 0 0 Error: can't read "safebit": no such variable

You may get this error messages when executing the BSDL Customizer tcl files with unsupported devices. If you open the BSDL Customizer tcl files, the device string for newer d…
www.altera.com/support/kdb/solutions/rd07262011_217.html - 2013-12-03

2013-12-03 120100 12.1 130200 13.1
Arria 10
Edition
100G Interlaken MegaCore Function User Guide Erroneously Indicates MetaFrameLength Can Be Less Than 128 64-Bit Words

According to the 100G Interlaken MegaCore Function User Guide, the Meta frame length in words parameter can have a value of 64 8-byte words. However, this is incorrect. The minimu…
www.altera.com/support/kdb/solutions/fb166520a.html - 2013-12-03

2013-12-03 130000 13.0 130200 13.1
Arria 10
Edition
50G Interlaken MegaCore Function User Guide Erroneously Indicates MetaFrameLength Can Be Less Than 128 64-Bit Words

According to the 50G Interlaken MegaCore Function User Guide, the Meta frame length in words parameter can have a value of 64 8-byte words. However, this is incorrect. The minimum…
www.altera.com/support/kdb/solutions/fb166520b.html - 2013-12-03

2013-12-02 130000 13.0 0 Error: TB_Gen: More than one reset ports found

Due to a problem in Quartus® II software version 13.0 and later, you may see this error message when you generate a Qsys testbench. This error occurs if a Qsys component has an exp…
www.altera.com/support/kdb/solutions/rd11062013_652.html - 2013-12-02

2013-12-02 120000 12.0 0 Error (170025): Fitter requires that more entities of type <cell type> be placed in a region than are available in the region

Due to a problem is the Quartus® II software version 12.1 and later, you may see this error if the fitter has promoted a high fan-out clock to a regional clock instead of a gl…
www.altera.com/support/kdb/solutions/rd10302013_719.html - 2013-12-02

2013-12-02 120100 12.1 0 Error (175001): Could not place ATX PLL

Due to a problem in the Quartus® II software version 12.1 and later, you may see fitter problems placing the ATX PLL when migrating from earlier versions of the Quartus II sof…
www.altera.com/support/kdb/solutions/rd10222013_204.html - 2013-12-02

2013-12-02 130000 13.0 0 Internal Error: Sub-system: SEDQ, File: /quartus/sld/sedq/sedq_number.cpp, Line: 332

Due to a problem in the Quartus® II software version 13.0 and later, you may see this error when you add nodes to the Data tab of the SignalTap™ II Logic Analyzer. E…
www.altera.com/support/kdb/solutions/rd11142013_789.html - 2013-12-02

2013-12-02 0 0 (mgcld) UNSUPPORTED: "alteramtivsim" (PORT_AT_HOST_PLUS ) <port>@<server> (License server system does not support this feature.)

You may see this error when using ModelSim-Altera software if you have a corrupt license.
www.altera.com/support/kdb/solutions/rd11132013_584.html - 2013-12-02

2013-12-02 130001 13.0 SP1 130100 13.1 Failed to load Altera_PLL v13.0 Megawizard for Arria V GZ

Due to a problem in the Quartus® II software version 13.0 SP1, you may see this error when opened the Altera PLL and you have only installed the Arria® V GZ device library.
www.altera.com/support/kdb/solutions/rd10112013_834.html - 2013-12-02

2014-06-30 0 0 Why do I see increased low frequency jitter when using the ATX PLL of Stratix V or Arria V GZ transceiver devices?

Due to a problem in the Quartus® II software you may see increased low frequency jitter when using the ATX PLL of Stratix® V or Arria® V GZ transceiver devices. The Quartus II so…
www.altera.com/support/kdb/solutions/rd11112013_835.html - 2013-11-29

2013-11-29 0 0 How can I use the Altera Secure File Transfer System (SFTA) to upload and download files?

To securely transfer large files to and from Altera you must use the Altera Secure File Transfer System (SFTA). If you are a first time user or your SFTA account has become inacti…
www.altera.com/support/kdb/solutions/rd11192013_686.html - 2013-11-29

2013-11-27 130100 13.1 0 Incorrect Register Value After Tx/Rx Reset

Some of the Low Latency 10GbE MAC registers will have incorrect value after being reset with tx_rst_n or rx_rst_n.. This issue affects the following registers: 0x0FE-0x0FF: Tx Und…
www.altera.com/support/kdb/solutions/fb151913.html - 2013-11-28

2013-11-26 120100 12.1 130100 13.1 100G Interlaken IP Core itx_chan Signal Must Be Held Steady for the Duration of the Packet

User logic must hold the 100G Interlaken IP core itx_chan signal steady for the duration of the packet on the TX user data transfer interface, from the time user logic asserts the…
www.altera.com/support/kdb/solutions/fb142831a.html - 2013-11-27

2013-11-26 130000 13.0 130100 13.1 50G Interlaken IP Core itx_chan Signal Must Be Held Steady for the Duration of the Packet

User logic must hold the 50G Interlaken IP core itx_chan signal steady for the duration of the packet on the TX user data transfer interface, from the time user logic asserts the …
www.altera.com/support/kdb/solutions/fb142831b.html - 2013-11-27

2013-11-27 0 0 How do I generate Raw Programming Data (.rpd) files for EPCS or EPCQ configuration devices which only contain configuration data?

A .rpd file which is generated from a Programmer Object File (.pof) or JTAG Indirect Configuration file (.jic) is always the same size as the EPCS or EPCQ configuration device whic…
www.altera.com/support/kdb/solutions/rd11182013_802.html - 2013-11-27

2013-11-26 130000 13.0 130100 13.1 40-100GbE MAC and PHY IP Core MegaCore Function User Guide Lists Wrong Module Names in Resource Utilization Tables

In the 40- and 100-Gbps Ethernet Mac and PHY MegaCore Function User Guide, the resource utilization numbers for 40GbE variations appear correctly in the tables, but the module nam…
www.altera.com/support/kdb/solutions/fb153201.html - 2013-11-27

2013-11-27 130000 13.0 0 IP Compiler for PCI Express SDC Constraint Generates Warnings

The following SDC constraint in the automatically generated Synopsys Design Constraints (.sdc) file for the IP Compiler for PCI Express generates warning messages: set_clock_group…
www.altera.com/support/kdb/solutions/fb134563.html - 2013-11-27

2013-11-27 130001 13.0 SP1 0 What is the correct part number used on the Arria V FPGA Development Kit?

The correct device part number for the FPGA used on the  Arria® V FPGA Development kit  is a 5AGXFB3H6F40C5NES device. This is incorrectly shown as 5A…
www.altera.com/support/kdb/solutions/rd10112013_478.html - 2013-11-27

2013-11-27 0 0 What is the number of program/erase cycles for a serial configuration (EPCS) device or a quad-serial configuration (EPCQ) device?

The EPCS and EPCQ devices support more than 100,000 program/erase cycles per sector.
www.altera.com/support/kdb/solutions/rd10312013_646.html - 2013-11-27

2014-05-13 120100 12.1 0 Why is the Read Device Dummy Clock instruction unreliable when using the QUAD and DUAL IO options on the ALTASMI_PARALLEL megafunction?

When the  read_dummyclk input of the ALTASMI_PARALLEL megafunction is asserted, the megafunction performs a read of the non-volatile control register of the EPCQ configur…
www.altera.com/support/kdb/solutions/rd11192013_10.html - 2013-11-27

2013-11-27 130001 13.0 SP1 130100 13.1 Why does the Altera PLL fail to lock in simulation after installing the dp5 patch?

The Altera® PLL simulation model may fail to operate correctly and fail to assert the locked signal after installing the dp5 patch for version 13.0sp1 of the Quartus® II software.Y…
www.altera.com/support/kdb/solutions/rd11192013_957.html - 2013-11-27

2013-11-26 130000 13.0 130100 13.1 50G Interlaken MegaCore Function User Guide Erroneously Indicates BurstMax Can Have Value Greater Than 256 Bytes

According to the 50G Interlaken MegaCore Function User Guide, MaxBurst can have a value of 512 bytes. However, this is incorrect. The only values that MaxBurst can have in this IP…
www.altera.com/support/kdb/solutions/fb158022.html - 2013-11-27

2013-11-27 0 0 What is the data retention time for a serial configuration (EPCS) device or a quad-serial configuration (EPCQ) device?

The data retention time for an EPCS or EPCQ device is more than 20 years.
www.altera.com/support/kdb/solutions/rd10312013_363.html - 2013-11-27

2013-11-27 0 0 Why does the Quartus II programmer display a different flash memory name when performing an Auto Detect when multiple flash memory devices are connected to the parallel flash loader (PFL)?

When multiple flash memory devices are connected to the PFL in MAX® devices, the Quartus® II programmer displays a different flash memory name when performing Auto Detect. Thi…
www.altera.com/support/kdb/solutions/rd10282013_187.html - 2013-11-27

2013-11-26 130100 13.1 0 40-100GbE MAC and PHY IP Core remote_fault_status and local_fault_status Signals Are Not Visible at Top Level in MAC-Only Variations

In MAC-only variations of the 40- and 100-Gbps Ethernet Mac and PHY MegaCore function, the remote_fault_status and local_fault_status signals are not visible in the top-level inte…
www.altera.com/support/kdb/solutions/fb154869.html - 2013-11-27

2013-11-27 100000 10.0 0 IP Compiler for PCI Express User Guide is Missing Description of lane_act[3:0] Signal

The IP Compiler for PCI Express User Guide does not describe the lane_act[3:0] signal. The following information is missing from the user guide: Lane active mode: This output sign…
www.altera.com/support/kdb/solutions/fb134541.html - 2013-11-27

2013-11-25 120100 12.1 0 Port 0 Control 2 CSR Data Rate Support and Enable Fields All Have the Value of 1

The _GB_SUPPORT and _GB_ENABLE fields of the Port 0 Control 2 CSR (offset 0x154) are set by default to the value of 1. However, these fields should only be set to the value of 1 f…
www.altera.com/support/kdb/solutions/fb156607.html - 2013-11-26

2013-11-26 130000 13.0 0 Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File hps_AC_ROM.hex

This critical warning may be displayed by the Quartus® II software for designs targeting SOC devices. The warning can safely be ignored as this file is not required by t…
www.altera.com/support/kdb/solutions/rd11252013_188.html - 2013-11-26

2013-11-26 120100 12.1 0 RapidIO II IP Core Has Wrong Default TX VOD Setting in Arria V and Cyclone V devices

The RapidIO II IP core does not set the transceiver TX VOD value correctly in Arria V GX, Arria V GT, and Cyclone V devices. The default value violates the RapidIO specification. …
www.altera.com/support/kdb/solutions/fb163810.html - 2013-11-26

2013-11-26 110000 11.0 0 RapidIO IP Core Has Wrong Default TX VOD Setting in Arria V and Cyclone V Devices

The RapidIO IP core does not set the transceiver TX VOD value correctly in Arria V (GX, GT, SX, and ST) and Cyclone V devices. The default value violates the RapidIO specification…
www.altera.com/support/kdb/solutions/fb162180.html - 2013-11-26

2013-11-26 0 0 Why does my USB debug Master not work in System console on the Cyclone V GX FPGA development kit

Due to a problem on the Cyclone® V GX FPGA Development Kit, when using the USB Debug Master core in Qsys, System console does not discover the master device when you…
www.altera.com/support/kdb/solutions/rd03202013_599.html - 2013-11-26

2013-11-25 120100 12.1 0 RapidIO II IP Core Does Not Declare Illegal Transaction Decode for MAINTENANCE Read Response With More Than 32 Bits of Payload

When the RapidIO II IP core receives a MAINTENANCE Read response with more than 32 bits of payload, the RapidIO II IP core MAINTENANCE module should declare an Illegal Transaction…
www.altera.com/support/kdb/solutions/fb169828.html - 2013-11-26

2013-11-26 130000 13.0 0 Why is clCreateSubBuffer defined in the Altera DSK for OpenCL cl.h but not in ateracl.lib

clCreateSubBuffer creates a buffer object from an existing buffer object, and it is defined in the Open CL specification 1-2.   Altera SDK for Open CL™ supports only the …
www.altera.com/support/kdb/solutions/rd11192013_30.html - 2013-11-26

2013-11-26 0 0 How do stop all warnings being seen as errors in DS-5?

If you remove –Werror complier option from Makefile, warnings will not be flagged as errors. 
www.altera.com/support/kdb/solutions/rd11182013_597.html - 2013-11-26

2013-12-02 130100 13.1 0 Possible Timing Failure on Designs Targeting Arria V and Cyclone V Devices

This problem affects DDR2, DDR3, and LPDDR2 SDRAM Controllers with UniPHY. DDR2, DDR3, and LPDDR2 soft interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience …
www.altera.com/support/kdb/solutions/fb165855.html - 2013-11-26

2013-11-25 120100 12.1 130100 13.1 Control of RapidIO II IP Core EF_PTR Fields is Incorrect

The RapidIO II MegaCore Function User Guide states that the Extended features pointer parameter in the RapidIO II parameter editor controls the final EF_PTR in the chain of pointe…
www.altera.com/support/kdb/solutions/fb85398.html - 2013-11-26

2013-11-25 120100 12.1 130100 13.1 RapidIO II IP Core Does Not Support VHDL Models

The RapidIO II IP core does not support VHDL models. If you generate a RapidIO II IP core in VHDL, it cannot compile successfully. The RapidIO II MegaCore Function User Guide clai…
www.altera.com/support/kdb/solutions/fb79178.html - 2013-11-26

2013-11-25 120100 12.1 0 RapidIO II IP Core link-response Timeout Behavior Does Not Match Documentation

According to the RapidIO II MegaCore Function User Guide, after the RapidIO II IP core sends a link-request, if it times out waiting for a link-response, it sends another link-req…
www.altera.com/support/kdb/solutions/fb160419.html - 2013-11-26

2013-11-26 130001 13.0 SP1 0 Why are the Memory preset settings missing in the Cyclone® V HPS Qsys GUI component?

Due to a problem in the Quartus® II software version 13.0 sp1, the memory presets setting are no longer available from the Qsys Hardware Processor System MegaWizard GUI in the…
www.altera.com/support/kdb/solutions/rd08122013_723.html - 2013-11-26

2013-11-26 130000 13.0 0 Why are the Altera OpenCL SDK definitions num_vector_lanes and num_copies not in the 13.0sp1 documentation?

The num_vector_lanes and num_copies definitions have changed name to more intuitive names num_simd_work_items num_compute_units  
www.altera.com/support/kdb/solutions/rd11192013_138.html - 2013-11-26

2013-11-26 120100 12.1 130001 13.0 SP1 Why can't my own coefficient be used by the FIR compiler GUI?

The documentation for the FIR Compiler II  GUI  in the Quartus® II software version 12.1 - 13.0, incorrectly describes the file format for the input coefficient…
www.altera.com/support/kdb/solutions/rd08122013_194.html - 2013-11-26

2013-11-25 130000 13.0 0 Long Term CK Jitter Exceeds Spec in HPS Memory Interface in Arria V and Cyclone V Devices

This problem affects DDR2, DDR3, and LPDDR2 products. DDR2, DDR3, and LPDDR2 interfaces using the HPS memory interface on Arria V or Cyclone V devices, produce a long term CK jitt…
www.altera.com/support/kdb/solutions/fb167412.html - 2013-11-25

2013-12-02 130100 13.1 0 Migrating UniPHY IP from 13.0 SP1 DP5 to 13.1 Resets GUI to Default Values

This problem affects DDR2, DDR3, LPDDR2, QDR II, RLDRAM II, and RLDRAM 3 UniPHY-based products. When a top-level EMIF wrapper generated in the Quartus II software version 13.0 SP1…
www.altera.com/support/kdb/solutions/fb168318.html - 2013-11-25

2013-11-27 130000 13.0 0 Recovery Timing Violation

When you compile your designs with the Serial Digital Interface (SDI) II MegaCore function, you may encounter recovery timing violation. This violation is caused by the reset cont…
www.altera.com/support/kdb/solutions/fb147290.html - 2013-11-20

2013-11-27 120100 12.1 130100 13.1 When Asserted, reg_burst_count Fails to Perform Burst Transaction

When asserted, the reg_burst_count signal fails to perform a burst transaction in designs using Audio Embed, Audio Extract, Clocked Audio Input, or Clocked Audio Output IPs.
www.altera.com/support/kdb/solutions/fb156550.html - 2013-11-20

2013-11-27 110000 11.0 120000 12.0 FIR Coefficient Reload May Get Delayed

FIR Compiler II intermittently inserts unnecessary delay registers between a coefficient storage register and the multiplier that uses that coefficient. This issue may cause the …
www.altera.com/support/kdb/solutions/fb46001.html - 2013-11-20

2013-11-27 130001 13.0 SP1 0 Cannot Reopen SDI II Wrapper File in MegaWizard

The MegaWizard Plug-In Manager does not recognize the Serial Digital Interface (SDI) II top level wrapper file when you choose Edit an existing custom megafunction variation. The …
www.altera.com/support/kdb/solutions/fb160625.html - 2013-11-20

2013-11-27 130000 13.0 0 Half Duplex Operation on 10/100M Ethernet MAC Not Supported

The Triple Speed Ethernet designs that turn on the Enable MAC 10/100 half duplex support option do not enable the half duplex operation. The user interface may allow you to turn o…
www.altera.com/support/kdb/solutions/fb163263.html - 2013-11-20

2013-11-27 120100 12.1 130100 13.1 Inaccurate Receiver Video Format Detection for SDI Rx Protocol Only Instance

When you select SDI Rx protocol only instance, the reported receiver video format always defaults to the PAL (1/1.000) value. For example, rx_video_format value is 0x27 for both 1…
www.altera.com/support/kdb/solutions/fb158752.html - 2013-11-20

2013-11-27 130000 13.0 0 GXB 0 ppm Warning for SerialLite II Designs with Custom PHY

The Quartus II software will show the following warning for designs that use more than 1 channel between the SerialLite II MegaCore function and the Custom PHY IP during integrati…
www.altera.com/support/kdb/solutions/fb94561.html - 2013-11-20

2014-06-30 0 0 Critical Warning (184043): Fitter was unable to find transceiver reconfiguration controllers

You may see this Quartus® II critical warning if you turn off the PROJECT_SHOW_ENTITY_NAME setting and your Stratix® V, Arria® V, or Cyclone® V design includes transceivers. The P…
www.altera.com/support/kdb/solutions/rd10292013_663.html - 2013-11-19

2013-11-19 130100 13.1 0 RapidIO IP Core Hangs After Receiving MAINTENANCE Read Response With DONE Status but No Payload

When the RapidIO IP core receives a MAINTENANCE read response with DONE status but without a payload, the IP core should indicate an error. However, the IP core hangs. Refer also …
www.altera.com/support/kdb/solutions/fb167940.html - 2013-11-19

2013-11-19 130100 13.1 0 RapidIO IP Core Does Not Return ERROR Response Packet to MAINTENANCE Request with Illegal Size

When the RapidIO IP core receives a MAINTENANCE request with an illegal size (rdsize not equal to 4’b1000 for a MAINTENANCE read request, or wrsize not equal to 4’b1000 for a MAIN…
www.altera.com/support/kdb/solutions/fb167941.html - 2013-11-19

2013-11-19 110000 11.0 130100 13.1 RapidIO IP Core Qsys Design Example Simulation Warning

When you simulate the RapidIO Qsys design example, warning messages display. These messages complain of a missing rio_sys_onchip_memory2_0.hex file.
www.altera.com/support/kdb/solutions/fb101308.html - 2013-11-19

2013-11-19 90100 9.1 0 Wrong Default Transceiver Equalization Setting in RapidIO IP Core in Some Device Families

The default value for the transceiver equalization setting in a RapidIO IP core should be the Low setting. The default Low setting supports adjustment upwards as you encounter sig…
www.altera.com/support/kdb/solutions/fb52169.html - 2013-11-19

2013-11-19 0 0 How do I calculate DFE power consumption using the Quartus II Power Play Power Analyzer (PPPA) and Early Power Estimator (EPE) for Stratix V and Arria V GZ devices?

Due to a limitation of the Quartus® II software version 13.1 and earlier, the Power Play Power Analyzer (PPPA) tool will not include Decision Feedback Equalizer (DFE) power consump…
www.altera.com/support/kdb/solutions/rd11182013_585.html - 2013-11-19

2013-11-19 110001 11.0 SP1 130100 13.1 RapidIO IP Core 5.0 Gbaud Variations Do Not Handle Out-of-Order Response Packets Properly

When a RapidIO IP core variation at 5.0 Gbaud receives out of order read responses on the RapidIO link, the IP core sends the wrong payload data on the I/O Avalon-MM slave interfa…
www.altera.com/support/kdb/solutions/fb133567.html - 2013-11-19

2013-11-19 120100 12.1 130100 13.1 RapidIO IP Core Qsys Design Example Cannot Simulate with -novopt Flag Set

If you turn on the -novopt flag in the ModelSim simulator, the RapidIO Qsys design example fails while loading in the simulator.
www.altera.com/support/kdb/solutions/fb101226.html - 2013-11-19

2013-11-19 0 0 Critical Warning: PLL clock *|divclk not driven by a dedicated clock pin or neighboring PLL source.

You may see the above critical warning when the reference clock to a UniPHY-based memory controller is sourced from a global clock routing resource. The global routing resource wil…
www.altera.com/support/kdb/solutions/rd11042013_699.html - 2013-11-19

2013-11-18 130000 13.0 0 What timing constraints are used by the Design Assistant?

The Quartus® II Design Assistant (DA) does not use any constraints from the Synopsys Design Constraints (.sdc) file. During processing you may see the following messages: Inf…
www.altera.com/support/kdb/solutions/rd11062013_975.html - 2013-11-18

2013-11-18 0 0 Why does my qsys-script command fail?
Error: invalid command name "< command name >"

qsys-script command fails if you do not include a package version. When running a qsys-script command you must perform one of the following actions: Specify the package v…
www.altera.com/support/kdb/solutions/rd10282013_107.html - 2013-11-18

2013-11-18 130000 13.0 130100 13.1 How do I list the IPs requiring upgrade using the command line?

The Quartus® II Help version 13.0 for ip_upgrade incorrectly displays: quartus_sh --ip_upgrade -list_ips
www.altera.com/support/kdb/solutions/rd11052013_522.html - 2013-11-18

2013-11-18 130000 13.0 130100 13.1 Why does the generation of the altsyncram IP from the command line fail?

Command line generation of the altsyncram IP component is not supported in the Quartus® II software version 13.0 and later. The chapter Command Line Scripting (PDF) in t…
www.altera.com/support/kdb/solutions/rd10312013_616.html - 2013-11-18

2013-11-18 120100 12.1 0 Error (184057): Fitter cannot read the .mif db/<name>.mif

Due to a problem in the Quartus® II Software version 12.1 and later, you may see this error message when you have multiple revisions in your design. The Quartus II software in…
www.altera.com/support/kdb/solutions/rd11012013_123.html - 2013-11-18

2013-11-18 110000 11.0 0 Which protocols are supported by Quartus II Floating License Server?

The Quartus® II software version 11.0 and later, uses the 10.x FLEXlm license manager. This software uses only the TCP/IP protocol. 
www.altera.com/support/kdb/solutions/rd11152013_923.html - 2013-11-18

2013-11-15 130000 13.0 0 Why does my register view stop responding in DS-5 when I use a peripheral map?

If the register view in Arm DS-5 Altera Edition is left open viewing the content of registers located within the FPGA fabric when a debugging session is closed,  the register …
www.altera.com/support/kdb/solutions/rd11122013_210.html - 2013-11-15

2013-11-15 120000 12.0 120100 12.1 Prefitter Not Instantiating io_clock_divider and DQSLB when DQSLB has No Associated EMIF Pins

This problem affects QDR II, and RLDRAM II products. For designs with x18 or x36 DQ groups, it is possible that the data pins do not require I/Os in all the DQ groups. When this h…
www.altera.com/support/kdb/solutions/fb79326.html - 2013-11-15

2013-11-15 130000 13.0 0 What is the size of the instruction cache on the HPS DMA Contoller in Cyclone V and Arria V SOC devices?

The instruction cache size of the ARM DMA-330  IP on Cyclone® and Arria® V series SOC devices is 512 bytes. The cache line size is 8 words (4 bytes each), resulting in a line…
www.altera.com/support/kdb/solutions/rd11122013_771.html - 2013-11-15

2013-11-15 130000 13.0 0 Error _mm_interconnect_0_addr_router.sv(196): (vlog-2730) Undefined variable: 'write_transaction'

Due to a problem in the Quartus® II software version 13.0 and later, a Qsys system that contains an AXI Default Slave but no AXI Slave will not compile and simulate correctly.…
www.altera.com/support/kdb/solutions/rd10312013_789.html - 2013-11-15

2013-11-20 130100 13.1 0 Mentor Graphics AXI Verification IP AE in the Quartus II 13.1 release does not support QuestaSim 10.2b for windows

Mentor Graphics® AXI3™/AXI4™ Verification IP Suite Altera® Edition that is released with Quartus® II 13.1 will not work with QuestaSim® 10.2b for windows.
www.altera.com/support/kdb/solutions/rd10302013_617.html - 2013-11-15

2013-11-15 0 0 Nios® II Boot to from EPCQ or EPCS in Quartus® II 13.0

The flow to configure Nios® II to boot from EPCS /EPCQ, generate required programming files, and program development kits can be complex.    Also due to some problem…
www.altera.com/support/kdb/solutions/rd11122013_865.html - 2013-11-15

2013-11-26 0 0 Why do I see random read errors when using the ALTDQ_DQS2 megafunction?

Due to a problem in the ALTDQ_DQS2 megafunction in the Quartus® II software, when doing PVT testing, a glitch may occur at the output of the DQS logic block which may cause ra…
www.altera.com/support/kdb/solutions/rd10232013_290.html - 2013-11-15

2014-06-30 130100 13.1 0 Why does sof2flash, elf2flash,elf2hex and bin2flash fail when run on a Windows PC?

Due to a problem in the Quartus II software® version 13.1,  some of the NIOS® II EDS utilities may fail with no error output or messages when run on a Windows PC. The af…
www.altera.com/support/kdb/solutions/rd11112013_614.html - 2013-11-15

2013-11-14 0 0 Is a board trace model required for UniPHY-based Controller?

No, board trace models are not needed for UniPHY-based controllers.
www.altera.com/support/kdb/solutions/rd08212012_926.html - 2013-11-14

2013-11-14 110100 11.1 120100 12.1 Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals?

Due to a problem in the Quartus® II software version 11.1 and later, the DDR3 UniPHY-based memory controllers with the efficiency monitor enabled incorrectly use the Aval…
www.altera.com/support/kdb/solutions/rd08302012_420.html - 2013-11-14

2013-11-14 110100 11.1 0 Why is the efficiency of the Cyclone V and Arria V hard memory controller lower than expected for single port designs?

The Multi-Port Front End (MPFE) which is used with the Hard Memory Controller for Arria® V and Cyclone® V devices contains an arbiter which enables load balancing across multiple p…
www.altera.com/support/kdb/solutions/rd10302012_952.html - 2013-11-14

2013-11-13 0 0 Does the Altera JRunner software support programming of CPLDs?

No, the Altera® JRunner software is developed to configure Altera FPGA devices in JTAG mode for embedded configurations. The Altera JRunner software does not support prog…
www.altera.com/support/kdb/solutions/rd10302013_701.html - 2013-11-13

2013-11-13 0 0 What is the top side marking format for Altera devices?

The top side marking format for current Altera® devices is shown in the diagrams below for ball-grid array (BGA) and non-BGA devices.  For more details, refer to  ADV0012…
www.altera.com/support/kdb/solutions/rd10292013_192.html - 2013-11-13

2014-03-04 0 0 Can I reduce the current on VCC_AUX pins (ICC_AUX) by toggle rates or resource usage?

No, the current on VCC_AUX pins (ICC_AUX) is not directly affected by toggle rates or resource usage.  The current on VCC_AUX pins (ICC_AUX) depends o…
www.altera.com/support/kdb/solutions/rd10302013_62.html - 2013-11-13

2013-11-12 120100 12.1 0 L2 Cache Controller Revision Incorrectly Listed as r3p2

The Cortex-A9 Microprocessor Unit Subsystem chapter in Volume 3: Hard Processor System Technical Reference Manual of the Arria V Device Handbook and the Cyclone V Device Handbook …
www.altera.com/support/kdb/solutions/fb162407.html - 2013-11-13

2013-11-13 130001 13.0 SP1 130100 13.1 How do I set the paramter FAST_SIMULATION of my 40- and 100-Gbps Ethernet MAC and PHY in VHDL?

In Quartus® II software version v13.0SP1 and earlier you must manually modify the IP libraries of the 40- and 100-Gbps Ethernet MAC and PHY IP Core to set the parameter FAST_SIMULA…
www.altera.com/support/kdb/solutions/rd10212013_745.html - 2013-11-13

2014-04-13 0 0 How do I reduce the percentage of crosstalk and SSN towards differential pins in Cyclone V devices?

The attached document will describe how to reduce the percentage (%) of crosstalk and percentage (%) of Simultaneous Switching Noise (SSN) towards differential pins in the Quartus®…
www.altera.com/support/kdb/solutions/rd10102013_979.html - 2013-11-13

2013-11-13 130000 13.0 130100 13.1 Why have unused ports appeared on the Triple Speed Ethenet (TSE) IP in Quartus II software version 13.0?

Due to an issue the following unused ports have incorrectly appeared on the TSE IP in Quartus® II software version 13.0: magic_sleep_n, magic_wakeup, xoff_gen, xon_gen In Qu…
www.altera.com/support/kdb/solutions/rd11072013_288.html - 2013-11-13

2013-11-12 120101 12.1 SP1 130000 13.0 Why Nios II Sof2flash failed to generate flash file for Cyclone II?

Due to a problem in the Quartus® II software version 12.1SP1,  the NIOS® II sof2flash utility is not able to generate a flash file from a Cyclone® II .SOF file.…
www.altera.com/support/kdb/solutions/rd11072013_929.html - 2013-11-12

2013-11-12 130000 13.0 0 Critical Warning (18061): Ignored Power-Up Level option on the following registers

This warning message may be generated for designs using the Serial Digital Interface (SDI) MegaCore® Function software version 13.0 or 13.1. Critical Warning (18061): Ignored…
www.altera.com/support/kdb/solutions/rd11072013_196.html - 2013-11-12

2013-11-27 120100 12.1 130100 13.1 Incorrect Clock Connections for Avalon-ST Receive and Transmit Interface

The Avalon Streaming (Avalon-ST) receive source gets wrongly connected to the transmit clock and the Avalon-ST transmit sink gets wrongly connected to the receive clock. However,…
www.altera.com/support/kdb/solutions/fb142588.html - 2013-11-12

2013-11-12 0 0 What are the definitions of the SPI signals routed from Hard Processor Subsystem (HPS) block to FPGA in Cyclone V SoC and Arria V SoC devices?

Current documentation does not define all the SPI signals routed from HPS block to the FPGA block within Cyclone® V SoC and Arria® V SoC devices.  
www.altera.com/support/kdb/solutions/rd07162013_171.html - 2013-11-12

2013-11-11 110100 11.1 0 Why is tRCD larger than expected with my DDR3 UniPHY controller?

You may see a larger than expected tRCD delay in DDR3 UniPHY quarter-rate memory controllers because the transactions are generated by the controller clock which is running at…
www.altera.com/support/kdb/solutions/rd06122013_805.html - 2013-11-11

2013-11-11 120100 12.1 0 Why doesn't read data return as expected from an Avalon-MM slave ?

Due to a problem in the Quartus® II software version 12.1 and earlier, read data may not return as expected when the Avalon-MM master's data port bit width is wider than …
www.altera.com/support/kdb/solutions/rd01082013_685.html - 2013-11-11

2013-11-11 130100 13.1 0 Why is the Netlist Viewer not updated after the design has been modified and recompiled?

Due to a problem in the Quartus® II software version 13.1 and later, the Netlist Viewer may not be updated after a design is modified and recompiled. This problem may occur when th…
www.altera.com/support/kdb/solutions/rd10062013_288.html - 2013-11-11

2013-11-11 130000 13.0 0 How do I upgrade my LPM, RAM, or ROM megafunctions?

Due to a problem in the Quartus® II software version 13.0 and later, you cannot use the Upgrade IP Components feature to upgrade LPM, RAM, or ROM megafunctions.
www.altera.com/support/kdb/solutions/rd08202013_503.html - 2013-11-11

2013-11-11 130000 13.0 0 Why does Quartus II report that no devices are installed despite installing them?

Due to a problem in the Quartus® II software version 13.0, you may see the following message during installation if your license is not valid or no longer under main…
www.altera.com/support/kdb/solutions/rd07282013_809.html - 2013-11-11

2013-11-07 130000 13.0 0 Bootloader Fails to Run with UART0 Disabled

In v13.1, even if UART0 is disabled in the HPS component, the preloader generator turns on spl.performance.SERIAL_SUPPORT (UART0 serial I/O support). In v13.0, even if UART0 is di…
www.altera.com/support/kdb/solutions/fb155746.html - 2013-11-07

2014-02-25 130000 13.0 130100 13.1 TCP DSTREAM Connection Fails with Trace Enabled

If you try to start a DS-5 debug configuration that connects to the target using DSTREAM over Ethernet, and the 4 GB DSTREAM trace buffer is enabled, the connection fails. You see…
www.altera.com/support/kdb/solutions/fb96231.html - 2013-11-07

2014-01-06 130100 13.1 0 Nios II GNU toolchain upgrade from GCC 4.1.2 to GCC 4.7.3

In ACDS version 13.1, the Nios® II GNU toolchain is upgraded from GCC 4.1.2 to GCC 4.7.3. Users upgrading to the new toolchain need to take note of the following changes liste…
www.altera.com/support/kdb/solutions/rd10302013_291.html - 2013-11-05

2013-11-05 110000 11.0 0 Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands?

The High Performance Controller II (HPCII) used by the DDR2 UniPHY and ALTMEMPHY cores issues back to back read/write commands on every other controller clock cycle (afi_…
www.altera.com/support/kdb/solutions/rd02142012_914.html - 2013-11-05

2013-11-07 130100 13.1 0 Bonding Does Not Work for Multiple MPFE Ports in Hard Memory Controller

This problem affects DDR2, DDR3, and LPDDR2 products. In Arria V and Cyclone V devices, you can bond two hard memory controllers to increase their bandwidth. To use bonding, you m…
www.altera.com/support/kdb/solutions/fb165793.html - 2013-11-05

2013-12-13 130100 13.1 0 Internal Exception Error During Elaboration with NCSim

This problem affects designs that contain a Reed-Solomon II decoder. when you elaborate your design in Cadence NcSim, you may receive a elaboration error.
www.altera.com/support/kdb/solutions/fb146729.html - 2013-11-05

2013-11-05 0 0 Error (181011): Incompatible on-chip termination settings detected for pins in the DQS group fed by DQS I/O pin "<QK clock pin>". All pins in group must use the same OCT control block.

Due to a problem in the Quartus® II software, this error may appear when instantiating multiple RLDRAM 3 UniPHY interfaces in the design. Quartus II software assigns the incorrect …
www.altera.com/support/kdb/solutions/rd05172013_989.html - 2013-11-05

2013-11-05 110001 11.0 SP1 0 Does Quartus II software support x36 QDRII/II+ SRAM emulation mode in Stratix V devices?

The x36 QDR II/II+ SRAM emulation mode is not supported for Stratix® V devices.
www.altera.com/support/kdb/solutions/rd11152011_5.html - 2013-11-05

2013-11-04 0 0 Internal Error: Sub-system: PJC, File: /quartus/sys/pjc/pjc_new_tcl.cpp, Line: 18954
acf_manager->load_side_revision_if_needed( revision_name.c_str()) == ACF_REVISION_MANAGER::LEGAL

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may this error when running the Clean Project utility from the Project menu. If you have project revi…
www.altera.com/support/kdb/solutions/rd08282013_208.html - 2013-11-04

2013-11-01 130100 13.1 0 x8 and x16 HPS Designs not Supported on Arria V and Cyclone V Devices

This problem affects DDR2 and DDR3, and LPDDR2 products. On Arria V and Cyclone V devices, x8 and x16 HPS designs are not supported.
www.altera.com/support/kdb/solutions/fb164231.html - 2013-11-04

2013-11-01 130100 13.1 0 EMIF Generation for Arria V or Cyclone V Devices Requires Stratix V Device Database to be Installed

This problem affects DDR2, DDR3, LPDDR2 and RLDRAM II products. When generating an external memory interface for an Arria V or Cyclone V device, the generation process may fail to…
www.altera.com/support/kdb/solutions/fb157149.html - 2013-11-04

2013-11-01 130100 13.1 0 IP Generation Fails When Both Efficiency Monitor and Ping Pong PHY Enabled

This problem affects DDR2, DDR3, LPDDR2, RLDRAM II and RLDRAM 3 products. IP generation fails when you attempt to instantiate your UniPHY-based external memory interface IP with b…
www.altera.com/support/kdb/solutions/fb158297.html - 2013-11-04

2013-11-04 0 0 Why is input data lost when using the Avalon ST channel multiplexer?

Due to a problem in the Avalon® Streaming Channel Multiplexer component available in Qsys, data may be lost from the input port while the ready input of the output port is dea…
www.altera.com/support/kdb/solutions/rd09232013_431.html - 2013-11-04

2013-11-04 130000 13.0 130100 13.1 Is vertical migration supported in Cyclone V SoC devices?

Yes, vertical migration is supported in the U672 packages of Cyclone® V SE and SX devices. Prior to the following patch, however, vertical migration between these devices…
www.altera.com/support/kdb/solutions/rd08272013_16.html - 2013-11-04

2013-11-04 130000 13.0 130001 13.0 SP1 ECC Not Enabled in Cyclone V SoC HPS Devices

This problem affects DDR2, DDR3, and LPDDR2 products. For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, interface widths of 24 (16 plus ECC) and 40 (32 plus …
www.altera.com/support/kdb/solutions/fb108775.html - 2013-11-04

2013-11-01 130100 13.1 0 Group Mask Settings in EMIF Debug Toolkit Not Applied During Recalibration

This problem affects DDR2, DDR3, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. For any UniPHY-based external memory interface IP generated in the Quartus II software version 13…
www.altera.com/support/kdb/solutions/fb153524.html - 2013-11-04

2013-11-01 130100 13.1 0 Possible Simulation Failure in Skip Calibration Mode

This problem affects DDR2, DDR3, and LPDDR2 products. Arria V or Cyclone V external memory interfaces that use the hard memory controller and were generated in the Quartus II soft…
www.altera.com/support/kdb/solutions/fb157477.html - 2013-11-04

2013-11-01 130100 13.1 0 EMIF Maximum Frequency Specification Update for Stratix V

This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Stratix V devices may have difficulty achieving timing closure at certain maximum frequencies.
www.altera.com/support/kdb/solutions/fb163770.html - 2013-11-04

2013-11-04 0 0 Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_tx_editors.cpp, Line: 1046

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see this error if your SignalTap™ II Logic Analyzer has a trigger condition which includes a node…
www.altera.com/support/kdb/solutions/rd08272013_386.html - 2013-11-04

2013-11-04 130100 13.1 0 DDR3 HPS Interfaces Supported Only to 450 MHz on Arria V SoC ES Devices

This problem affects DDR3 products. In Arria V SoC ES devices, the HPS hard memory controller supports DDR3 interfaces to a maximum of 450 MHz. Higher frequency interfaces are not…
www.altera.com/support/kdb/solutions/fb144502.html - 2013-11-04

2013-11-04 130001 13.0 SP1 130100 13.1 ECC Enabled Automatically in Cyclone V SoC HPS Devices

This problem affects DDR2, DDR3, and LPDDR2 products. For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, if you create interface widths of 24 or 40, ECC is en…
www.altera.com/support/kdb/solutions/fb129162.html - 2013-11-04

2013-11-01 120101 12.1 SP1 0 EMIF Maximum Frequency Specification Update

This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience problems achieving timing closure at certain…
www.altera.com/support/kdb/solutions/fb156054.html - 2013-11-01

2013-10-30 130100 13.1 0 Unable to Install DS-5: “Error running msiexec”

You might see an error message similar to the following when you try to install DS-5: Error running msiexec ... Program ended with an error exit code The DS-5 installer does not r…
www.altera.com/support/kdb/solutions/fb146385.html - 2013-10-31

2014-02-28 130000 13.0 0 Why does my Cyclone V PCIe design have intermittent link up issue?

The Quartus® II software version 13.0sp1 and earlier have incorrect settings for the Receiver Common Mode Voltage (Vcm) and the Receiver Signal Detection Voltage Threshold (Vth) …
www.altera.com/support/kdb/solutions/rd10162013_246.html - 2013-10-31

2013-10-31 120100 12.1 130001 13.0 SP1 Conflicting Pin Assignment Error with UART0

If your HPS design was created with Qsys v13.0 or earlier, and you open it in v13.0 SP1 or later, you might see an error message similar to the following: The selected peripheral …
www.altera.com/support/kdb/solutions/fb137954.html - 2013-10-31

2013-10-30 130000 13.0 0 DS-5 Debugger Unable to Connect to SoC HPS

If you try to connect the DS-5 debugger to the SoC HPS with a USB-Blaster, you might see an error message similar to the following: Connection Failed Unable to connect This proble…
www.altera.com/support/kdb/solutions/fb143377.html - 2013-10-31

2013-10-30 0 0 Why is the PCIe Hard IP core not sending out the required flow control (FC) update within 30 us

Due to an issue with the Altera® PCI Express® Hard IP, FC update may not happen within the required 30us.
www.altera.com/support/kdb/solutions/rd10222013_523.html - 2013-10-30

2013-10-30 0 0 External Memory Interface Handbook: Known Issues

Issue 138581: Volume 3, Chapter 12: Timing Diagrams for UniPHY IP, Version 2.1 Figure 12-18 shows that the avl_size is 0. This value is illegal and should be 1. Everything else in…
www.altera.com/support/kdb/solutions/rd10082013_533.html - 2013-10-30

2013-10-30 120000 12.0 130000 13.0 Why do I see timing violations for the altera_reserved_tck signal when using DDR3 SDRAM controller with UniPHY?

Due to a problem in the Quartus® II software version 12.1sp1 and before, when instantiating a DDR3 SDRAM controller with UniPHY, you may get a hold timing violation for altera_rese…
www.altera.com/support/kdb/solutions/rd08312012_660.html - 2013-10-30

2014-10-07 120000 12.0 0 Why are the values for FS (Full Swing) and LF (Low Frequency) zero when simulating a PCIe Hard IP core for Gen3?

There is an issue with the PCIe® Hard IP simulation models when targeting the Stratix® V and Arria® V GZ device families, where the values for FS and LF are zero for Gen3.&nbs…
www.altera.com/support/kdb/solutions/rd10022013_210.html - 2013-10-30

2014-01-08 0 0 What is the description of the MsiIntfc_o[81:0] and MsixIntfc_o[15:0] signals?

If you select Enable multiple MSI/MSI-X support under the Avalon Memory-Mapped (Avalon-MM) System Settings banner in Hard IP for PCI Express® MegaWizard™ window, it expor…
www.altera.com/support/kdb/solutions/rd09262013_223.html - 2013-10-30

2013-12-02 130000 13.0 0 How should I connect the clocks on the Triple-Speed Ethernet (TSE) MegaCore IP when implemented in Qsys

When the TSE IP MAC is implemented in Qsys, the required clock connections are as detailed below:Qsys Name :  Interface Description in the User Guidecontrol_port_clock_co…
www.altera.com/support/kdb/solutions/rd10302013_752.html - 2013-10-30

2013-10-29 120100 12.1 130100 13.1 Rapid Recompile feature is disabled for all device families

If you compile a design that was created by a previous version of the Quartus II software, and the Quartus II Settings File (.qsf) contains the setting set_global_assignment ‑name…
www.altera.com/support/kdb/solutions/fb97271.html - 2013-10-29

2014-06-04 0 0 Why is my JTAG chain broken when the HPS_nRST or HPS_nPOR signal is asserted?

The hard processor system (HPS) JTAG port (HPS_TCK, HPS_TMS, HPS_TDI, HPS_TDO) of Arria® V SoC and Cyclone® V SoC devices is held in Test Logic Reset when either HPS_nRST or H…
www.altera.com/support/kdb/solutions/rd08122013_684.html - 2013-10-29

2013-10-29 0 0 Can I use the hard processor system (HPS) flash programmer to program a Raw Binary File (.rbf)?

The HPS flash programmer supports only the Binary File (.bin) type, not .rbf extension.
www.altera.com/support/kdb/solutions/rd10222013_501.html - 2013-10-29

2013-10-29 120000 12.0 120101 12.1 SP1 Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of (value)

This error may occur when compiling a project which contains an LPDDR2 controller and one or more non-associated on-chip termination (OCT) blocks. The reason is that the outp…
www.altera.com/support/kdb/solutions/rd11152012_357.html - 2013-10-29

2013-10-29 130001 13.0 SP1 130100 13.1 Assign LVDS I/O standard-supported pins in right I/O banks of Arria V A1/A3/C3 devices as PLL clock input pins only

If you use the Quartus II software version 13.0 DP2 or 13.0 SP1 to create a design that targets an Arria V A1, A3 or C3 device, and you use the LVDS I/O standard-enabled pins in t…
www.altera.com/support/kdb/solutions/fb128391.html - 2013-10-29

2013-10-29 120000 12.0 120100 12.1 The supplied JTAG Debug Information (.jdi) file for the project does not appear to match the specified target device as not all nodes have hierarchy info.

Due to an issue with the Quartus® II software version 12.0 and later, this error may occur the Quartus II software output files is set to a directory other than the defau…
www.altera.com/support/kdb/solutions/rd06122012_292.html - 2013-10-29

2013-10-29 120001 12.0 SP1 0 Error (129029): Input port CLK on atom "<DLL instance>", which is a arriav_dll primitive, is not connected to a valid source File: <project path>/dll.v Line: 53

The PLL output cannot be connected to the DLL directly when Enable access to dynamic phase shift ports is selected in the Altera PLL MegaWizard™ GUI. The Quartus® II…
www.altera.com/support/kdb/solutions/rd01152013_434.html - 2013-10-29

2013-10-29 110001 11.0 SP1 0 How do I reduce the UniPHY DDR3 controller pulsing avl_ready low on the Avalon interface?

Depending on the type of accesses on the controller's Avalon® interface, you may see the avl_ready pulse low in some situations where it should not be expected. This occurs because…
www.altera.com/support/kdb/solutions/rd08142013_467.html - 2013-10-29

2013-10-29 0 0 Does the Stratix V MLAB block support byte enable option in x16 depth mode?

No, Stratix® V device MLAB blocks do not support the byte enable option in x16 depth mode.
www.altera.com/support/kdb/solutions/rd10102013_890.html - 2013-10-29

2013-10-28 0 0 How do I duplicate nodes in Data tab of the SignalTap II Logic Analyzer?

To duplicate nodes in Data tab of the SignalTap™ II Logic Analyzer, select the nodes, then drag and drop while holding Ctrl key.
www.altera.com/support/kdb/solutions/rd10212013_335.html - 2013-10-28

2013-10-28 120000 12.0 0 How do I restore the Enable decompression during Partial Reconfiguration option?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, in Convert Programming File utility the Enable decompression during Partial Reconfiguration option is not…
www.altera.com/support/kdb/solutions/rd09132013_317.html - 2013-10-28