Search Results For:
 
 
  
Last Modified Version Found Version Found Version Fixed Version Fixed Document Title, Description, URL
2014-06-06 130200 13.1
Arria 10
Edition
0 How does the Arria 10 device know if the configuration mode is Fast Passive Parallel (FPP) or Passive Serial (PS) when the MSEL pin setting is the same for both modes?

In Arria® 10 devices the MSEL pins encode whether the device is operating in a Passive configuration mode (FPP/PS) or an Active mode (Active Serial (AS)). There is no separat…
www.altera.com/support/kdb/solutions/rd06052014_67.html - 2014-06-06

2014-06-05 130000 13.0 0 Is DDR2 SDRAM with HPS Hard Controller supported in Arria V SoC Devices?

No, Arria V SoC Devices do not support DDR2 SDRAM with an HPS Hard Memory Controller. The External Memory Interface Spec Estimator Tool incorrectly states that the Arria …
www.altera.com/support/kdb/solutions/rd08272013_227.html - 2014-06-05

2014-06-05 110001 11.0 SP1 110100 11.1 Warning (10230): Verilog HDL assignment warning at *instance_name*_write_datapath.v(118): truncated value with size to match size of target (1)

You may experience the above warning when compiling the DDR2 or DDR3 SDRAM Controller with UniPHY IP in Quartus II.  This warning occurs as Quartus II synthesized away so…
www.altera.com/support/kdb/solutions/rd03252014_634.html - 2014-06-05

2014-06-02 120000 12.0 0 Internal Error: Sub-system: SIN, File: /quartus/tsm/sin/sin_micro_tnodes_dag.cpp, Line: 626

This error may be seen in the Quartus® II software version(s) 12.0sp2 and earlier when running the EDA Netlist Writer to create IBIS Models for designs targeting the Arria® V famil…
www.altera.com/support/kdb/solutions/rd12072012_144.html - 2014-06-02

2014-06-02 130000 13.0 0 Internal Error: Sub-system: SSC, File: /quartus/tsm/ssc/ssc_timing.cpp, Line: 93

Due to a problem in the Quartus® II software version 13.0 and later, you may see this error during synthesis if the design does not having any timing paths and Timing-Driven S…
www.altera.com/support/kdb/solutions/rd05282014_443.html - 2014-06-02

2014-05-30 0 0 Is there a maximum configuration time specification for Passive Serial (PS) or Fast Passive Parallel (FPP) configuration modes?

There is no maximum configuration time specification for Passive Serial (PS) or Fast Passive Parallel (FPP) configuration modes.  Hence it is possible to pause DCLK durin…
www.altera.com/support/kdb/solutions/rd05292014_860.html - 2014-05-30

2014-06-01 0 0 Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

You may see this warning in the Quartus® II design software fitter report if a PLL which has the reconfiguration option enabled does not have a compensated clock specified.
www.altera.com/support/kdb/solutions/rd05232014_921.html - 2014-05-30

2014-05-29 130000 13.0 0 Why does Configuration via Protocol (CvP) fail to initiate core image update at PCIe Gen1 x1 in Cyclon V or Arria V?

Due to a problem in the Quartus® II software version 13.1 update 4 and earlier, the CvP may fail to initiate core image update showing time out error at PCI Express® Gen …
www.altera.com/support/kdb/solutions/rd05142014_39.html - 2014-05-29

2014-05-27 0 0 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

You may see the critical warning above during the fitter stage when compiling the UniPHY-based memory controller IP. You may safely ignore this critical warning message.
www.altera.com/support/kdb/solutions/rd01282014_301.html - 2014-05-27

2014-05-27 0 0 Error (170084): Can't route signal "~GND" to atom "< dqs_oct_alignment~_Duplicate>"

The above error may appear when you use the Stratix® V ALTDQ_DQS2 Megafunction in the Quartus® II software version 13.1. The error is caused during the fitter stage…
www.altera.com/support/kdb/solutions/rd05062014_472.html - 2014-05-27

2014-05-27 0 0 Stratix V Device Handbook: Known Issues

Issue 187612: Chapter 7.External Memory Interfaces in Stratix V Devices (.PDF) (ver 2014.01.10, Jan 2014, 532 KB) Table 7-2 shows External Memory Interface Performance in Str…
www.altera.com/support/kdb/solutions/rd04232014_345.html - 2014-05-27

2014-05-27 0 0 How to change the reset controller from hard reset to soft reset?

The HIP will use hard reset controller by default. Please use keyword "hip_hard_reset_hwtcl" in the PCIe core top level file, and then replace this parameter to '0'. This will chan…
www.altera.com/support/kdb/solutions/rd08302012_466.html - 2014-05-27

2014-05-23 0 0 Why does execution of the KEY_VERIFY JTAG instruction return 0x0 (hex) after the tamper protection bit has been programmed in Stratix V, Arria V or Cyclone V devices?

The JTAG instruction, KEY_VERIFY is one of many non-mandatory JTAG instructions that are disabled when the tamper protection bit is enabled in&nb…
www.altera.com/support/kdb/solutions/rd04112014_482.html - 2014-05-23

2014-08-03 0 0 Do additional power-up transient currents need to be added to the Early Power Estimator (EPE) or Power Play Power Analyzer (PPPA) reports for Stratix V devices?

No.  The transient currents at power-up are already included in the minimum current requirements in the EPE and PPPA tools for Stratix® V devices.  When th…
www.altera.com/support/kdb/solutions/rd03252014_294.html - 2014-05-23

2014-05-23 0 0 Can I place input differential clock or data pins in an I/O bank not powered by 2.5V VCCIO?

In Stratix® V, Arria® V, and Cyclone® V devices, the differential input buffer is powered by VCCPD which must be 2.5-V to support differential
www.altera.com/support/kdb/solutions/rd06252012_306.html - 2014-05-23

2014-05-19 0 0 Can I use Hard Processor System (HPS) I/Os for the Logic Analyzer Interface?

The Logic Analyzer Interface does not support HPS I/Os. 
www.altera.com/support/kdb/solutions/rd05012014_686.html - 2014-05-19

2014-05-19 130100 13.1 0 Why is it not possible to drive out on pins that are reserved as bi-directional when performing post-configuration mode boundary scan testing on Arria V or Cyclone V devices?

Due to a problem in the Quartus® II software version 13.1, the output buffers of pins that are reserved as bidirectional are disabled in Arria® V or Cyclone® V …
www.altera.com/support/kdb/solutions/rd04282014_840.html - 2014-05-19

2014-05-19 110100 11.1 0 Why does the PowerPlay Early Power Estimator (EPE) show incorrect number of Hard Memory Controller (HMC) when the EPE imports the PowerPlay Early Power Estimator (.csv) file?

Due to a problem in the Quartus® II software version 11.1 and later, the EPE may show an incorrect number of HMCs when the EPE imports the .csv file. The Quart…
www.altera.com/support/kdb/solutions/rd03182014_858.html - 2014-05-19

2014-05-15 130001 13.0 SP1 0 In Heavy Traffic, RapidIO IP Core Might Not Respond to Some NWRITE_R Packets

The RapidIO IP core might not transmit some NWRITE_R Response packets, when it is operating in heavy traffic, due to FIFO overflow.
www.altera.com/support/kdb/solutions/fb184807.html - 2014-05-16

2014-05-19 130100 13.1 0 How can I address known issues with the ALTASMI_PARALLEL megafunction in the Quartus II software version 13.1?

There are known issues with the read_status port and Read Device Dummy Clock function in the ALTASMI_PARALLEL megafunction, in the Quartus® II software version …
www.altera.com/support/kdb/solutions/rd05132014_481.html - 2014-05-16

2014-05-15 130001 13.0 SP1 0 RapidIO IP Core Does Not Support ILL_TRAN_TARGET Field of Logical/Transport Layer Error Detect CSR

The RapidIO IP core does not update the ILL_TRAN_TARGET field of the Logical/Transport Layer Error Detect CSR at offset 0x10800.
www.altera.com/support/kdb/solutions/fb137266.html - 2014-05-16

2014-07-10 0 0 Can the CLKUSR pin be used as both a configuration pin and then a user I/O pin after the device enters user mode?

If you have enabled the CLKUSR pin function in your Quartus® II project, it cannot be used as user I/O once configuration is complete and the device has entered user…
www.altera.com/support/kdb/solutions/rd05152014_443.html - 2014-05-16

2014-05-16 0 0 Can the VCCLSENSE and GNDSENSE pins be left unconnected if not used on Arria 10 devices?

Yes, if the VCCLSENSE and GNDSENSE pins are not used on Arria® 10 devices, you can leave them unconnected.
www.altera.com/support/kdb/solutions/rd03312014_367.html - 2014-05-16

2014-05-16 0 0 Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI?

Altera® does not provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI. You can refer to the Input Signal Edge Rate Guidance (PDF) …
www.altera.com/support/kdb/solutions/rd03192014_573.html - 2014-05-16

2014-05-15 120000 12.0 0 Some RapidIO IP Core Variations Do Not Assert mnt_s_readerror Correctly

The RapidIO IP core Maintenance module should assert the mnt_s_readerror output signal in response to a Read response packet with status ERROR. However, 2x and 4x IP core variatio…
www.altera.com/support/kdb/solutions/fb187952.html - 2014-05-16

2014-05-15 120100 12.1 0 RapidIO II IP Core Capture Registers Might Capture Wrong Information for Out-of-Order Maintenance Response Packet With Error

When the RapidIO II IP core Maintenance module receives a response packet with ERROR status, it captures information about the errored packet in the Error Management Extension Log…
www.altera.com/support/kdb/solutions/fb185168.html - 2014-05-16

2014-05-15 110000 11.0 110100 11.1 RapidIO IP Core Might Lose TX Buffers During Resynchronization of ackID Value

If you resynchronize the ackID value for your RapidIO IP core instance, the IP core should reset the expected ackID value in the Port 0 Local AckID CSR at offset 0x148. The change…
www.altera.com/support/kdb/solutions/fb202053.html - 2014-05-16

2014-05-16 0 0 Why does the Early Power Estimator tool (EPE) report higher power than PowerPlay Power Analyzer (PPPA), when using ALTUFM_OSC in MAX II and MAX V devices?

When using the ALTUFM_OSC megafunction in MAX® II or MAX V devices, the EPE and Quartus® II PPPA power results may vary significantly, if the oscena port is hardcode…
www.altera.com/support/kdb/solutions/rd05082014_372.html - 2014-05-16

2014-05-16 0 0 What type of memory technology is used in Altera Quad-Serial (EPCQ) configuration devices?

Altera® EPCQ devices employ NOR flash memory technology.
www.altera.com/support/kdb/solutions/rd01282014_625.html - 2014-05-16

2014-05-16 130100 13.1 0 Is there a known issue with the scandata port when using the ALTPLL_RECONFIG megafunction in the Quartus® II software version 13.1?

The scandata output port in the ALTPLL_RECONFIG megafunction has been inverted in the Quartus® II software version 13.1.
www.altera.com/support/kdb/solutions/rd05052014_157.html - 2014-05-16

2014-05-16 0 0 Does varying the Junction Temperature (Tj) or Ambient Temperature (Ta) settings in the Quartus II software affect the overall power results in PowerPlay Power Analyzer (PPPA), for MAX II Industrial and Extended Temperature grade devices?

Varying Tj or Ta in the Operating Temperature conditions in the Quartus® II design software will not affect the overall power reported by PPPA when targeting Industrial a…
www.altera.com/support/kdb/solutions/rd05082014_157.html - 2014-05-16

2014-12-04 130001 13.0 SP1 0 How do I generate Configuration via Protocol (CvP) programming files for a Arria V or Cyclone V designs?

To generate CvP programming files for Arria® V or Cyclone® V CvP designs with Quartus® II software version 13.1 and earlier, follow the workaround/fix steps below: &…
www.altera.com/support/kdb/solutions/rd10162013_225.html - 2014-05-16

2014-05-15 0 0 Do the UniPHY-based memory controllers support Short ZQ Calibration?

No, the UniPHY-based memory controllers do not support Short ZQ Calibration. The UniPHY-based controllers use DQS Tracking to adjust for small voltage and temperature variations. R…
www.altera.com/support/kdb/solutions/rd03032014_876.html - 2014-05-15

2014-05-15 130100 13.1 0 Error: The specified Memory clock frequency exceeds the Memory device speed grade of 533.333 MHz. Please increase the Memory device speed grade (in Memory Parameters tab) or decrease the Memory clock frequency.

You may see the above error when generating a Stratix IV DDR3 UniPHY controller in the Quartus® II software version 13.1 or later. There is a new frequency check in the MegaWizard™…
www.altera.com/support/kdb/solutions/rd03252014_367.html - 2014-05-15

2014-05-15 0 0 Error: nofile(37): in protected region

You may experience the above error while simulating a VHDL-based DDR3 UniPHY memory controller design with ModelSim. When the DDR3 memory controller is generated in VHDL, all …
www.altera.com/support/kdb/solutions/rd12162013_881.html - 2014-05-15

2014-07-04 130100 13.1 0 Which ARM SoC addresses report the status of the physical FPGA-to-HPS Interrupts (f2h_irq0 and f2h_irq1 signals)?

In the Altera SoC Hard Processor System (HPS), the raw status of the physical f2h_irq0 and f2h_irq1 interrupt signals can be read directly from the ARM® Generic Interrupt Controlle…
www.altera.com/support/kdb/solutions/rd04282014_511.html - 2014-05-15

2014-05-15 120100 12.1 0 Why do I see R105 warnings on the DDR3 reset paths when using the Design Assistant tool?

The Design Assistant tool will generate R105 warnings if it detects a reset signal that is generated in one clock domain and used in another clock domain. This warns the user …
www.altera.com/support/kdb/solutions/rd05012014_39.html - 2014-05-15

2014-05-15 120101 12.1 SP1 0 Why is ODT asserted for more than one rank in my DDR3 UniPHY controller?

If you have a multi-rank DDR3 UniPHY controller generated in the Quartus® II software version 12.1SP1 or later, you may see the ODT signals for multiple ranks assert at the sa…
www.altera.com/support/kdb/solutions/rd04142014_400.html - 2014-05-15

2014-05-15 0 0 How do I specify different timing constraints for TimeQuest, Fitter, or Analysis & Synthesis?

To identify which executable is currently running you can use the $::TimeQuestInfo(nameofexecutable) command from within a Synopsys Design Constraints (.sdc) file. This method can …
www.altera.com/support/kdb/solutions/rd06062011_944.html - 2014-05-15

2014-05-14 120100 12.1 0 RapidIO II IP Core Capture Registers Might Capture Wrong Information for Out-of-Order Non-Maintenance Response Packet With Error

When the RapidIO II IP core I/O slave module receives a response packet with ERROR status, it captures information about the errored packet in the Error Management Extension Logic…
www.altera.com/support/kdb/solutions/fb187964.html - 2014-05-14

2014-05-14 0 0 Why does the Stratix V Advanced Systems Development Kit fail to link up to L0?

Due to an error in the schematic, provided .pin and Quartus® II Settings File(.qsf) files, the PCI Express® reference clock is not assigned to the correct pins. This error&nbs…
www.altera.com/support/kdb/solutions/rd05012014_582.html - 2014-05-14

2014-05-14 0 0 How can I dynamically change the Stratix V Hard IP for PCIe configuration registers' content?

The Stratix® V Hard IP for PCI Express® configuration registers' content can be dynamically modified through the Hard IP Avalon® Memory-Mapped (Avalon-MM) reconfiguration inte…
www.altera.com/support/kdb/solutions/rd05072014_141.html - 2014-05-14

2014-05-20 120101 12.1 SP1 0 Why do MSI's not work on my altpcie_demo application for the PCI Express Avalon-ST High-Performance Reference Design?

Due to a problem with the provided driver information file(.inf), the reference design Device ID does not match that expected by the driver and Message Signal Interrupts (MSIs…
www.altera.com/support/kdb/solutions/rd12102013_51.html - 2014-05-14

2014-05-14 110100 11.1 0 Why does the PCI Express Hard IP core not transistion through all the required hot reset LTSSM states in simulation?

Due to a problem in the soft reset controller, when hot reset is applied, the LTSSM does not go through every state expected when initiating hot resets.
www.altera.com/support/kdb/solutions/rd01072014_718.html - 2014-05-14

2014-06-23 0 0 How do I ensure cold-start operation for Enpirion EN53xxxx and EP53xxxx series devices?

You can ensure cold-start operation for Enpirion® EN53xxxx and EP53xxxx series devices by adding a delay on the ENABLE pin. This can be done by adding a 10-kR resistor between…
www.altera.com/support/kdb/solutions/rd04022014_824.html - 2014-05-14

2014-05-14 120101 12.1 SP1 0 Why does my altpcie_demo application display as "PCI Device" under "Other Devices" in the Windows Device Manager for the PCI Express Avalon-ST High-Performance Reference Design?

Due to a problem with the provided driver information file(.inf), the reference design Device ID does not match that expected by the driver and Message Signal Interrupts (MSIs…
www.altera.com/support/kdb/solutions/rd05082014_916.html - 2014-05-14

2014-08-03 0 0 Error: dma_0_control_port_slave_translator.avalon_anti_slave_0: master without waitrequest must match parameters and ports of slave dma_0_control_port_slave_translator_avalon_anti_slave_0_agent.av

You will see this error when generating a 64-bit address Avalon® Memory-Mapped Hard IP for PCI Express® design with the Scatter Gather DMA (SGDMA) function.The error…
www.altera.com/support/kdb/solutions/rd04302014_603.html - 2014-05-14

2014-10-10 0 0 How should I connect coreclkout_hip to pld_clk on Stratix V?

In the Stratix® IV Hard IP for PCI Express®, some configurations allowed the pld_clk to be driven from a PLL that was, in turn, derived from coreclkout_hip.  Th…
www.altera.com/support/kdb/solutions/rd05062014_528.html - 2014-05-14

2014-05-12 130100 13.1 130102 13.1
Update2
RapidIO II IP Core Might Declare Loss of Scrambler Synchronization If Link Partner Has Different Reference Clock Source

If the RapidIO II IP core and its RapidIO link partner have independent reference clock sources, the RapidIO II IP core declares a scrambler synchronization error by setting bit […
www.altera.com/support/kdb/solutions/fb183580.html - 2014-05-13

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Set RESPONSE_VALID in Port 0 Link Maintenance Response CSR After Transmitting link-request reset-device Control Symbol

After the RapidIO II IP core sends a link-request reset-device control symbol on the RapidIO link, it should set the RESPONSE_VALID bit in the Port 0 Link Maintenance Response CSR…
www.altera.com/support/kdb/solutions/fb184795.html - 2014-05-13

2014-05-12 120100 12.1 130100 13.1 RapidIO II IP Core Might Send Truncated Data on Avalon-ST Pass-Through Interface if tt = 0

When a RapidIO II IP core sends data to the Avalon-ST Pass-Through interface in a transaction with Transport Type value 0, it truncates the payload to a multiple of eight bytes.
www.altera.com/support/kdb/solutions/fb193858a.html - 2014-05-13

2014-05-12 120100 12.1 0 RapidIO II IP Core Might Send Truncated Data on Avalon-ST Pass-Through Interface if tt = 1

When the RapidIO II IP core sends data to the Avalon-ST Pass-Through interface in a transaction with Transport Type value 1, it truncates the payload to a multiple of eight bytes.…
www.altera.com/support/kdb/solutions/fb193858b.html - 2014-05-13

2014-05-12 120100 12.1 0 RapidIO II IP Core logical_transport_error, port_failed, and port_degraded Input Signals Do Not Trigger Interrupts

The RapidIO II IP core Port 0 Control CSR (offset 0x15C) LOG_TRANS_ERR_IRQ_EN, PORT_FAIL_IRQ_EN, and PORT_DEGR_IRQ_EN bits should control whether or not the IP core generates an i…
www.altera.com/support/kdb/solutions/fb187972.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Transmits Unintended link-request Control Symbols

Writing the value 3’b100 to the COMMAND field of the RapidIO II IP core Port 0 Link Maintenance Request CSR at offset 0x140 should cause the RapidIO II IP core to transmit a singl…
www.altera.com/support/kdb/solutions/fb183974.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Might Transmit More Than 515 Consecutive IDLE2 Characters

According to the RapidIO Interconnect Specification, Revision 2.2, the total length of the IDLE Sequence 2 random data field can be no more than 515 characters. However, the Rapid…
www.altera.com/support/kdb/solutions/fb184811.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Declare Illegal Transaction Decode in Response to Malformed NWRITE_R Response Packet

When the RapidIO II IP core receives a malformed NWRITE_R response packet on the RapidIO link, it should declare an Illegal Transaction Decode by setting the ILL_TRAN_DECODE bit i…
www.altera.com/support/kdb/solutions/fb187948.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Erroneously Transitions to Output Error Stopped State

When software writes to the COMMAND field of the Port 0 Link Maintenance Request CSR at offset 0x140 to specify that the outgoing link-request packet has the value input-status in…
www.altera.com/support/kdb/solutions/fb185176.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Responds Incorrectly to Received stomp Control Symbol

According to Part 6 of the RapidIO Protocol Specifications, Revision 2.2, when the RapidIO II IP core receives a stomp control symbol, it should enter the Input Retry Stopped stat…
www.altera.com/support/kdb/solutions/fb184787.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Support Streaming Data Packets with Device ID Width 16

The RapidIO II IP core does not support streaming data packets (packets with ftype value of 9) in variations with a 16-bit device width (packet tt value of 1).
www.altera.com/support/kdb/solutions/fb184789.html - 2014-05-12

2014-05-13 120100 12.1 0 Why is the VCCIO current estimation lower than expected for the Hard Memory Controller?

You may see lower than expected maximum VCCIO current in the PowerPlay Power Analyzer report for the banks which contain address/command pins which are controlled by a hard me…
www.altera.com/support/kdb/solutions/rd02032014_570.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Support Write Transactions With Payload Size Below Maximum

The RapidIO II IP core should be able to handle NWRITE and NWRITE_R requests on the RapidIO link for all legal combinations described in Table 4-4 in Part 1: Input/Output Logical …
www.altera.com/support/kdb/solutions/fb187932.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Incorrectly Sets Illegal Transaction Decode Flag Instead of Unsupported Transaction Flag

In response to an incoming RapidIO read transaction with rdsize greater than 4’b1011 and address[0] set to 1, the RapidIO II IP core should set the Unsupported Transaction (UNSUPP…
www.altera.com/support/kdb/solutions/fb187928.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Does Not Drop Packets When STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE and DROP_PKT_ENABLE Bits Are Set

When the RapidIO II IP core Port 0 Control CSR (offset 0x15C) STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE and DROP_PKT_ENABLE fields are set, the port should discard all output packets unti…
www.altera.com/support/kdb/solutions/fb184792.html - 2014-05-12

2014-05-12 120100 12.1 130100 13.1 RapidIO II IP Core Does Not Transmit NREAD Responses With Payload Size Less Than 16 Bytes

According to the RapidIO Protocol Specifications, Revision 2.2, the mimimum size of Read payload on the RapidIO link is eight bytes. However, the RapidIO II IP core does not trans…
www.altera.com/support/kdb/solutions/fb193869.html - 2014-05-12

2014-05-12 130100 13.1 130103 13.1
Update3
RapidIO II IP Core Detects Corrupted Control Symbol If Link Partner Has Different Reference Clock Frequency

If the RapidIO II IP core and its RapidIO link partner have different reference clock frequencies, the RapidIO II IP core might detect a corrupted control symbol or a control symb…
www.altera.com/support/kdb/solutions/fb183585.html - 2014-05-12

2014-05-12 120100 12.1 0 RapidIO II IP Core Transmits link-response Control Symbols With Incorrect port_status Value

When the RapidIO II IP core transmits a link-response control symbol, it does not provide a correct value in the port_status field.
www.altera.com/support/kdb/solutions/fb184732.html - 2014-05-12

2014-05-09 130000 13.0 0 40-100GbE IP Core User Guide Describes IPG_DEL_PERIOD Register Incorrectly

The 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide describes the 40-100GbE IP core IPG_DEL_PERIOD register at offset 0x126 incorrectly. The user guide states …
www.altera.com/support/kdb/solutions/fb199633.html - 2014-05-10

2014-05-09 120000 12.0 0 40-100GbE IP Core User Guide Erroneously Indicates Pause Signals Are Unavailable in Variations Without Adapters

The 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide states that the 40-100GbE IP core pause control and generation signals are unavailable in IP core variations…
www.altera.com/support/kdb/solutions/fb204361.html - 2014-05-10

2014-05-08 0 0 Which On-Chip Termination (OCT) setting is supported by the HiSPI I/O standard in Cyclone V devices?

HiSPi inputs in Cyclone® V devices support the "Differential" OCT assignment, similar to LVDS inputs.
www.altera.com/support/kdb/solutions/rd05062014_851.html - 2014-05-08

2014-05-13 130100 13.1 0 Why does the read_status port on the ALTASMI_PARALLEL megafunction not return the correct status?

Due to a problem in the Quartus® II software version 13.1, the read_status port of the ALTASMI_PARALLEL megafunction does not return the correct status on the dataout port.
www.altera.com/support/kdb/solutions/rd05062014_83.html - 2014-05-08

2014-06-29 0 0 Are there any recommendations when using more than one ATX PLL that run at the same Voltage Controlled Oscillator (VCO) frequency in Arria V GZ and Stratix V transceiver devices?

Yes, there are placement recommendations when using more than one ATX PLL that run at the same VCO frequency in Arria® V GZ and Stratix® V transceiver devices. For optimal ATX PL…
www.altera.com/support/kdb/solutions/rd03282014_193.html - 2014-05-07

2014-05-07 130100 13.1 0 Do Arria V GX devices support the Rate Match FIFO option when the word aligner is in manual alignment mode, and the PMA-PCS interface is 20 bits wide?

Yes, Arria® V GX devices support the Rate Match FIFO option when the word aligner is in manual alignment mode, and the PMA-PCS interface is 20 bits wide. Due to a mistake in Fi…
www.altera.com/support/kdb/solutions/rd03242014_198.html - 2014-05-07

2014-06-29 120101 12.1 SP1 0 Why is the pll_powerdown port of the Stratix V device Transceiver Native PHY IP Core not removed when I enable the “Use external TX PLL” option?

Due to a problem in the Quartus® II software, the pll_powerdown port of the Stratix® V device Transceiver Native PHY IP Core is not removed when the “Use external TX PLL” option is…
www.altera.com/support/kdb/solutions/rd05042014_393.html - 2014-05-07

2014-06-29 130100 13.1 0 Critical Warning: parameter 'crcchk_init' of instance '...|sv_hssi_10g_rx_pcs_rbc' has illegal value '' assigned to it. Valid parameter values are: '(crcchk_int)'. Using value 'crcchk_int'

You may see the following warning message when implementing the Stratix® V device 10GBaser-R IP in Quartus® II software versions 13.1 and earlier. Info (10648): Verilog HDL D…
www.altera.com/support/kdb/solutions/rd04292014_918.html - 2014-05-07

2014-05-07 0 0 Why can’t I turn on the rx_clklow and rx_fref ports in the Transceiver Native PHY IP Core for of Arria V, Cyclone V, and Stratix V devices?

Due to a problem with the Altera Transceiver PHY IP Core User Guide (PDF), the rx_clklow and rx_fref ports are incorrectly listed as available on the Native PHY IP Core for Arria® …
www.altera.com/support/kdb/solutions/rd02092014_792.html - 2014-05-07

2014-05-07 120100 12.1 0 All Devices in Multirank Designs Must Enter and Exit Self-Refresh at the Same Time

This problem affects all external memory interface products. In multirank designs, you must ensure that all memory devices enter self-refresh at the same time, and exit self-refre…
www.altera.com/support/kdb/solutions/fb72361.html - 2014-05-07

2014-05-07 130100 13.1 0 Why does the Arria V GZ and Stratix V device Transceiver PLL Megawizard show a "Dynamic reconfiguration of ATX PLLs is not supported in the current release" message when you hover your cursor over the "Enable PLL reconfiguration" option in Quartus® II software version 13.1?

Due to a problem in the Quartus II software version 13.1 MegaWizard Plugin Manager, the Arria® V GZ and Stratix® V Transceiver PLL Megawizard™ shows a "Dynamic reconfiguration of A…
www.altera.com/support/kdb/solutions/rd01132014_769.html - 2014-05-07

2014-06-29 0 0 Why does the Quartus II software fail to fit more than four groups of 40G BaseKR IP into one side of a Stratix V device?

When you place more than four groups of 40G BaseKR IP on one side of a Stratix® V device, you might get the following error message: Error (175001): Could not place fractio…
www.altera.com/support/kdb/solutions/rd03272014_628.html - 2014-05-07

2014-05-07 130100 13.1 0 Why does the Arria V GX and Cyclone V GX device Transceiver PLL Megawizard show a "Dynamic reconfiguration of ATX PLLs is not supported in the current release" message when you hover your cursor over the "Enable PLL reconfiguration" option in Quartus II software version 13.1?

Due to a problem in the Quartus® II software version 13.1 MegaWizard™ Plug-In Manager, the Arria® V GX and Cyclone® V GX device Transceiver PLL Megawizard shows a "Dynamic reconfig…
www.altera.com/support/kdb/solutions/rd01132014_734.html - 2014-05-07

2014-05-07 130100 13.1 0 Error: set_port_property sets an illegal FRAGMENT_LIST for port unused_rx_parallel_data

Due to a problem in Quartus® II software version 13.1 update 3 you may see this error when using an Arria® V device Transceiver Native PHY instance with the “Enable simpl…
www.altera.com/support/kdb/solutions/rd04092014_581.html - 2014-05-07

2014-05-07 130100 13.1 0 Simulation With Riviera-PRO May Fail to Initialize Under Certain Conditions

This problem affects all external memory interface products. If your design uses a VHDL simulation model with an Altera External Memory bus functional model (.BFM), simulation wit…
www.altera.com/support/kdb/solutions/fb187580.html - 2014-05-07

2014-06-29 130100 13.1 0 Why does the recommendation for the connection of the unused GXB_RX and GXB_REFCLK pins disagree between the Stratix V and Arria V GZ pin connection guidelines documents and the Quartus II software .PIN files?

Due to a problem in Quartus® II Software version 13.1 and earlier, the recommendation for connecting unused GXB_RX and GXB_REFCLK pins for Stratix® V and Arria® V GZ devi…
www.altera.com/support/kdb/solutions/rd03032014_448.html - 2014-05-07

2014-06-29 0 0 Can I invert the transciever Tx polarity with a signal port when using the Stratix V device, Native PHY IP, 10G PCS?

No, You cannot invert the transciever Tx polarity with a signal port when using the Stratix® V device, Native PHY IP, 10G PCS.
www.altera.com/support/kdb/solutions/rd01162014_412.html - 2014-05-07

2014-05-02 130104 13.1
Update4
0 Can the 128-bit Avalon-MM Txs slave interface of the Altera Hard IP for PCI Express handle read/write request with ByteEnable=0x01 ?

Due to a problem in the Quartus® II software version 13.1 and earlier, the 128-bit Avalon-MM® Txs slave interface of the Hard IP for PCI Express® cannot generate a correc…
www.altera.com/support/kdb/solutions/rd04172014_563.html - 2014-05-02

2014-04-30 130100 13.1 0 NicheStack TCP/IP Stack - Nios II Edition No Longer Supported

You might encounter problems using the NicheStack TCP/IP Stack - Nios II Edition. For example, you might see an error similar to the following: inet startup error: unable to find …
www.altera.com/support/kdb/solutions/fb172438.html - 2014-05-01

2014-12-16 130001 13.0 SP1 130100 13.1 Why is the PCI Express endpoint stuck in DETECT.QUIET when using the example Avalon-MM Qsys design?

The Avalon®-MM Stratix® V Hard IP for PCI® Express example design, which is available from the <install_dir>/ip/altera/altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ di…
www.altera.com/support/kdb/solutions/rd12312013_590.html - 2014-04-30

2014-04-30 120100 12.1 0 Why does alt_signaltap_run fail in MATLAB?

When alt_signaltap_run is run under MATLAB™, an "Assertion failed" pop-up window is displayed and MATLAB crashes when the pop-up is dismissed.
www.altera.com/support/kdb/solutions/rd12132013_803.html - 2014-04-30

2014-04-30 130001 13.0 SP1 130100 13.1 Error in 'mdm/HDLImport' while executing C MEX S-function 'sGeneric', (mdlStart), at time 0.0.

You may receive the error message below when running a Simulink® simulation which includes the NCO Megacore® block using DSP Builder in an Arria® V design: Error in 'mdm…
www.altera.com/support/kdb/solutions/rd08072013_475.html - 2014-04-30

2014-05-06 0 0 Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"

When recompiling the PCI Express® reference design supplied with AN465 the following error occurs: Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_s…
www.altera.com/support/kdb/solutions/rd02032014_790.html - 2014-04-30

2014-04-30 0 0 Warning (12283): Assignment INPUT_TERMINATION on transceiver refclk clk buf/pin is not supported

In Arria® V, Cyclone® V and Stratix® V devices the INPUT_TERMINATION assignment cannot be used on transceiver pins.
www.altera.com/support/kdb/solutions/rd04042013_231.html - 2014-04-30

2014-05-27 0 0 Parameter "rstctrl_tx_lc_pll_rstb_select" of instance "stratixv_hssi_gen3_pcie_hip" has illegal value "ch4_10_sel" assigned to it. Possible parameter values are: "NOT_ACTIVE", "CH4_OUT", "CH4_10_OUT", "CH1_OUT", "CH7_OUT".

This error can occur if the parameter force_hrc=1 is set in the Hard IP(HIP) for PCI Express® variant file. Typically this occurs if you are moving from a Gen 2 to Gen 3 …
www.altera.com/support/kdb/solutions/rd04232014_376.html - 2014-04-29

2014-04-28 130100 13.1 0 Manual Removal of Unsupported Families from VHDL DO File in Customer Testbench

For SerialLite II 13.1 designs using Arria II GX and Stratix IV GX devices, the customer testbench DO file includes obsolete device families. The obsoleted device families includ…
www.altera.com/support/kdb/solutions/fb182571.html - 2014-04-28

2014-04-29 130100 13.1 0 Why don't I get identical fitter results when my source files haven't changed?

Due to a problem in the Quartus® II software version 13.1, you may see that compiles with identical source files do not have identical fitter results if you are using the SignalTap…
www.altera.com/support/kdb/solutions/rd04222014_264.html - 2014-04-28

2014-05-01 130100 13.1 0 Certain Ports and Parameters Not Supported In SDI Audio IP Cores for 13.1

Version 13.1 of the SDI Audio Embed and Audio Extract MegaCore functions do not support certain ports and parameters. The following ports and parameters are not fully implemented.…
www.altera.com/support/kdb/solutions/fb175422.html - 2014-04-28

2014-05-01 130000 13.0 0 Audio Embed IP Design Transmits Unstable 3G Video Image

Designs using SDI Audio Embed IP core transmit unstable and flickering 3G video images. This issue affects all designs using the SDI Audio Embed MegaCore function version 13.1.
www.altera.com/support/kdb/solutions/fb184377.html - 2014-04-28

2014-05-01 130100 13.1 0 SDI II Does Not Assert Frame Locked Signal and Shows Invalid Receive Format When Receiving Certain Video Formats

The Serial Digital Interface (SDI) II MegaCore function does not assert the frame_locked signal and shows invalid rx_format signal when it receives certain video formats. This iss…
www.altera.com/support/kdb/solutions/fb183561.html - 2014-04-28

2014-04-28 0 0 How do I launch Transceiver Toolkit without launching the Quartus II software first?

You can not launch Transceiver Toolkit as a standalone application. Transceiver Toolkit can only be launched from the Quartus II® software GUI.
www.altera.com/support/kdb/solutions/rd04112014_654.html - 2014-04-28

2014-05-01 130000 13.0 130100 13.1 Broadcast Deinterlacer Fails to Launch

The Broadcast Deinterlacer MegaCore function in the Video and Image Processing Suite version 13.1 fails to launch. You cannot access the Broadcast Deinterlacer parameters through …
www.altera.com/support/kdb/solutions/fb160499.html - 2014-04-28

2014-04-28 0 0 Why does the Arria V GZ and Stratix V Hard IP for PCI Express Gen3 LTSSM periodically transition from L0 state to the Recovery state then back to L0 state?

A Gen3  Arria® V GZ and Stratix® V Hard IP  for PCI Express® instance may transition from L0 to Recovery and back again if the receive(RX) Physical Coding Sublayer(P…
www.altera.com/support/kdb/solutions/rd04242014_695.html - 2014-04-28

2014-04-28 130100 13.1 0 Error (21075): The junction temperature range value of '[-40 C, 100 C]' is illegal for the currently selected part.

In the Quartus® II software version 13.1, you may see this fitter error if you compile a design targetting a Max® V device in the industrial temperature range that was&nb…
www.altera.com/support/kdb/solutions/rd04152014_654.html - 2014-04-28

2014-05-12 130100 13.1 140000 14.0 Upgrade IP Window Display Incorrect ACDS Version Number for Altera Ethernet 10G MAC Design Examples

When you load any of the Ethernet 10G MAC design examples, the Upgrade IP Cores window displays incorrect current ACDS version. This issue does not have any impact on the version…
www.altera.com/support/kdb/solutions/fb200361.html - 2014-04-28

2014-04-25 130100 13.1 0 How should the DCLK and DATA pins be connected when using the HPS to configure the FPGA fabric in Arria V or Cyclone V SoC devices?

When configuring an Arria® V SoC or Cyclone® V SoC device through the HPS, the configuration DATA pins can be left unconnected. The DCLK pin should not be left uncon…
www.altera.com/support/kdb/solutions/rd04242014_804.html - 2014-04-25

2014-04-28 130000 13.0 0 No OpenCore Plus Feature for V Series

OpenCore Plus feature is not supported for SerialLite II designs that target Arria V, Cyclone V, and Stratix V devices. This issue will be fixed in a future version of the Serial…
www.altera.com/support/kdb/solutions/fb153676.html - 2014-04-25

2014-04-25 0 0 Error (169187): Following feature(s) of I/O pin <pin_name> has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location <pin_location>

Due to a problem in the Quartus® II software you may see this error message when the WEAK_PULL_UP_RESISTOR option is disabled in a project targeting Cyclone® IV…
www.altera.com/support/kdb/solutions/rd04072014_413.html - 2014-04-25

2014-04-17 130000 13.0 130100 13.1 "Port already in use" Error When Attempting to Connect DS-5 to Multiple USB Blaster Targets

The ARM DS-5 debugger supports connecting to only a single USB Blaster debug target at a time on a given host. If you attempt to launch multiple USB Blaster debug connections, DS-…
www.altera.com/support/kdb/solutions/fb145963.html - 2014-04-21

2014-04-16 120100 12.1 0 Incorrect ACP IDs Listed in HPS Technical Reference Manual

The Hard Processor System Technical Reference Manual lists incorrect values for the HPS peripheral master input IDs in the Accelerator Coherency Port (ACP) ID mapper. The “HPS Per…
www.altera.com/support/kdb/solutions/fb169066.html - 2014-04-18

2014-04-16 130000 13.0 0 "FPGA programming might cause HPS boot error” Message While Programming SoC

When you program the FPGA portion of the SoC through the USB Blaster, the contents of the HPS SDRAM can corrupt the session. This noise might overwrite the operating system (OS) i…
www.altera.com/support/kdb/solutions/fb132225.html - 2014-04-18

2014-04-23 0 0 Which Altera FPGA devices support EPCQ-L devices for Active Serial (AS) configuration?

EPCQ-L devices can only be used with Arria® 10 devices for Active Serial (AS) configuration. Older Altera® device families do not support EPCQ-L devices for AS confi…
www.altera.com/support/kdb/solutions/rd04162014_770.html - 2014-04-17

2014-04-17 0 0 Does connecting VCCIO to a different voltage to that stated in the Quartus II fitter report affect device reliability?

Altera® characterizes device operation under conditions consistent with the "Recommended Operating Conditions” that can be found in the respective devices datasheet.  Operatio…
www.altera.com/support/kdb/solutions/rd04082014_356.html - 2014-04-17

2014-04-16 0 0 How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stratix V devices?

To use the Hard IP for PCI Express® test bus in conjunction with SignalTap™ II, a register map, or general purpose IOs to observe the PIPE interface signals on Arria® V GZ a…
www.altera.com/support/kdb/solutions/rd03042014_402.html - 2014-04-16

2014-04-16 0 0 Warning (12192): "10GBASE-R PCS-PMA " does not support the OpenCore Plus Hardware Evaluation feature

You may receive the following messages when trying to generate an OpenCore Plus time limited SOF file for the 10GBASE-R PCS-PMA Etherent IP. Warning (12189): OpenCore Simulation-O…
www.altera.com/support/kdb/solutions/rd04092014_926.html - 2014-04-16

2014-04-16 0 0 Why is my Stratix IV Hard IP for PCI Express VHDL altpcierd_write_dma_requester_128.vhd different from its Verilog counterpart?

The Stratix IV® Hard IP for PCI Express® in VHDL has an inconsistency from its Verilog HDL counterpart. This inconsistency can cause errors in a PCIe design for certain a…
www.altera.com/support/kdb/solutions/rd02242014_414.html - 2014-04-16

2014-04-30 0 0 Error: pcie_av_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name"

This error will be seen when generating a testbench for the PCI Express® reference design supplied with AN456 in either Arria® V or Cyclone® V devices. This error is…
www.altera.com/support/kdb/solutions/rd04092014_108.html - 2014-04-15

2014-04-15 130200 13.1
Arria 10
Edition
0 Why do I see a NCSim simulation error when using the Arria 10 Hard IP for PCI Express?

You may see the error below in NCSim when using the Arria® 10 Hard IP for PCI Express®, due to a missing timescalencelab: *F,CUMSTS: Timescale directive missing on one or more modu…
www.altera.com/support/kdb/solutions/rd04112014_359.html - 2014-04-15

2014-04-15 130001 13.0 SP1 130103 13.1
Update3
Error (12012): Port direction mismatch for entity "altpcie_sv_hip_avmm_hwtcl:pcie_avgz_hip_avmm_0" at port "tlbfm_out[0]". Upper entity is expecting "Output" pin while lower entity is using "Input" pin.

This error may be seen when trying to compile an Arria® V GZ or Stratix® V Hard IP for PCI Express® for the Avalon® Memory Mapped Qsys component in VHDL.This problem is due to…
www.altera.com/support/kdb/solutions/rd04012014_517.html - 2014-04-15

2014-04-15 130100 13.1 0 When does the UniPHY DDR3 IP use an I/O standard of SSTL-15 Class II ?

When the UniPHY DDR3 PHY Settings tab "Memory Clock frequency" parameter is set above 800MHz, the default DDR3 interface signal I/O standard is set to SSTL-15 Class II to increase …
www.altera.com/support/kdb/solutions/rd11132013_424.html - 2014-04-15

2014-04-15 0 0 How do I fix the core setup timing violations when I bond two DDR3 hard memory controllers from the top edge to bottom edge of the FPGA device?

When you bond two DDR3 hard memory controllers (HMC) located on the top and bottom edges and use pll_afi_half_clk as the clock for the MPFE port, you may g…
www.altera.com/support/kdb/solutions/rd03112014_680.html - 2014-04-15

2014-09-01 0 0 How do I view the external memory signals in my HPS SDRAM simulation?

The HPS simulation model does not use external memory pins to connect to the DDR2, DDR3 or LPDDR2  memory model. The actual memory model is created internally in the…
www.altera.com/support/kdb/solutions/rd04092014_381.html - 2014-04-15

2014-07-04 130100 13.1 0 Error May Occur When Generating Hard Memory Controller in Qsys

This problem affects DDR2 and DDR3 interfaces using the hard memory controller in Arria V or Cyclone V devices. When using Qsys to generate an Arria V or Cyclone V external memory…
www.altera.com/support/kdb/solutions/fb181874.html - 2014-04-14

2014-04-14 110100 11.1 0 VHDL Postfit Simulation Not Supported for Arria V and Cyclone V Designs with Hard Memory Controller

This problem affects DDR2, DDR3, and LPDDR2 products using hard memory controllers. VHDL postfit simulation is not supported for Arria V and Cyclone V designs containing hard memo…
www.altera.com/support/kdb/solutions/fb119316.html - 2014-04-14

2014-04-14 130100 13.1 0 Internal Error: Sub-system: HDB, File: /quartus/db/hdb//hdb_asgn.cpp, Line: 1571

Due to a problem in the Quartus® II software version 13.1 and later, you may see this Internal Error when compiling a design with a Quartus II Exported Partion File (.qxp)
www.altera.com/support/kdb/solutions/rd04012014_757.html - 2014-04-14

2014-04-14 0 0 Why does the Quartus II software incorrectly show “Critical Warning: Timing analysis was performed on core hps_sdram_p0 using Quartus II v13.1 with a preliminary timing model and constraints..”?

Due to a problem in the Quartus® II software version 13.1 Update 3 and later, you may see the the following critical warnings when compiling a Cyclone® V SoC HP…
www.altera.com/support/kdb/solutions/rd03172014_960.html - 2014-04-14

2014-04-14 0 0 Error (170039): Cannot place RAM cells or portions of RAM cells in the design

Due to a problem in Quartus® II software version 13.1 and earlier, you may see this fitter error if you defined nesting reserved and non-reserved regions and floating LogicLoc…
www.altera.com/support/kdb/solutions/rd04082014_701.html - 2014-04-14

2014-04-14 0 0 Does the Stratix V device family support the Enable Beneficial Skew Optimization option?

No, the Stratix® V device family does not support the Enable Beneficial Skew Optimization option.
www.altera.com/support/kdb/solutions/rd04012014_513.html - 2014-04-14

2014-04-11 0 0 Is it safe to ignore incomplete I/O assignment warning messages in the Quartus II software for Active Parallel configuration pins?

Yes, it is safe to ignore incomplete I/O assignment warning messages in the Quartus® II software, for dual purpose configuration pins that are used for Active …
www.altera.com/support/kdb/solutions/rd03312014_182.html - 2014-04-11

2014-04-11 0 0 Do the PowerPlay Early Power Estimators (EPE) which incorporate the Enpirion integrated solution add margin to the load current that is estimated?

Yes, EPEs which incorporate the Enpirion® integrated solution report the total summed currents with an additional 30% margin. Please see the tooltip on cell labelled “Lo…
www.altera.com/support/kdb/solutions/rd04102014_752.html - 2014-04-11

2014-04-09 120100 12.1 0 NativeLink Simulation of DDR2, DDR3, and LPDDR2 Interfaces Fails for ModelSim AE and ModelSim SE

This problem affects DDR2, DDR3, and LPDDR2 products. When you attempt to simulate a DDR2, DDR3, or LPDDR2 design using NativeLink with ModelSim or ModelSim-Altera, NativeLink fai…
www.altera.com/support/kdb/solutions/fb77918.html - 2014-04-09

2014-04-08 130100 13.1 0 Why does the tx_datak signal refer to received data for the Arria V, Cyclone V and Stratix V devices in the Altera Transceiver PHY IP User Guide?

Due to mistakes in "Table 9-12: Avalon-ST TX Interface Signals" and "Table 11-8: Avalon-ST TX Interface" of the Altera® Transceiver PHY IP Core User Guide (PDF) the tx_datak s…
www.altera.com/support/kdb/solutions/rd03032014_187.html - 2014-04-08

2014-04-08 130100 13.1 0 Why does the Arria 10 device Transceiver PHY User Guide (PDF) describe the tx_datak signal as '1' for a data word and '0' as a control word?

Due to a mistake in "Table 2-40: TX Standard PCS: Data, Control, and Clocks" of the Arria® 10 device Transceiver PHY User Guide (PDF) the tx_datak signal is described as being '1' …
www.altera.com/support/kdb/solutions/rd03032014_183.html - 2014-04-08

2014-04-07 0 0 Error: Standard RX/TX PCS Parameter 'hd_pcs8g_digi_rx/tx_byte_deserializer' is set to an illegal value of 'en_bds/bs_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom.

You may see the following Quartus® II software fitter error when using the transceiver PHY instance and the “enable Byte Serializer/Deserializer with 16- and 20-Bit PMA-PCS Widths”…
www.altera.com/support/kdb/solutions/rd03172014_8.html - 2014-04-07

2014-12-02 130100 13.1 0 Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria V GZ, and Stratix V GX/GT devices?

The tx_cal_busy signal will not assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ, and Stratix® V GX/GT devices. The tx_cal_busy s…
www.altera.com/support/kdb/solutions/rd03052014_988.html - 2014-04-07

2014-04-07 0 0 Why is the input common mode voltage (VICM) of the Arria II GX dedicated transceiver refclk pins lower than the 1.1V device specification?

Due to a problem in the Quartus® II software version 13.1 and earlier, the input common mode voltage (VICM) of the Arria® II GX dedicated transceiver refclk pins with on-chip…
www.altera.com/support/kdb/solutions/rd02242014_573.html - 2014-04-07

2014-04-07 130100 13.1 0 Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic.

You may encounter the following warnings with the XAUI PHY IP in Arria® V GZ and Stratix® V devices during the Quartus® II software version 13.1 compilation: Warning (12…
www.altera.com/support/kdb/solutions/rd12262013_338.html - 2014-04-07

2014-04-07 120101 12.1 SP1 0 How do I disable the transceiver On-Chip-Termination (OCT) of the Stratix IV GT device 10GBase-R PHY IP?

You can disable the transceiver On-Chip-Termination (OCT) of the Stratix® IV GT device 10GBase-R PHY IP by following the steps below. Open the MegaWizard™ generated siv_xcvr_low…
www.altera.com/support/kdb/solutions/rd04102013_210.html - 2014-04-07

2014-04-07 0 0 How are the IO pins that migrate to NC configured by the Quartus II software, when compiling a design targeting Arria V, Cyclone V or Stratix V devices, with migration devices selected?

When compiling a design targeting Arria®  V, Cyclone®  V or Stratix®  V devices, with migration devices selected, IO pins that migrate to NC will be configured as …
www.altera.com/support/kdb/solutions/rd04042014_245.html - 2014-04-07

2014-06-29 0 0 How can I enable transceiver polarity inversion in the 10GBASE-R PHY IP for Arria V GZ and Stratix V GX devices?

You can enable transceiver polarity inversion in the 10GBASE-R PHY IP for Arria® V GZ and Stratix® V GX devices by following the sequence below. Generate the 10GBase-R PHY …
www.altera.com/support/kdb/solutions/rd03272014_29.html - 2014-04-07

2014-04-04 100101 10.1 SP1 0 Why do I get this and similar warning messages in Qsys: pcie_internal_hip.rc_rx_analogreset must be exported, or connected to a matching conduit?

Starting in Quartus® II software version 10.1 SP1, there were changes to the implementation of the PCI Express® IP when using Qsys and SOPC Builder.  The changes implemented c…
www.altera.com/support/kdb/solutions/rd08182011_29.html - 2014-04-04

2014-04-04 130000 13.0 0 Why is the reported center DQS enable calibration result outside of the start - end range when the runtime calibration report is enabled for the HPS external memory controller?

Due to a probem in the HPS SDRAM Controller calibration algorithm generated by the Altera SoC Embedded Design Suite for Cyclone® V SoC and Arria® V SoC&nbs…
www.altera.com/support/kdb/solutions/rd02102014_671.html - 2014-04-04

2014-04-04 100101 10.1 SP1 0 Why do I get the following warning message in Qsys: pcie_internal_hip.pice_core_clk cannot be both connected and exported?

Starting in Quartus® II software version 10.1 SP1, you may see this warning message, even though you are not both connecting and exporting these signals.  You may also see&nb…
www.altera.com/support/kdb/solutions/rd08182011_364.html - 2014-04-04

2014-04-04 0 0 Is it possible to connect ADCGND directly to GND on Arria 10 devices, when the voltage sensor and temperature sensing diode features are not used?

No. ADCGND pins on Arria® 10 devices should be connected to a separate board ground plane from GND, or to GND via a proper isolation filter, even if t…
www.altera.com/support/kdb/solutions/rd03312014_553.html - 2014-04-04

2014-04-04 110100 11.1 0 How do I constrain the Serial RapidIO IP core when implementing multiple instances in a Qsys system?

When you generate a Qsys system that contains the Serial RapidIO® IP, Qsys generates a (.tcl) script and Synopsys Design Constraint(.sdc) file for your IP. The .sdc file does not w…
www.altera.com/support/kdb/solutions/rd01302014_527.html - 2014-04-04

2014-06-18 0 0 How do I set up the environment variables so I can launch the Altera device development kit GUI?

The Altera® device development kit (Board Test System (BTS), CLK, and Power) GUIs heavy rely on the Quartus® II software version due to specific library requirements. Unlike o…
www.altera.com/support/kdb/solutions/rd01292013_416.html - 2014-04-04

2014-04-04 0 0 Why do I get warnings for my correctly configured PCI Express core in Qsys?

When instantiating a IP Compiler for PCI Express® core within Qsys, the following warnings can appear, even though the core is configured and connected correctly: Warning: System.…
www.altera.com/support/kdb/solutions/rd11172011_691.html - 2014-04-04

2014-04-04 0 0 Can alternative Ra/Rb resistor values be used instead of those recommended by Altera even if they derive the same ratio, when using Enpirion EN5364 or EN5322 devices?

No. Ra is part of the loopback circuitry of the Enpirion® EN5364 and EN5322 devices and therefore Altera® does not recommend deviating from the recommended resistor values that can…
www.altera.com/support/kdb/solutions/rd03312014_647.html - 2014-04-04

2014-04-04 120101 12.1 SP1 0 Why do I see incorrect read data when using a Hard Memory Controller with multiple MPFE ports?

When performing write and read transactions to the hard memory controller (HMC) MPFE ports, you may observe that the read transactions are performed before the write transactions e…
www.altera.com/support/kdb/solutions/rd09242013_535.html - 2014-04-04

2014-04-04 0 0 When selecting "Use differential mode" in the ALTIOBUF megafunction and using differential SSTL or HSTL IO standards, will the output buffer be implemented as a true differential buffer?

No, differential SSTL or HSTL outputs can only be implemented as single-ended pseudo-differential outputs. However, SSTL and HSTL differential input buffers are…
www.altera.com/support/kdb/solutions/rd04032014_345.html - 2014-04-04

2014-04-04 0 0 ** Warning: nofile(37): in protected region.

You may experience the above warning while simulating a VHDL-based DDR3 UniPHY memory controller with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog an…
www.altera.com/support/kdb/solutions/rd12162013_873.html - 2014-04-04

2014-04-03 130100 13.1 0 WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU has no memories connected to its Avalon master(s)

Due to a problem in the Quartus® II software version 13.1, users cannot dynamically set the Address Span expander to be / not be visible as memory for the Nios® II i…
www.altera.com/support/kdb/solutions/rd03182014_17.html - 2014-04-03

2014-04-02 130100 13.1 0 How do I connect aud_z signal from SDI Audio Extract MegaCore?

The aud_z signal from the Altera® Serial Digital Interface (SDI) Audio Extract MegaCore® is not required.   You can ignore this signal. 
www.altera.com/support/kdb/solutions/rd03122014_224.html - 2014-04-02

2014-04-02 130100 13.1 0 How do I enable serial loopback in Serial RapidIO IP core?

In the Quartus® II software version 13.1 and earlier, the Serial RapidIO® IP core does not have a register or a port in top level module that enables serial loopback.
www.altera.com/support/kdb/solutions/rd03042014_469.html - 2014-04-02

2014-04-02 0 0 Why does my third-party PCI Express Bus Functional Model (BFM) flag invalid symbol after End of Data Stream (EDS) token?

The Arria® V GZ and Stratix® V Hard IP for PCI Express® may cause third party BFMs to flag invalid symbol after EDS for the following reason: When the Hard IP for PCI Ex…
www.altera.com/support/kdb/solutions/rd01302014_94.html - 2014-04-02

2014-07-22 0 0 Why can't I simulate the Arria II IP Compiler for PCI Express in Quartus 13.1?

HardCopy® IV and Stratix® II support was removed from 13.1. You may see an error such as that shown below: # ** Error: (vlog-7) Failed to open design unit file "/tools/acds/1…
www.altera.com/support/kdb/solutions/rd04012014_271.html - 2014-04-02

2014-04-02 0 0 Why does my Stratix V Hard IP for PCI Express in Gen3 configuration fail to link up to L0 after toggling pin PERST in simulation?

When simulating Stratix® V and Arria® V GZ Hard IP for PCI Express® as an Endpoint, the PCIe Hard IP can become stuck at Speed.Recovery if the Hard IP is reset …
www.altera.com/support/kdb/solutions/rd02242014_943.html - 2014-04-02

2014-04-02 0 0 What is the maximum payload size supported in Stratix V Hard IP for PCI Express?

Due to a documentation error, the table Dynamically Reconfigurable Registers in the Hard IP Implementation of the Stratix® V Hard IP for PCI Express® User Guide shows a 4096 byte m…
www.altera.com/support/kdb/solutions/rd03272014_687.html - 2014-04-02

2014-04-02 0 0 Line <line> : Invalid data rate! Cell value must be between 0.0 and 1434.0 Skipping!

You may see this error when importing a Quartus® II generated PowerPlay Early Power Estimator (EPE) File into the EPE tool version 13.1 and earlier, for a Stratix® V desi…
www.altera.com/support/kdb/solutions/rd04022014_893.html - 2014-04-02

2014-04-02 0 0 Why can't I observe any activity on the Triple Speed Ethernet MegaCore Function’s RGMII_OUT signals in the SignalTap II Logic Analyzer?

The RGMII_OUT registers are implemented using Alt DDIO_OUT atoms which cannot be observed using SignalTap™ as a routing path to the core is not possible. Hence it is not …
www.altera.com/support/kdb/solutions/rd03122014_936.html - 2014-04-02

2014-03-28 130100 13.1 0 Example Code Error in Nios II Processor Reference Handbook, Application Binary Interface Chapter

In the Application Binary Interface chapter of the Nios II Processor Reference Handbook, Example 7-3 (“Returned struct is Larger than 8 Bytes”) contains a typographical error. *va…
www.altera.com/support/kdb/solutions/fb141549.html - 2014-04-01

2014-03-28 120100 12.1 0 Unexplained Errors After Compilation in Nios II Software Build Tools for Eclipse

After compiling a project with the Nios II Software Build Tools for Eclipse, you might encounter a <function/symbol> could not be resolved message, or unexpected error marke…
www.altera.com/support/kdb/solutions/fb91565.html - 2014-04-01

2014-04-03 0 0 How do I resolve timing violations on the quarter rate to half rate clock transfer in my UniPHY-based DDR3 controller design?

When the UniPHY DDR3 controller in quarter rate mode is operated at or near the maximum frequencies specified in the External Memory Interface Spec Estimator Tool (HTML), you may s…
www.altera.com/support/kdb/solutions/rd03262014_301.html - 2014-03-31

2014-03-31 0 0 Why are the assignments via altera_attribute not being applied correctly?

Due to a problem in the Quartus® II software version 13.1 and earlier, the Verilog HDL synthesis attribute may not be processed correctly if you were using pragma-style attributes.…
www.altera.com/support/kdb/solutions/rd03132014_457.html - 2014-03-31

2014-03-31 0 0 Internal Error: Sub-system: GIOQ, File: /quartus/edt/gioq/gioq_port.cpp, Line: 696

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when you double click on any port connection wire in a Block Design File (.bdf).
www.altera.com/support/kdb/solutions/rd02232014_760.html - 2014-03-31

2014-03-26 130100 13.1 130101 13.1
Update1
Introduction to the Hard Processor System Contains Incorrect Addresses

The Introduction to the Hard Processor System chapter of Volume 3: Hard Processor System Technical Reference Manual in the Arria V Device Handbook and Cyclone V Device Handbook co…
www.altera.com/support/kdb/solutions/fb167123.html - 2014-03-31

2014-03-27 130001 13.0 SP1 130100 13.1 Spurious Error Messages from sopc2dts

When you are generating the device-tree source file (.dts) for an SoC HPS hardware design, you might see a large number of spurious error messages. The following list shows some …
www.altera.com/support/kdb/solutions/fb127751.html - 2014-03-31

2014-03-31 130100 13.1 0 How do I specify the web browser in the Quartus II software version 13.1 and later?

In the Quartus® II software version 13.1 and later, the Tools > Options > Web Browser setting has been removed and the software uses the default web browser specifi…
www.altera.com/support/kdb/solutions/rd12132013_991.html - 2014-03-31

2014-03-31 0 0 Package effects when probing at the FPGA pin

When comparing signals probed at the memory device and the FPGA pins, it is observed on the oscilloscope that the signals at the FPGA pins have severe reflections when co…
www.altera.com/support/kdb/solutions/rd03182014_79.html - 2014-03-31

2014-03-31 0 0 Why does the fitter report display Use as programming pin for nCEO regardless of Dual purpose pin settings?

Due to a problem in the Quartus® II software, the fitter report the Dual Purpose and Dedicated Pins section incorrectly displays Use as programming pin for the …
www.altera.com/support/kdb/solutions/rd03102014_780.html - 2014-03-31

2014-03-26 70201 7.2 SP1 100000 10.0 Windows Vista: Limited Support in Nios II EDS

The Quartus II software introduced Windows Vista (32-bit and 64-bit) support in version 7.2. However, 7.2SP1 and several ensuing releases of the Nios II Embedded Design Suite supp…
www.altera.com/support/kdb/solutions/spr257471.html - 2014-03-31

2014-03-31 130200 13.1
Arria 10
Edition
0 Error (12595): Design Assistant information: Design Assistant does not support current family.

Due to a Problem in the Quartus® II software version 13.1 A10, you may see the following error when you compile an Arria® 10 design with Design Assistant enabled. E…
www.altera.com/support/kdb/solutions/rd03252014_863.html - 2014-03-31

2012-06-26 130001 13.0 SP1 130100 13.1 Spurious Error Messages from sopc2dts

When you are generating the device-tree source file (.dts) for an SoC HPS hardware design, you might see a large number of spurious error messages. The following list shows some …
www.altera.com/support/kdb/solutions/fb127751.html - 2014-03-31

2014-03-28 110000 11.0 110100 11.1 Why does my PCI Express end point design, using legacy interrupts, send the "Deassert_INTA" message immediately after the “Assert_INTA” message, when signal Rxmirq_irq[n] is still asserted?

Due to a problem with the PCI Express® core implementation in the Quartus® II software, the Deassert_INTA message may be sent out shortly after the Assert_INTA message, while the R…
www.altera.com/support/kdb/solutions/rd10062011_172.html - 2014-03-28

2014-03-26 130100 13.1 0 Many New Warnings in Altera HAL Code with GCC 4.7.3

Upgrading from GCC 4.1.3 to GCC 4.7.3 generates more warnings than before. You are likely to see more warning messages when compiling Altera’s BSP code.
www.altera.com/support/kdb/solutions/fb145297.html - 2014-03-28

2014-03-28 0 0 Why are interrupts not working in my PCI Express End Point

When using the Altera® IP Compiler for PCI Express®, interrupts will not work for all configurations of the IP, except for completer only single dword variants, if the CR…
www.altera.com/support/kdb/solutions/rd03282014_331.html - 2014-03-28

2014-03-27 0 0 Why are RESPONSE packets from the RapidIO I/O Write Master dropped?

The RESPONSE packets to NWRITE_R packets may be dropped by the I/O Write Master within the RapidIO® MegaCore® function when there is insufficient bandwidth on the Transport Layer t…
www.altera.com/support/kdb/solutions/rd03242014_446.html - 2014-03-27

2014-03-25 130000 13.0 0 DS-5 Not Installed with SoC EDS Installation on Linux

If the xterm package is not installed before installing SoC EDS, the DS-5 installation is not launched at the end of the SoC EDS installation on Linux.
www.altera.com/support/kdb/solutions/fb113913.html - 2014-03-27

2014-04-01 0 0 Which exposed pads represent VCC or GND pads for a 148 pin QFN package?

The middle pad (Yellow) represents the ground pad while the side pad (Red) represents the  core VCC pad which is VCCINT.  
www.altera.com/support/kdb/solutions/rd11212012_540.html - 2014-03-25

2014-03-21 130100 13.1 130102 13.1
Update2
Memory Parameter Presets May Not Appear in Parameter Editor

This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products. When using the Quartus II software version 13.1, and targeting an Arria V, Cyclone V, or Stratix V devi…
www.altera.com/support/kdb/solutions/fb191203.html - 2014-03-24

2014-03-24 0 0 Why are there timing violations within my Altera PLL Reconfig megafunction?

The maximum frequency for the mgmt_clk and scanclk reconfiguration clock inputs for PLL reconfiguration are specified in the respective device datasheets for Stratix® V, Arria® V a…
www.altera.com/support/kdb/solutions/rd03242014_72.html - 2014-03-24

2014-06-06 0 0 How do I access the EPCQ configuration device on the Cyclone V GT FPGA Development Kit?

The MAX® V design provided with the Cyclone® V GT FPGA development kit does not allow you to access the EPCQ configuration device that is fitted …
www.altera.com/support/kdb/solutions/rd02112014_88.html - 2014-03-21

2014-11-20 130100 13.1 0 Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1

Due to a problem in the Quartus II software, the Quartus Programmer must be used to program EPCQ devices using a generated .jic file in order to enable 4 bytes …
www.altera.com/support/kdb/solutions/rd11192013_118.html - 2014-03-21

2014-07-31 0 0 Can I use a USB Blaster download cable for AES key programming?

For device families that support non-volatile AES key programming for design security, you will need to use either an EthernetBlaster, EthernetBlaster II or USB…
www.altera.com/support/kdb/solutions/rd01032008_684.html - 2014-03-21

2014-03-21 0 0 How is the on-board USB-Blaster II powered?

The on-board USB-Blaster™ II solution is powered via your PCB JTAG header pin 4 and not the USB port on your computer.
www.altera.com/support/kdb/solutions/rd03292013_938.html - 2014-03-21

2014-03-21 0 0 How do I download the latest version of the Board Skew Parameter Tool?

The 'Board Skew Parameter Tool' can be downloaded using the following link:Board Skew Parameter Tool (.HTML)This tool enables you to calculate the board skew parameter values requi…
www.altera.com/support/kdb/solutions/rd10232012_771.html - 2014-03-21

2014-04-20 120100 12.1 0 Is there a known issue with the mif file generated for PLL reconfiguration, for Arria V, Cyclone V and Stratix V devices?

Yes, when the Altera_PLL Megawizard is used to generate a Memory Initialization File (.mif) for Arria® V, Cyclone® V or Stratix® V devices, the generated file will contain the…
www.altera.com/support/kdb/solutions/rd02242014_46.html - 2014-03-21

2014-03-20 90102 9.1 SP2 110000 11.0 Nios II Options Do Not Appear in Eclipse

When Nios® II SBT for Eclipse starts, the Nios II plugins might fail to load, resulting in the following symptoms: The Nios II perspective is not availab…
www.altera.com/support/kdb/solutions/rd08162011_378.html - 2014-03-20

2014-07-04 130000 13.0 0 Which clock is the reference clock for HPS Ethernet MDC clock?

The correct reference clock for HPS Ethernet clock is l4_mp_clk. The V HPS Address Map, emac->gmacgrp->GMII_Address->cr incorrectly states the CSR clock range select…
www.altera.com/support/kdb/solutions/rd03132014_729.html - 2014-03-20

2014-03-20 130100 13.1 0 Why doesn't the Frame Buffer IP generate a simulation model?

Due to a problem in the Quartus® II software for Linux version 13.1, the MegaWizard™ Plug-In Manager fails to generate a simulation model for the Frame Buffer IP and issues the fol…
www.altera.com/support/kdb/solutions/rd03062014_597.html - 2014-03-20

2014-03-20 130001 13.0 SP1 130100 13.1 Why can't I see any SDRAM Presets in QSYS Hard Processer System Megawizard?

Due to a problem in the Quartus® II software version 13.0SP1,  DDR presets are not visble in the SDRAM tab of the HPS megawizard.
www.altera.com/support/kdb/solutions/rd12102013_700.html - 2014-03-20

2014-03-20 90100 9.1 0 Why does my Nios II software crash unexpectedly when using MicroC/OS-II with Vectored Interrupt Controller(VIC) ?

The Vectored Interrupt Controller (VIC) is not currently supported for use with MicroC/OS-II  based systems.  The Nios II MicroC/OS-II multitasking kernel&…
www.altera.com/support/kdb/solutions/rd02162014_886.html - 2014-03-20

2014-03-31 130100 13.1 0 Why don't I see the h2f_rst_n signal assert in HPS simulation?

Due to a problem in the Quartus® II software BFM simulation model, asserting the "h2f_rst_n" signal does not drive the "h2f_rst_n" signal. This causes unexpecte…
www.altera.com/support/kdb/solutions/rd02042014_881.html - 2014-03-20

2014-03-20 130000 13.0 130100 13.1 Why do I see errors when compiling the Video Sync Generator in Quartus II 13.0 and 13.0sp1.

Due to a problem in the Quartus® II software version 13.0 and 13.0sp1,  the Video Sync Generator component does not declare HDL parameters for Qsys systems generated in Verilo…
www.altera.com/support/kdb/solutions/rd11262013_466.html - 2014-03-20

2014-03-20 0 0 Why does my Nios II processor simulation fail when the data cache line size is set to 4 bytes?

You may encounter a simulation failure with the Nios® II processor when the data cache line size is set to 4 bytes.  The failures you may observe are: Failing to dis…
www.altera.com/support/kdb/solutions/rd02172014_343.html - 2014-03-20

2014-07-04 130000 13.0 0 What is the maximum baud rate on the HPS UART?

The Cyclone ® V Device Handbook contains conflicting information regarding the maximum baud rate regarding the internal UART.
www.altera.com/support/kdb/solutions/rd12132013_749.html - 2014-03-20

2014-03-20 130100 13.1 0 How do I connect the detected_rate and detected_rate_in signals from the Serial Digital Interface (SDI) MegaCore?

The detected_rate signal is available when you generate the SDI MegaCore® in Transceiver Only configuration.The detected_rate_in signal is available when you generate t…
www.altera.com/support/kdb/solutions/rd03122014_306.html - 2014-03-20

2014-03-20 130000 13.0 130100 13.1 Why does the Lauterbach memory watch window display inconsistent values ?

Due to a problem in the Quartus II software version 13.0, the data display in the Lauterbach memory watch window is not consistent due to an arbitration logic bug that causes …
www.altera.com/support/kdb/solutions/rd03192014_964.html - 2014-03-20

2014-03-20 0 0 Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_logical_physical_mapping.cpp, Line: 562

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error if your Arria® V design includes the Altera® Serial Digital Interface (SDI) II Megacor…
www.altera.com/support/kdb/solutions/rd03062014_292.html - 2014-03-20

2014-03-20 100000 10.0 100100 10.1 Run Configuration Cannot Find Imported Custom Makefile Project

After you import a project using the Import Custom Makefile for Nios II Software Build Tools Project option, the Nios II SBT fails to recognize the imported custom…
www.altera.com/support/kdb/solutions/rd08162011_501.html - 2014-03-20

2014-03-20 130000 13.0 0 Why do my make files fail in Altera ARM DS-5 on Windows?

If the ARM Development Studio™ 5 (DS-5™) Altera Edition Toolkit eclipse is launched from the DS-5 Windows Start Menu group,  any scripts or Makefiles will run in a DOS co…
www.altera.com/support/kdb/solutions/rd07042013_512.html - 2014-03-20

2014-03-19 130100 13.1 0 Why is timing not closing in my Stratix V Hard IP for PCI Express on Quartus 13.1?

Timing may not closing in the Stratix® V Hard IP for PCI® Express because constraints are missing on internal clocks that are in separate domains.
www.altera.com/support/kdb/solutions/rd03052014_71.html - 2014-03-19

2014-03-19 110100 11.1 0 Error: System.DUT.config_tl/APPS.config_tl: Signal tl_cfg_sts has width 73 on DUT.config_tl, but has width 123 on APPS.config_tl

In Arria® V and Cyclone® V Hard IP for PCI Express reference designs, if you set the parameter 'Number of functions' to a value greater than one in the APPS (Altera's DMA) componen…
www.altera.com/support/kdb/solutions/rd03032014_155.html - 2014-03-19

2014-04-10 130100 13.1 0 Why does the simulation script for the PCIe HIP chaining_dma example design fail?

Due to a problem in the Quartus® II software version 13.1, the simulation script generated for the PCIe HIP chaining_dma example design fails because it uses the Stratix® II and Ha…
www.altera.com/support/kdb/solutions/rd03052014_334.html - 2014-03-19

2014-03-13 120100 12.1 130000 13.0 Long Locking Time when Switching between HD and 3G in SDI II IP Core in Stratix V and Arria V Devices

A long locking time occurs when switching between high definition (HD) and third-generation (3G) in the serial digital interface (SDI) II core for Stratix V and Arria V devices.
www.altera.com/support/kdb/solutions/fb86360.html - 2014-03-14

2014-03-13 130000 13.0 130100 13.1 Cyclone V SoC and Arria V SoC Hard Processor System SDRAM calibration fails with the Quartus II software versions 13.1.1 and 13.1.2

When the HPS preloader is compiled from handoff files generated by the Quartus® II software versions 13.1.1 and 13.1.2, SDRAM calibration will fail immediately in Stage 1…
www.altera.com/support/kdb/solutions/rd02272014_719.html - 2014-03-13

2014-03-13 130100 13.1 0 Why does the Gen3 x8 AVMM 256-bit DMA design hang when the host attempts to perform two accesses in a row to the descriptor controller interface?

In Quartus® II software version 13.1, you may see the Hard IP for PCI Express® using Avalon® Memory-Mapped interface with DMA design crash if the descriptor controller in…
www.altera.com/support/kdb/solutions/rd03052014_175.html - 2014-03-13

2014-03-20 130100 13.1 0 Error (11802): Can't fit design in device.

You may encounter the following fitter error when compiling a 16-bit DDR3 hard memory controller design in a Cyclone® V A5 device with the Quartus II softw…
www.altera.com/support/kdb/solutions/rd03062014_997.html - 2014-03-13

2014-03-13 0 0 Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command

Information messages regarding clock uncertainty may be seen in some UniPHY IP applications. Info (332171): The following clock uncertainty values are less than the recommended val…
www.altera.com/support/kdb/solutions/rd01072013_565.html - 2014-03-13

2014-03-12 130100 13.1 0 Can I use TK from System Console?

Yes, the TK libraries and functions can be used from System Console.
www.altera.com/support/kdb/solutions/rd01212014_911.html - 2014-03-12

2014-03-12 90100 9.1 0 Why can I not accelerate my floating point division using the Floating Point Divider Custom Instruction

There is currently a known issue where Nios® II Software Build tool for Eclipse (SBT4E) does not automatically add the "-mcustom-fpu-cfg=60-2" flag even if your design created wi…
www.altera.com/support/kdb/solutions/rd08222011_115.html - 2014-03-12

2014-03-12 110001 11.0 SP1 130000 13.0 Why do I not see interrupts on the Scatter Gather DMA controller when writing zero to the MAX_DESCRIPTOR_PROCESSED field?

An issue has been identified in the Scatter Gather DMA that prevents the interrupt ocurring when MAX_DESC_PROCESSED field is set to 0.
www.altera.com/support/kdb/solutions/rd11082011_653.html - 2014-03-12

2014-03-31 0 0 How can I re-host my DS 5 AE License?

DS-5 Altera Edition licenses are  'FIXED' and node-locked. If  you need to transfer your license to a new machine, you must ask ARM to do the 're-host'.&nb…
www.altera.com/support/kdb/solutions/rd02132014_454.html - 2014-03-12

2014-03-11 0 0 How do I use the CHANGE_EDREG instruction to simulate a CRC error in Stratix, Stratix II, Arria GX, and Cyclone II and later series devices?

You can download the contents required to create a crc.jam file and follow the instructions below to issue the CHANGE_EDREG instruction to simulate a CRC e…
www.altera.com/support/kdb/solutions/rd01152010_577.html - 2014-03-11

2014-06-29 130100 13.1 0 Error (12848): "REF10GCLK" is locked to right side. There is no HSSI strip on right side.

Due to a bug in the Quartus® II software version 13.1, you may see the Fitter error above.
www.altera.com/support/kdb/solutions/rd02092014_966.html - 2014-03-11

2014-03-11 130000 13.0 0 Warning: New Pin Type Dedicated Clock

You may see this message when generating a Boundary Scan Description Language (BSDL) file in the Quartus® II software, for your design. This message requires no action from t…
www.altera.com/support/kdb/solutions/rd03102014_341.html - 2014-03-11

2014-06-30 130001 13.0 SP1 0 Why doesn't the "set_parameter -name pma_bonding_master" Quartus Settings File (.qsf) assignment have an effect in the Quartus II software version 13.0sp1 for Arria V, Cyclone V, or Stratix V devices?

Due to a problem in the Altera® Transceiver PHY IP Core User Guide (PDF) version 2013.7.1, the "set_parameter -name pma_bonding_master" Quartus® Settings File (.qsf) assignment wil…
www.altera.com/support/kdb/solutions/rd10312013_951.html - 2014-03-11

2014-03-10 0 0 How do I use the Configuration via Protocol (CvP) Update with Revision Flow in a source controlled environment?

To use the CvP Update with Revision Flow in a source controlled environment with multiple team members: 1) Create an archive (QAR) of the base revision which include…
www.altera.com/support/kdb/solutions/rd03042014_441.html - 2014-03-10

2014-03-10 120100 12.1 0 Internal Error: Sub-system: FTITAN, File: /quartus/fitter/ftitan/ftitan_expert.cpp, Line: 4431

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error in designs that implement the altlvds_rx megafunction with the Use External PLL option…
www.altera.com/support/kdb/solutions/rd03052014_169.html - 2014-03-10

2014-03-07 130100 13.1 0 Which device families have been removed from the Quartus II software starting with version 13.1?

The Quartus® II software version 13.1 no longer supports the following devices: MAX® 3000A, MAX 7000AE, MAX 7000S, MAX 7000B devices HardCopy II, HardCopy III, HardCopy IV (E/G…
www.altera.com/support/kdb/solutions/rd08252013_188.html - 2014-03-07

2014-11-03 110100 11.1 0 Why is the addressing incorrect for the CRA port on the Hard IP for PCI Express?

The Qsys address translation for the CRA port on the Avalon®-MM Hard IP for PCI Express® is incorrect when using VHDL as the generation language.This problem do…
www.altera.com/support/kdb/solutions/rd03062014_662.html - 2014-03-07

2014-03-07 0 0 Why do a small number of GND pins in the pin-out files of Stratix V, Arria V or Cyclone V devices have IO bank designations, whilst the rest do not?

GND pins that have bank designations in the pin-out files of Stratix® V, Arria® V or Cyclone® V devices are defined as Programming Ground pins. They should be treated like all…
www.altera.com/support/kdb/solutions/rd03072014_712.html - 2014-03-07

2014-03-04 130000 13.0 0 In Qsys why are the Triple Speed Ethernet IP core clock names not described in the User Guide?

The Triple Speed Ethernet User Guide describes the clock names used in the MegaWizard® configuration. Qsys uses the following clock names: control_port_clock_…
www.altera.com/support/kdb/solutions/rd02102014_389.html - 2014-03-04

2014-03-04 0 0 How do I modify the UniPHY example driver to run continuously?

By default, the driver only runs once when you use the UniPHY example project. To make the driver run continuously, modify the driver file at the location "<variation_name&…
www.altera.com/support/kdb/solutions/rd09262013_405.html - 2014-03-04

2014-03-11 130100 13.1 0 How do I simulate bi-directional signals with dynamic OCT with the Quartus® II software generated IBIS file ?

For software versions before Quartus II 13.1, the flow for simulating the input side of a bidirectional pin with dynamic on chip termination (OCT) is described in solution :http://…
www.altera.com/support/kdb/solutions/rd02142014_604.html - 2014-03-04

2014-03-04 0 0 When using the Stratix V Hard IP for PCI Express, why is the No Command Completed Support (bit 18) of the Slot Capability Register incorrectly set?

Due to a problem in the Stratix® V Hard IP for PCI® Express, this bit is incorrectly set.
www.altera.com/support/kdb/solutions/rd02212014_517.html - 2014-03-04

2014-07-04 0 0 Error : exception in thread java.lang.outOfMemoryError: java heap space

You may receive this error message when running System Console, due to the memory requirements of System Console exceeding the maximum heap size allocated to the Java VM. When…
www.altera.com/support/kdb/solutions/rd07022013_686.html - 2014-03-03

2014-03-03 100000 10.0 130100 13.1 Error: add_fileset_file: No such file C://qsys/_p0_sequencer_rom.hex

Due to a problem in the Quartus II software version 10.0 and later, the generation of a UniPHY core may error out with the above message. Error: add_fileset_file: No such file C:/…
www.altera.com/support/kdb/solutions/rd05242013_29.html - 2014-03-03

2014-02-28 0 0 Why does my third-party PCI Express BFM report an error for TX EIOS to Electrical Idle (TTX-IDLE-SET-TO-IDLE) timing violation?

When simulating the Altera® Hard IP for PCI Express® as endpoints with third-party BFMs, a simulation error may be reported for the time between sending out EIOS and entering Elect…
www.altera.com/support/kdb/solutions/rd12052013_482.html - 2014-02-28

2014-02-28 0 0 Can the unencrypted peipheral image for use with CvP be used when the anti-tamper bit is set?

When using Configuration via Protocol (CvP) Initialization mode, the periphery image generated by the Convert Programming Files tool is unencrypted.When the anti-tamper bit is set …
www.altera.com/support/kdb/solutions/rd02242014_962.html - 2014-02-28

2014-02-28 130100 13.1 0 ERROR: The attributes for bit 'rdynamic_sw' have illegal conflicting values

Due to a problem in the Stratix® V and Arria® V GZ HSSI PMA model, you may see this reported error when simulating the Hard IP for PCI Express® with the QuestaSim® or NC-Sim® …
www.altera.com/support/kdb/solutions/rd02282014_373.html - 2014-02-28

2014-02-28 100100 10.1 0 How do I force an update of the configuration RAM in a MAX II or MAX V device following programming using Real-time ISP?

When MAX® II and MAX V devices are reprogrammed using a JAM file where Real-Time ISP has been enabled, the configuration RAM of the MAX device is not updated following program…
www.altera.com/support/kdb/solutions/rd02122014_737.html - 2014-02-28

2014-02-27 0 0 Rule C101: Gated clock should be implemented according to the Altera standard scheme

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design.  Rule C101: Gated clock should be imple…
www.altera.com/support/kdb/solutions/rd02262014_834.html - 2014-02-27

2014-02-27 0 0 Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power

You may see the following warning when running the Design Assistant tool in Quartus II software on your compiled HPS design. Rule C103: Gated clock does not feed at leas…
www.altera.com/support/kdb/solutions/rd02262014_41.html - 2014-02-27

2014-02-27 120100 12.1 130000 13.0 Error (15700): Termination calibration block atom "|altera_mem_if_oct_stratixv:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout

You may see the following error when you compile your design when the "Rapid recompile" option is enabled. "Error (15700): Termination calibration block atom "<your_in…
www.altera.com/support/kdb/solutions/rd06052013_224.html - 2014-02-27

2014-02-27 0 0 Rule C105: Clock signal should be a global signal

You may see the following warnings when running the Design Assistant tool in Quartus II software on your compiled HPS design. Rule C105: Clock signal should be a global …
www.altera.com/support/kdb/solutions/rd02262014_16.html - 2014-02-27

2014-02-25 130000 13.0 130001 13.0 SP1 Functions Missing From Math Library

If you build a custom embedded math library with the -mhw-mulx switch, and no other options, the Software Build Tools generate an incomplete library. Some functions, such as pow()…
www.altera.com/support/kdb/solutions/fb127626.html - 2014-02-27

2014-02-26 0 0 What is the voltage diagram for the Schmitt trigger input standard and how does it relate to VIL and VIH specifications?

A  Schmitt trigger input standard allows input buffers to respond to slow input edge rates with a fast output edge rate. Most importantly, Schmitt triggers provide hysteresis …
www.altera.com/support/kdb/solutions/rd02112014_672.html - 2014-02-26

2014-02-24 0 0 Why does Quartus II re-run Analysis and Elaboration when opening the RTL viewer?

Due to a problem in Quartus® II Software, when you open netlist viewers from the Tasks pane, Analysis and Elaboration is run before opening the design in the RTL vie…
www.altera.com/support/kdb/solutions/rd02212014_350.html - 2014-02-24

2014-02-21 100000 10.0 110100 11.1 Incorrect information about Embedded C++

The Embedded Design Handbook contains the following incorrect statement about C++ support: The HAL supports only the standard Embedded C++ subset of the full C++ language. C++ pr…
www.altera.com/support/kdb/solutions/spr361482.html - 2014-02-24

2014-02-21 60100 6.1 70200 7.2 Hardware Accelerators Remain After Deleting the Software Project

If a system contains C2H accelerators, deleting the software project that defines the accelerators does not remove the accelerators from the hardware system, and the accelerator l…
www.altera.com/support/kdb/solutions/spr189600.html - 2014-02-24

2014-02-21 100000 10.0 0 BSP Not Updated for Memory Size Changes in SOPC Builder

If you change the size of a memory in SOPC Builder, and you have a BSP previously created with v9.1 or earlier, the memory region sizes are no longer correct. Regenerating the BSP…
www.altera.com/support/kdb/solutions/spr332637.html - 2014-02-24

2014-02-21 110002 11.0 SP2 120000 12.0 Nios II Application Properties Settings Not Saved

If the active configuration is not selected on the Nios II Application Properties page, you can not save the settings set in the Nios II Application Properties page. The active co…
www.altera.com/support/kdb/solutions/fb31565.html - 2014-02-24

2014-02-21 100000 10.0 100001 10.0 SP1 Error Building Imported Project: ‘target pattern contains no %’

If your application or library makefile uses an absolute path and is generated with the GCC 3 toolchain, and you import it to the version 10.0 Nios II SBT for Eclipse using the GC…
www.altera.com/support/kdb/solutions/spr341302.html - 2014-02-24

2014-02-24 0 0 Why does Qsys fail to generate any HDL files?

Qsys will fail to generate any HDL files if a Qsys component has a name that is illegal in either VHDL or Verilog HDL. For example in VHDL a name that ends in an underscore is ille…
www.altera.com/support/kdb/solutions/rd02212014_243.html - 2014-02-24

2014-02-21 120000 12.0 0 Is it possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix V, Arria V or Cyclone V devices?

No it is not possible to  dynamically enable or disable Global Clock (GCLK) or Regional clock  (RCLK) networks that drive fPLLs in Stratix® V, Arria® V or Cyclone® V devi…
www.altera.com/support/kdb/solutions/rd02122014_616.html - 2014-02-21

2014-02-19 110000 11.0 130100 13.1 Error 129001 Compiling HPS Component

When compiling an HPS design, you might see an error message similar to the following: Error (129001): Input port DATAIN on atom \ "hps_qsys:u0|hps_qsys_hps_0:hps_0|hps_qsys_hps_0…
www.altera.com/support/kdb/solutions/fb82901.html - 2014-02-20

2014-02-19 130001 13.0 SP1 0 SoC EDS Installation Error with Previous Version of DS-5

Before you install the SoC Embedded Design Suite (EDS), you must uninstall all previous versions of DS-5. If you do not uninstall a previous DS-5 version, the SoC EDS installation…
www.altera.com/support/kdb/solutions/fb128134.html - 2014-02-20

2014-02-19 130202 13.1
Arria 10
Edition
Update 2
0 Low Latency 40-100GbE IP Core Reserved Register Accesses Hang

If you attempt to access a reserved register in the Low Latency 40-100GbE IP core through its Avalon-MM control and status interface, the transaction might not complete. More prec…
www.altera.com/support/kdb/solutions/fb181384.html - 2014-02-20

2014-02-19 130000 13.0 130100 13.1 Segmentation Fault When Registering GPIO Interrupt Handler

In the Linux implementation included with the Golden System Reference Design, if you attempt to register an interrupt handler for a nonexistent GPIO device, you will see error mes…
www.altera.com/support/kdb/solutions/fb117780.html - 2014-02-20

2014-02-19 120100 12.1 130101 13.1
Update1
SoC HPS Interface to LPDDR2 is Unsupported

LPDDR2 memory is unsupported for the Arria V SoC and Cyclone V SoC in certain releases of the Quartus II software.
www.altera.com/support/kdb/solutions/fb154450.html - 2014-02-20

2014-02-19 130202 13.1
Arria 10
Edition
Update 2
0 Low Latency 40-100GbE IP Core VHDL Model Cannot Simulate Correctly

If you generate a VHDL model for a Low Latency 40-100GbE IP core, it cannot simulate correctly.
www.altera.com/support/kdb/solutions/fb181334.html - 2014-02-20

2014-02-19 130000 13.0 130001 13.0 SP1 SDRAM ECC Disabled in Preloader

Qsys cannot generate a DDR interface in the HPS component with ECC enabled. If you try to specify such an interface, the result is an interface with no ECC. Depending on the inter…
www.altera.com/support/kdb/solutions/fb108175.html - 2014-02-20

2014-02-19 120100 12.1 0 Bus Failure using FPGA-to-SDRAM Interface

When trying to access SDRAM through the SoC’s FPGA-to-SDRAM interface, your design might experience a bus failure, resulting in either of the following symptoms: The FPGA-to-SDRAM…
www.altera.com/support/kdb/solutions/fb110286.html - 2014-02-20

2014-02-19 120100 12.1 0 Debug APB Model Instance Does Not Exist in Testbench

When you simulate the HPS component, if the debug APB interface is enabled and you attempt to reference it in your testbench, you see an error message indicating that the debug AP…
www.altera.com/support/kdb/solutions/fb100506.html - 2014-02-20

2014-02-19 130000 13.0 130100 13.1 U-Boot Times Out During FPGA Programming

On the Cyclone V SoC HPS, U-Boot might time out without completing, and report an error code of -6, indicating that the FPGA control block cannot obtain valid data. This can happe…
www.altera.com/support/kdb/solutions/fb114045.html - 2014-02-20

2014-02-19 0 0 How can I choose my own reset pin location for npor when using the soft reset controller for the Hard IP for PCI Express?

To use your own reset pin location for npor first ensure that you are using the soft reset controller by checking that hip_hard_reset_hwtcl parameter is set to …
www.altera.com/support/kdb/solutions/rd02132014_196.html - 2014-02-19

2014-02-18 0 0 WARNING: Attempting to read from uninitialized location

You may experience the above warning when running a dual rank DDR3 simulation. This warning occurs during the memory initilialization and calibration process. Uninit…
www.altera.com/support/kdb/solutions/rd01082014_306.html - 2014-02-18

2014-02-18 0 0 Why can’t I merge PLLs for two different instances of the ALTMEMPHY IP?

ALTMEMPHY calibration uses PLL reconfiguration to update PLL phases. Thus, dynamic PLL reconfiguration is required. Since each ALTMEMPHY interface must be calibrated separatel…
www.altera.com/support/kdb/solutions/rd04112013_81.html - 2014-02-18

2014-03-04 130000 13.0 0 * Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v

You may see the above error when simulating your DDR3 UniPHY controller with ModelSim. The cause of the error is the ordering of the compilation libraries in the ModelSim vsim elab…
www.altera.com/support/kdb/solutions/rd01212014_488.html - 2014-02-18

2014-12-16 140100 14.1 0 "Generate PowerPlay Early Power Estimator File" function produces incorrect transceiver data rates for the Arria 10 device

In the Quartus II software version 14.1, if you export a file for Arria 10 device designs with the Generate PowerPlay Early Power Estimator File function, the file wil…
www.altera.com/support/kdb/solutions/fb249529.html - 2014-02-16

2014-02-13 110000 11.0 0 How do I implement the half rate bridge option for connection to a full rate memory controller ?

While using the Quartus® II software  versions before 11.0, the half rate bridge option was a selectable parameter in the memory controller IP megawizard. While using&nbs…
www.altera.com/support/kdb/solutions/rd01062014_253.html - 2014-02-13

2014-02-13 0 0 How do I set the DDR3 UniPHY memory controller timing parameters from the External Memory vendor DDR3 datasheet ?

The External Memory Interface Handbook Volume 2, Section I, Chapter 9, "Implementing and Parameterizing Memory IP" has details on how to select the timing parameters but the d…
www.altera.com/support/kdb/solutions/rd01282014_876.html - 2014-02-13

2014-02-13 0 0 Can the address pins be swapped on my DDR2 or DDR3 UniPHY controller?

No, the address (mem_a) and bank address (mem_ba) signals are used for programming the mode registers in the DDR2 or DDR3 memory device during initialization. Swapping around …
www.altera.com/support/kdb/solutions/rd12182013_515.html - 2014-02-13

2014-02-13 0 0 What are the minimum memory clock frequencies supported by the UniPHY External Memory Interface IP ?

The minimum frequencies are defined either by the relevant JEDEC® standard or by component features of the FPGA device used to implement the External Memory Interface IP. If too lo…
www.altera.com/support/kdb/solutions/rd01032014_294.html - 2014-02-13

2014-09-01 0 0 Where can I find the pre-configuration and post-configuration BSDL file generation customizer for Stratix IV GX, Stratix IV GT, Stratix IV E, Arria II GX, and HardCopy® III devices?

For Stratix® IV GX, Stratix IV GT, Stratix IV E, Arria® II GX, and HardCopy® III devices the BSDL file pre-configuration and post-configuration generation is now generated and cust…
www.altera.com/support/kdb/solutions/rd10132010_113.html - 2014-02-12

2014-02-11 120100 12.1 130000 13.0 Invalid pin multiplexing configurations in HPS Qsys systems for Cyclone V SoC devices

If you create a hard processor system (HPS) in Qsys that targets a Cyclone V SoC device with the U19 package and a 484 pin count, the following peripheral pin multiplexing paramet…
www.altera.com/support/kdb/solutions/fb73715.html - 2014-02-11

2014-02-10 130100 13.1 0 Why does the Qsys interconnect has a buswidth mismatch on the burstcount signal?

Due to a problem in the Quartus® II software version 13.1, Qsys may incorrectly generate the bitwidth of burstcount signal when the Avalon-MM component uses the…
www.altera.com/support/kdb/solutions/rd02052014_584.html - 2014-02-10

2014-02-10 130100 13.1 0 Why does Design Assistant not report a rule violation when my design uses a PLL locked signal as an asynchronous reset signal?

Due to a problem in the Quartus® II software version 13.1 and earlier, Design Assistant does not report a rule violation when the locked signal of a PLL is connected directly to th…
www.altera.com/support/kdb/solutions/rd12042013_325.html - 2014-02-10

2014-02-10 120000 12.0 130000 13.0 How do I set a phase shift in degrees in the ALTPLL megafunction?

Due to a problem in the Quartus® II version 12.1 SP1 and earlier, you may see the phase shift is not applied in the ALTPLL megafunction when using the wizard. This problem occ…
www.altera.com/support/kdb/solutions/rd01122014_158.html - 2014-02-10

2014-02-13 0 0 What are the supported VCCIO and VCCPD voltage combinations for IO banks with LVDS inputs and/or outputs in Stratix V, Arria V and Cyclone V devices?

The following table illustrates supported VCCIO and VCCPD combinations for IO banks with LVDS inputs and/or outputs in Stratix®  V, Arria®  V and Cyclone®  V de…
www.altera.com/support/kdb/solutions/rd01312014_45.html - 2014-02-07

2014-11-23 130000 13.0 0 What is the difference between ‘Number of ranks per slot’ and ‘Number of chip-selects per device/DIMM’ for DDR3 RDIMM and LRDIMM?

For RDIMMs, a minimum of two chip select (CS) signals are required per RDIMM. This is necessary for RDIMM memory device programming. A single or dual rank RDIMM configuration …
www.altera.com/support/kdb/solutions/rd11122013_19.html - 2014-02-07

2014-02-07 0 0 What are the AC voltage levels that Quartus® II uses for UniPHY DDR3 and DDR3L tDS and tIS set up derating ?

The AC voltage levels depend on the value set in the Memory Parameters tab -> Memory Device Speed Grade. This speed grade and the AC voltage level shown below should be used to…
www.altera.com/support/kdb/solutions/rd01032014_56.html - 2014-02-07

2014-02-07 0 0 What are the AC voltage levels that Quartus® II uses for DDR2 and LPDDR2 tDS and tIS set up derating ?

The AC voltage levels depend on the value set in the Memory Parameters tab -> Memory Device Speed Grade and are shown below. DDR2AC250 for speed grades 200.0  & 266.66…
www.altera.com/support/kdb/solutions/rd01032014_110.html - 2014-02-07

2014-12-19 0 0 How do I implement and connect between an external Altera_PLL and an ALTLVDS_RX with Dynamic Phase Alignment (DPA) enabled?

When using ALTLVDS_RX in external PLL mode with DPA enabled in Quartus® II software versions 12.1 and later, you will receive an error in Analysis and Synthesis as shown below: Er…
www.altera.com/support/kdb/solutions/rd07192013_460.html - 2014-02-07

2014-02-06 130100 13.1 0 TOD Synchronizer Does Not Recognize Qsys-Generated Parameter Value

The TOD synchronizer in IEEE 1588v2 designs, using Triple Speed Ethernet, 10GbE MAC, or Low Latency Ethernet MAC, does not recognize certain Qsys-generated parameter values. When…
www.altera.com/support/kdb/solutions/fb166971.html - 2014-02-07

2014-02-07 120101 12.1 SP1 130100 13.1 Timing Closure for Hard LPDDR2 Interfaces May Not be Robust in Cyclone V SoC Devices

This problem affects LPDDR2 products. Hard LPDDR2 interfaces targeting Cyclone V SoC devices may have difficulty achieving timing closure.
www.altera.com/support/kdb/solutions/fb98435.html - 2014-02-07

2014-02-07 130000 13.0 0 How should I place the QDRII/QDRII+ mem_cq and mem_cq_n pins in Arria V GX/GT/ST/SX devices?

From the device pinout file, there is only one pin location available for both mem_cq and mem_cq_n pins. For these Arria V devices complementary strobes are not supported, so …
www.altera.com/support/kdb/solutions/rd01232014_943.html - 2014-02-07

2014-02-06 0 0 How can I share On Chip Termination (OCT) calibration blocks if my design exceeds the maximum available?

All I/O banks with the same VCCIO can share one OCT calibration block. If your design exceeds the maximum number of available blocks, you can try and direct the Quartus® …
www.altera.com/support/kdb/solutions/rd01142014_259.html - 2014-02-06

2014-02-06 0 0 Does Altera comply with ISO 17025?

ISO 17025 is a standard for testing and calibration laboratories to set up and adhere to quality management systems. This standard does not apply to a semiconductor …
www.altera.com/support/kdb/solutions/rd01292014_726.html - 2014-02-06

2014-02-06 130100 13.1 0 Error (15629): Atom "comb~6" is dependent on unconnected input ports

You may see the error when instantiating the Altera® PLL Reconfiguration IP and enabling physical synthesis in the Quartus® II software.
www.altera.com/support/kdb/solutions/rd01212014_425.html - 2014-02-06

2014-02-05 0 0 Arria V GZ and Stratix V PCI Express Hard IP does not reject coefficient requests properly

If the Arria® V GZ or Stratix® V Hard IP for PCI Express® receives an illegal coefficient request from a link partner during either equalization phase 2 or 3, the IP…
www.altera.com/support/kdb/solutions/rd01302014_235.html - 2014-02-05

2014-02-05 130100 13.1 0 Cadence NCSim VHDL Compilation Error for Low Latency Ethernet 10G MAC

The Cadence NCSim VHDL simulator may cause compilation error for Low Latency Ethernet 10G MAC designs. The simulator library mapping in the Qsys .spd file shows the following erro…
www.altera.com/support/kdb/solutions/fb156992.html - 2014-02-05

2014-02-05 130100 13.1 0 Does the Hard IP for PCI Express for the Avalon-MM interface with DMA support out of order completions?

When the Hard IP for PCI Express® read DMA module receives out-of-order completions, the DMA can, in certain instances, flag the descriptor completion signal too early,&n…
www.altera.com/support/kdb/solutions/rd01302014_355.html - 2014-02-05

2014-02-05 110000 11.0 0 Preamble Pass Through Mode in 10-Gbps Ethernet MAC Does Not Meet Average IPG

10GbE MAC designs with the Enable preamble pass-through mode option turned on, the average inter-packet gap (IPG) is set to 16 instead of 12. Your designs will have lower throughp…
www.altera.com/support/kdb/solutions/fb176924.html - 2014-02-05

2014-02-05 130100 13.1 130100 13.1 Are there any problems with version 13.1 of the JNEye tool when modelling the receiver of Arria 10 GX/T devices?

Yes, due to a bug in Quartus® II software version 13.1 of the JNEye tool, you may see a problem with the modelling of the receivers in Arria® 10 GX/T devices. Modelling effectiv…
www.altera.com/support/kdb/solutions/rd01132014_397.html - 2014-02-05

2014-02-05 130100 13.1 0 Why do the Arria V GZ and Stratix V Hard IP for PCI Express exit hot reset early?

The Arria® V GZ and Stratix® V Hard IP for PCI Express® exit the LTSSM state Hot Reset immediately when the soft reset controller is being used. This causes the Hard IP to exit hot…
www.altera.com/support/kdb/solutions/rd01302014_386.html - 2014-02-05

2014-02-05 130000 13.0 0 How do I implement an 8b/10b Encoder-Decoder function?

In designs targeting Arria® II GZ, Arria V, Cyclone® V and Stratix® V, refer to the Advanced Synthesis Cookbook(PDF). For earlier device families use the Altera® 8B10B Encoder-Dec…
www.altera.com/support/kdb/solutions/rd12222013_503.html - 2014-02-05

2014-02-05 130200 13.1
Arria 10
Edition
0 Low Latency Ethernet 10G MAC Designs Using Arria 10 May Fail Timing

Large designs for Low Latency Ethernet 10G MAC using Arria 10 devices may fail setup timing.
www.altera.com/support/kdb/solutions/fb156881.html - 2014-02-05

2014-02-05 130100 13.1 0 Triple Speed Ethernet with 1000BASE-X and SGMII PCS Designs Receive Wrong Number of Preamble Bytes

Triple Speed Ethernet designs using SGMII PCS and 1000BASE-X protocol will receive wrong number of preamble bytes. For 1000BASE-X protocol, the encoding of Idle periods /I2/ is …
www.altera.com/support/kdb/solutions/fb162858.html - 2014-02-05

2014-02-05 120002 12.0 SP2 0 Why are all nodes ending with *sync*/*s0* incorrectly set to set_false_path in my project when using the CPRI MegaCore Function?

Starting from Quartus® II software version 12.0, when you generate a Common Public Radio Interface(CPRI) IP in your design, an “altera_cpri.sdc” file is generated au…
www.altera.com/support/kdb/solutions/rd12112013_829.html - 2014-02-05

2014-03-31 110100 11.1 0 Why is the address translation incorrect for the Serial RapidIO Avalon-MM ports?

The address translation to the Avalon®-MM slave ports on the Serial RapidIO® MegaCore will be incorrect when using VHDL generation within Qsys. Qsys always uses vectors with …
www.altera.com/support/kdb/solutions/rd02032014_394.html - 2014-02-05

2014-02-05 0 0 Does the Stratix V Hard IP for PCI Express support L0s and L1 states?

The Stratix® V Hard IP for PCI Express® does not support the L0s or L1 states.
www.altera.com/support/kdb/solutions/rd12172013_99.html - 2014-02-05

2014-02-05 130100 13.1 0 Pause and PFC Frames Still Generated When Transmit Path is Re-Enabled

The Low Latency Ethernet 10G MAC still services Pause and PFC frame requests after the transmit path is disabled and re-enabled. The requested Pause and PFC frames will be generat…
www.altera.com/support/kdb/solutions/fb154406.html - 2014-02-05

2014-02-05 0 0 Does the Stratix V Hard IP for PCI Express support Gen3 Phase 2 and Phase 3 equalization in simulation?

The auto generated Stratix® V Hard IP for PCI Express® test bench Root Port bus functional model (BFM) bypasses Gen3 Phase 2 and Phase 3 Equalization. If using a third-p…
www.altera.com/support/kdb/solutions/rd12182013_166.html - 2014-02-05

2014-02-05 0 0 Why do I get the following error messages when building the Linux open source Configuration via Protocol driver provided by Altera?

When building the Altera® example Linux Configuration via Protocol(CvP) driver the following error messages may occur: altera_cvp.c: In function ‘altera_cvp_wait_for_bit’:alt…
www.altera.com/support/kdb/solutions/rd02042014_622.html - 2014-02-05

2014-02-05 0 0 How do I disable the scrambler for PCI Express simulations?

To disable scrambling in PCI Express® simulations do the following: 1. Open <work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/altpcie_tbed_s…
www.altera.com/support/kdb/solutions/rd12172013_276.html - 2014-02-05

2014-02-03 0 0 How do I perform VHDL simulation for the altchip_id megafunction?

The Quartus® II software version 13.1 and earlier only has VHDL simulation support for the altchip_id megafunction for the Modelsim simulator.A Verilog HDL simulation model fo…
www.altera.com/support/kdb/solutions/rd01292014_9.html - 2014-02-03

2014-02-03 0 130100 13.1 Why does the Quartus II software ignore the power up values for my inferred RAM?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, the power up values of RAM inferred from raw logic may be incorrect. This problem is specific to cases w…
www.altera.com/support/kdb/solutions/rd01272014_323.html - 2014-02-03

2014-06-24 0 0 Internal Error: Sub-system: TIS, File: /quartus/tsm/tis/tis_physical_timing_stratixv_lab.cpp, Line: 161

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error during the fitter stage of compilation of your Arria® V, Cyclone® V or Strati…
www.altera.com/support/kdb/solutions/rd01292014_563.html - 2014-02-03

2014-02-03 0 0 Error (213035): Configuration device CFI_XXXMb/NAND_XXXMb is illegal -- specify a legal configuration device

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when using the quartus_cpf command to generate a Programmer Object File(.pof). This er…
www.altera.com/support/kdb/solutions/rd01302014_177.html - 2014-02-03

2014-01-31 0 0 Do LVDS receivers in Altera devices have on-chip dc-biasing resistors?

No, LVDS receivers in Altera® devices do not have on-chip dc-biasing resistors. If you are AC-coupling between an LVDS transmitter and an LVDS receiver in an Altera devic…
www.altera.com/support/kdb/solutions/rd01292014_586.html - 2014-01-31

2014-01-29 0 0 Why is there an increase in measured transceiver VCCL_GXB and VCCR_GXB current for a design compiled in Quartus II software versions 13.0, 13.0sp1. 13.1, and 13.1sp1 for Cyclone V, Arria V, and Stratix V transceiver devices?

Due to a bug in Quartus® II software versions 13.0, 13.0sp1. 13.1, and 13.1sp1 you may see an increase in measured transceiver VCCL_GXB and VCCR_GXB current for Cyclone® V, Arria® …
www.altera.com/support/kdb/solutions/rd01172014_109.html - 2014-01-29

2014-01-29 0 0 How do I confirm if a hardware failure on my design using an Arria V or Cyclone V Altera Development Kit is caused by any known device issue?

When operating designs with an Arria® V or Cyclone® V Altera Development Kit, you may observe failures which may be related to known device issues: Example: Phase Alignment …
www.altera.com/support/kdb/solutions/rd08292013_462.html - 2014-01-29

2014-01-29 0 0 How do I set the Marvel 88E1111 Ethernet PHY on the Stratix IV E FPGA Development Kit to GMII mode?

The hardware default setting of Stratix® IV E FPGA Development Kit is incorrectly set to Serial Gigabit Media Independent Interface (SGMII) mode. The Marvel 88E1111 Ethernet P…
www.altera.com/support/kdb/solutions/rd07082013_58.html - 2014-01-29

2014-01-29 130100 13.1 0 Possible Error When Simulating EMIF Designs in VHDL Using ModelSIM AE

This problem affects DDR2, DDR3, DDR4, LPDDR2, QDR II, RLDRAM II and RLDRAM 3 products. If you are running the Quartus II software version 13.1 Arria 10 Edition or 13.1 Arria 10 E…
www.altera.com/support/kdb/solutions/fb170129.html - 2014-01-29

2014-01-28 0 0 Why does my Configuration via Protocol (CvP) design hang the PCIe bus after a CvP core fabric load?

The PCIe® bus can hang when using the CvP Update with Revision Flow if any partitions that are used for CvP become empty. The choices in the Quartus® II software when creating…
www.altera.com/support/kdb/solutions/rd08282013_832.html - 2014-01-28

2014-01-28 130100 13.1 0 Why does the Arria V VHDL PCI Express example design fail to simulate in the Synopsys VCS simultion tool?

Due to a problem in the Quartus® II Software version 13.1, errors may be seen when simulating the VHDL PCI Express Qsys example design using the autogenerated simulation scripts fo…
www.altera.com/support/kdb/solutions/rd01062014_191.html - 2014-01-28

2014-01-31 0 0 Do the LED_AN or LED_LINK signals of Triple Speed Ethernet IP Core reflect the copper link status when the IP Core is in SGMII MAC mode?

No, LED_AN / LED_LINK signals or AUTO_NEGOTIATION_COMPLETE / LINK_STATUS registers do not reflect the copper link status but SGMII link status.
www.altera.com/support/kdb/solutions/rd01262014_695.html - 2014-01-28

2014-01-28 130001 13.0 SP1 130100 13.1 Why do I get a fatal error when installing the Quartus II software version 13.0?

Due to a problem in the Quartus® II installer, you may see this error during installation.  
www.altera.com/support/kdb/solutions/rd08012013_389.html - 2014-01-28

2014-01-28 0 0 Why does my altsyncram based memory fail to initialize correctly when using the $readmemh function during simulation in the ModelSim simulator?

The readmemh function may fail to correctly initialize your altsyncram based memories during simulation if your top level testbench includes the initialization of any other si…
www.altera.com/support/kdb/solutions/rd01272014_86.html - 2014-01-28

2014-04-10 130100 13.1 0 Why am I still getting a Critical Warning about Simultaneous Switching Noise (SSN) and crosstalk even though I am following the SSN and crosstalk reduction guidelines?

Due to a problem in the Quartus® II software version 13.1 you may see the critical warning shown below, even though you have followed the Knowledge Base solution ID: rd1010201…
www.altera.com/support/kdb/solutions/rd01142014_182.html - 2014-01-27

2014-01-27 130100 13.1 0 Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_module_av.cpp, Line: 6805

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error if your design targets an Arria® V ES or Cyclone® V ES device and have Config…
www.altera.com/support/kdb/solutions/rd01272014_852.html - 2014-01-27

2014-01-27 120001 12.0 SP1 120100 12.1 Why are there two different setup relationships for timing paths to the altera_reserved_tdo port in the TimeQuest Timing Analyzer?

Due to a problem in the Quartus® II software version 12.0 SP1 and later, you may see two different relationships for timing paths to the altera_reserved_tdo port. This problem occu…
www.altera.com/support/kdb/solutions/rd12132013_236.html - 2014-01-27

2014-01-27 130100 13.1 0 Internal Error: Sub-system: NVD, File: /quartus/nlv/nvd/nvd_vdiimpl.cpp, Line: 2827

Due to a problem in the Quartus® II software version 13.1, you may see this error when launching the RTL viewer.
www.altera.com/support/kdb/solutions/rd01072014_681.html - 2014-01-27

2014-01-27 0 0 When does the Parallel Flash Loader (PFL) IP assert the flash_nreset signal?

The flash_nreset signal will be asserted in any of the following cases:(1) The device with the PFL design is powered up or configured.(2) The pfl_nreset in…
www.altera.com/support/kdb/solutions/rd01082014_747.html - 2014-01-27

2014-01-27 120100 12.1 0 Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_lut.cpp, Line: 464

Due to a problem in the Quartus® II software version 12.1 and later, you may see this internal error if Rapid Recompile is enabled while using the Incremental Compilation flow.
www.altera.com/support/kdb/solutions/rd12122013_270.html - 2014-01-27

2014-01-22 130001 13.0 SP1 0 No Cyclone V Device Support for 10-Gbps Ethernet MAC Version 13.1 SP1

10GbE MAC version 13.0 Service Pack 1 fails to meet timing when used with Cyclone V devices. This issue will be fixed in a future version of the 10GbE MAC MegaCore function.
www.altera.com/support/kdb/solutions/fb129479.html - 2014-01-24

2014-01-22 110100 11.1 0 PCI Testbench Uses Clear-Text VHDL and Verilog HDL Files

The PCI Compiler user guide wrongly states that the PCI testbench uses open source VHDL and Verilog HDL files. The PCI testbench uses clear-text files.
www.altera.com/support/kdb/solutions/fb116621.html - 2014-01-24

2014-01-22 130000 13.0 130001 13.0 SP1 Broadcast Deinterlacer Hardware Issues

The behaviour of the Broadcast Deinterlacer for cadenced input sequences and some progressive input sequences is 'undefined' when tested in hardware. This issue is fixed in versi…
www.altera.com/support/kdb/solutions/fb117815.html - 2014-01-24

2014-01-21 130000 13.0 130100 13.1 During simulation of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, l8_rx_fcs_error goes to 'X' when l8_rx_fcs_valid is '1'

Due to a problem in the 40- and 100-Gbps Ethernet MAC and PHY MegaCore® Function, l8_rx_fcs_error may go to “X” when l8_rx_fcs_valid goes to '1'.
www.altera.com/support/kdb/solutions/rd01082014_743.html - 2014-01-21

2014-01-21 130100 13.1 0 ncelab: *F,CUMSTS: Timescale directive missing on one or more modules

The Hard IP for PCI Express® auto-generated ncsim_setup.sh file is missing the timescale option.This problem can result in the Cadence® NC-Sim® simulator generating the follow…
www.altera.com/support/kdb/solutions/rd01052014_603.html - 2014-01-21

2014-01-21 0 0 Is there a Linux based PCIe demonstration application?

Application Note 456 uses a Windows-based PCIe demonstration application.
www.altera.com/support/kdb/solutions/rd01072014_495.html - 2014-01-21

2014-01-21 120100 12.1 120101 12.1 SP1 Why does the Hard IP for PCI Express downtrain from Gen3 x8 to Gen3 x1 in simulation?

Due to a problem in the Quartus II software version 12.1 and earlier, the Stratix V Hard IP for PCI Express testbench downtrains from Gen3 x8 to Gen3 x1.This problem only affe…
www.altera.com/support/kdb/solutions/rd04272013_81.html - 2014-01-21

2014-03-12 130100 13.1 0 Why does the Stratix V Hard IP for PCI Express fail to complete DMA transactions when using the Descriptor Control interface?

Due to a problem of Altera® Descriptor Controller IP, simultaneous DMA read and write operations with the Stratix® V Hard IP for PCI Express® for Avalon Memory-Mapped Int…
www.altera.com/support/kdb/solutions/rd01152014_734.html - 2014-01-21

2014-01-20 0 0 How do I fully remove Common Clock Path Pessimism for my edge aligned Source-Synchronous Output Interface?

Due to a problem in the Quartus® II software version 13.1 and earlier, the TimeQuest™ Timing Analyzer removes an insufficient amount of Common Clock Path Pessmism (CCPP) for edge a…
www.altera.com/support/kdb/solutions/rd01172014_985.html - 2014-01-20

2014-01-20 0 0 Internal Error: Sub-system: PUTIL, File: /quartus/power/putil/putil_cyclonev_hssi_info.cpp, Line: 610

Due to a problem in the Quartus® II software version 13.1, you may see this Internal Error while running the PowerPlay Power Analyzer.
www.altera.com/support/kdb/solutions/rd12312013_236.html - 2014-01-20

2014-01-20 120100 12.1 130100 13.1 Why does the Quartus II software give a fatal error after adding post-fit nodes in the SignalTap II Logic Analyzer?

Due to a problem in the Quartus® II software version 12.1 and later, you may see a fatal error after adding post-fit nodes to the SignalTap™ II Logic Analyser in your Str…
www.altera.com/support/kdb/solutions/rd11042013_965.html - 2014-01-20

2014-02-19 130000 13.0 130001 13.0 SP1 bsp-generate-files Hangs when Generating Preloader on Windows

When you attempt to generate preloader files by running bsp-generate-files on a Windows command line, the tool might fail to generate the preloader files, and hang without exiting…
www.altera.com/support/kdb/solutions/fb115815.html - 2014-01-20

2014-01-20 0 0 Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/arriav_arch/arriav_ram_netlist_routines.c, Line: 5520

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error when compiling a design that contains invalid physical width for WY…
www.altera.com/support/kdb/solutions/rd01152014_308.html - 2014-01-20

2014-05-02 130100 13.1 0 Is there SoC Hardware Library (HWLIB) support for QSPI, I2C, or ECC in SoC EDS 13.1?

Yes, SoC Hardware Library (HWLIB) APIs for QSPI, I2C, and ECC are available in SoC EDS version 13.1 via an update patch.
www.altera.com/support/kdb/solutions/rd01072014_376.html - 2014-01-20

2014-01-20 100000 10.0 0 How can I check the results of the RAM bit Reservation settings in Cyclone III designs?

To check the results of the RAM bit reservation settings in Cyclone® III designs, follow these steps: 1. Locate the RAM in the Resource Property Editor 2. Check the Connecti…
www.altera.com/support/kdb/solutions/rd11122013_785.html - 2014-01-20

2014-01-20 130100 13.1 0 Why do I see different timing in the Quartus II timing report and the TimeQuest timing analyzer?

Due to a problem in the Quartus® II software version 13.1, you may see the timing reported in the Quartus II software timing report is different from the timing…
www.altera.com/support/kdb/solutions/rd12022013_526.html - 2014-01-20

2014-01-20 130001 13.0 SP1 0 Why is the latency of my DSP block incorrect?

Due to a problem in the Quartus® II software version 13.0 SP1, you may see this problem if you synthesize your design using a 3rd party synthesis tool and use the DSP input registe…
www.altera.com/support/kdb/solutions/rd11012013_370.html - 2014-01-20

2014-01-15 130000 13.0 130100 13.1 Possible Read/Write Errors for DDR2 and DDR3 Hard Memory Controllers on Arria V and Cyclone V Devices at Low Vcc and Extreme Temperatures

This problem affects DDR2 and DDR3 products. The hard memory controller on Arria V GX, Arria V GT, Arria V SoC, Cyclone V GX, Cyclone V GT, and Cyclone V SoC devices might exhibit…
www.altera.com/support/kdb/solutions/fb153997.html - 2014-01-15

2014-08-26 130200 13.1
Arria 10
Edition
0 ALTFP_MATRIX and ALTFP_MATRIX_INV Megafunctions Do Not Work

In the Quartus II software v13.1 Arria 10 Edition, the ALTFP_MATRIX and ALTFP_MATRIX_INV Megafunctions do not work.
www.altera.com/support/kdb/solutions/fb154187.html - 2014-01-15

2014-01-14 0 0 Why does the DQS Delay reported in the TimeQuest Timing Analyzer for my altdq_dqs2 based design not match my requested phase shift?

Due to a problem in the Quartus® II software versions 13.1 and earlier, you may see an incorrect DQS phase shift reported in the TimeQuest™ Timing Analyzer when the clock used…
www.altera.com/support/kdb/solutions/rd12202013_243.html - 2014-01-14

2014-06-29 110100 11.1 0 How should I connect the MIF address bus between the reconfiguration controller and MIF ROM when word addressing is used in Stratix V GX devices?

MIF addressing is dependent upon the mode selected by bit 1 of address offset 0x1 detailed in the "Streamer Module Internal MIF Register Offsets" table of the PHY IP User…
www.altera.com/support/kdb/solutions/rd05212012_921.html - 2014-01-14

2014-01-13 0 0 Is there a guideline and checklist for debugging calibration failure

Yes. You can find the guideline and checklist located in the altera wiki page to help you to troubleshoot the calibration failure prior seeking assistance from factory application…
www.altera.com/support/kdb/solutions/rd11142011_834.html - 2014-01-13

2014-01-13 0 0 How do I improve timing when I process an Engineering Change Order (ECO)?

To improve timing when processing an ECO, ensure that you turn on the Optimize Timing for ECOs option (Settings > Fitter Settings > More Settings). You will get th…
www.altera.com/support/kdb/solutions/rd12042013_902.html - 2014-01-13

2014-01-13 0 0 Why does my Arria V design fail to route even though the device is not fully utilized?

Due to a problem in the Quartus® II software version 13.1 and earlier,  you may see that your Arria® V design fails to route when the device is not fully utilized. This p…
www.altera.com/support/kdb/solutions/rd12182013_569.html - 2014-01-13

2014-01-13 0 0 Internal Error: Sub-system: SGN, File: /quartus/synth/sgn/sgn_hier_connector.cpp, Line: 6144

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this internal error if your SystemVerilog HDL design uses an unpacked array.
www.altera.com/support/kdb/solutions/rd01082014_490.html - 2014-01-13

2014-01-13 130000 13.0 0 How do I select which modules I want to install from the command line?

Run the QuartusSetup-<version> file, for example QuartusSetup-13.0.0.152.exe or QuartusSetup-13.0.1.232.run with either the --enable-components switch or with the --disable-c…
www.altera.com/support/kdb/solutions/rd11012013_249.html - 2014-01-13

2014-01-13 130001 13.0 SP1 0 What is the maximum operating frequency for an external memory interface using the custom PHY?

The supported maximum global clock network frequency specification is 717 MHz for the fastest speed grade Stratix® V devices. Therefore, the maximum achievable frequence for&n…
www.altera.com/support/kdb/solutions/rd09302013_592.html - 2014-01-13

2014-01-13 0 0 Error (10430): VHDL Primary Unit Declaration error at <location>: primary unit "<name>" already exists in library "<name>"

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a design after you have generated your Qsys system. This error can occu…
www.altera.com/support/kdb/solutions/rd01072014_599.html - 2014-01-13

2014-01-13 120100 12.1 0 Is there an issue after hard memory controller design without specific INI file being programmed on Arria V ES device ?

Design using Arria V ES with hard memory controller compiles fine in quartus and you can program the board successfully. However the design will have problem to work prop…
www.altera.com/support/kdb/solutions/rd11112013_746.html - 2014-01-13

2014-12-16 0 0 What is the HUB IP Configuration Register definition for the Virtual JTAG Megafunction?

The HUB IP Configuration Register definition for bits 7:0 is incorrect in table 9 of the Virtual JTAG Megafunction (sld_virtual_jtag) user guide (PDF).
www.altera.com/support/kdb/solutions/rd12312013_401.html - 2014-01-13

2014-01-13 0 0 Why does my Cyclone IV design have minimum pulse width violations related to the ALTINT_OSC megafunction?

Due to a problem in the Quartus® II software versions 13.1 and earlier, the ALTINT_OSC megafunction incorrectly allows the clock to be set at 100MHz in the MegaWizard™ Pl…
www.altera.com/support/kdb/solutions/rd12182013_337.html - 2014-01-13

2014-11-26 130100 13.1 0 How do I regenerate the Stratix V IP for PCIe?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see the following error when you regenerate the IP for PCIe if you have opened the IP wizar…
www.altera.com/support/kdb/solutions/rd11252013_629.html - 2014-01-13

2014-01-13 130100 13.1 0 Why does System Console fail to launch?

Due to a problem in the Quartus® II software version 13.1, system console may fail to launch. You may see one of the following error messages: Cannot load library: C:/alter…
www.altera.com/support/kdb/solutions/rd01072014_949.html - 2014-01-13

2014-01-13 0 0 Why does the TimeQuest Timing Analyzer only analyze the path from clock to output for the ALTDDIO_OUT megafunction?

The ALTDDIO_OUT megafunction uses a multiplexer where the select pin is driven with a clock signal, and the inputs are two registers with a 1 and 0 connected to the data pins. This…
www.altera.com/support/kdb/solutions/rd12102013_365.html - 2014-01-13

2014-01-13 130100 13.1 0 Why does my RTL inferred RAM use more registers in the Quartus II software version 13.1 than in previous versions?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see a reduced number of registers when inferring a RAM from raw logic with non-zero power-up valu…
www.altera.com/support/kdb/solutions/rd01032014_990.html - 2014-01-13

2014-01-30 0 0 How can I generate the Altera_PLL IP using a script or the command line interface?

In order to generate the Altera_PLL IP from the command line interface, the ip-generate utility can be used.  
www.altera.com/support/kdb/solutions/rd12182013_862.html - 2014-01-10

2014-12-16 0 0 How do I ensure low skew between the two pins that make up an emulated LVDS output on MAX V devices?

MAX® V devices support emulated LVDS outputs using the LVDS_E_3R I/O standard.  If the LVDS_E_3R I/O standard is applied to an output, the Quartus® II software will infer…
www.altera.com/support/kdb/solutions/rd12312013_237.html - 2014-01-10

2014-12-16 0 0 What is the part marking format for MAX V devices in the M100 package?

Due to the small size of the M100 package used by MAX® V devices, the top-side marking format is different to the standard BGA marking format.The following text is shown in the cen…
www.altera.com/support/kdb/solutions/rd12312013_718.html - 2014-01-10

2014-12-16 0 0 Why is the read data misaligned when using the ALTASMI_PARALLEL megafunction?

The dataout[] port from the ALTASMI_PARALLEL megafunction will be misaligned when reading from EPCQ devices if the number of dummy cycles set in the EPCQ non-volatile configuration…
www.altera.com/support/kdb/solutions/rd12312013_813.html - 2014-01-10

2014-01-10 130001 13.0 SP1 0 Error(177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL

You may get this error message if you assign your input clock signal to a dedicated clock pin location and make a global clock (GCLK) assignment to th…
www.altera.com/support/kdb/solutions/rd12162013_361.html - 2014-01-10

2014-01-09 0 0 How can I observe the PIPE interface signals of Stratix IV, Cyclone V and Arria V GX PCIe HIP using Signaltap II?

If you want to use Signaltap™ II to observe the PIPE interface signals of the Stratix® IV, Cyclone® V and Arria® V GX Hard IP for PCI Express®, please set test_in[11:8] of the PCIe…
www.altera.com/support/kdb/solutions/rd12122010_690.html - 2014-01-09

2014-01-09 130100 13.1 0 Can I create false path constraints for paths contained in the file altpcie_reconfig_driver.sv?

Yes, the three paths that you can false path in the Quartus II software version 13.1 are: adce_off_r adce_on_rr resetpld_sync_r The syntax below can be added into a…
www.altera.com/support/kdb/solutions/rd12162013_581.html - 2014-01-09

2014-02-21 0 0 Why does my Cadence NCSim Cyclone V PCIe simulation fail to complete, getting stuck at L0?

Due to an issue when simulating the Cyclone® V Hard IP for PCI Express® using Cadence® NCSim®  the simulation models must be updated.
www.altera.com/support/kdb/solutions/rd01072014_38.html - 2014-01-08

2014-01-08 130100 13.1 0 Why does my 40GBASE-KR4 MAC+ PHY example design fail to simulate in VCS?

When executing the run_vcs.sh simulation script generated by software version 13.1 of the 40GBASE-KR4 IP example design, the simulation will fail to compile, with th…
www.altera.com/support/kdb/solutions/rd12122013_551.html - 2014-01-08

2014-02-10 0 0 Why does my Cadence NCSIM Arria V PCIe simulation fail complete getting stuck in L0 and timeout?

Due to an issue when simulating the Arria® V Hard IP for PCI Express® using Cadence® NCSim®  the simulation models must be updated.
www.altera.com/support/kdb/solutions/rd12272013_814.html - 2014-01-08

2014-01-08 120000 12.0 0 Why does my Configuration via Protocol (CvP) design fail link training and not load the core image when I use a SOF from a Quartus II software version 13.0 or lower in CvP Initialization mode?

There is a known issue with the Convert Programming files conversion of the SRAM Object File (.sof) from Quartus® II software version 12.0 through 12.1sp1. The "Disable EPCS ID che…
www.altera.com/support/kdb/solutions/rd12132013_345.html - 2014-01-08

2014-01-08 130100 13.1 0 Arria II GX CPRI IP Core Verilog HDL Variations at 4.915 Gbps Experience Data Transfer Failure on Antenna/Carrier Interface 17 in Simulation

If you generate a Verilog HDL model for a CPRI IP core variation with a data rate of 4.915 Gbps that targets an Arria II device and transfers data through 18 or more enabled anten…
www.altera.com/support/kdb/solutions/fb153722.html - 2014-01-08

2014-01-08 130100 13.1 0 Why do I get the following error message after updating IP Compiler for PCI Express to version 13.1?

The error is related to the used of fixed address translation table. Error (10198): Verilog HDL error at altpciexpav_stif_a2p_vartrans.v(121): part-select direction is opposite fr…
www.altera.com/support/kdb/solutions/rd11192013_370.html - 2014-01-08

2014-01-08 100000 10.0 0 Why does the Quartus II software crash during the EDA Netlist Writer for designs targeting Stratix V devices?

Due to a problem in the Quartus® II software version 13.1 and earlier, the EDA Netlist Writer may crash for designs targeting Arria® V, Cyclone® V and Stratix® V devices. This…
www.altera.com/support/kdb/solutions/rd04122013_471.html - 2014-01-08

2014-07-04 130100 13.1 0 How can I enable timing support for HPS Loaner I/O in the Quartus II version 13.1?

Timing support for Loaner I/O is not available by default in the Quartus® II software version 13.1.  However a patch is available to add this functionality.
www.altera.com/support/kdb/solutions/rd01082014_212.html - 2014-01-08

2014-05-02 130100 13.1 0 Why do I see high memory usage during the FPGA compilation stage of OpenCL kernels?

Due to a problem in the OpenCL SDK version 13.1,  high memory usage may be seen during the FPGA compilation stage of OpenCL kernels.
www.altera.com/support/kdb/solutions/rd01072014_228.html - 2014-01-07

2014-01-07 130000 13.0 0 ** Error: Unresolved defparam somewhere**

This error can occur when simulating Cyclone® V, Arria® V, and Stratix® V transceiver designs if the "altera_mf" library is placed before the "altera_mf_ver" library in your s…
www.altera.com/support/kdb/solutions/rd07172013_482.html - 2014-01-07

2014-01-07 120101 12.1 SP1 0 Why does the Quartus II software not create transceiver MIF files for Cyclone®, Arria® V, and Stratix® V devices with "advanced" or "inital" support?

Cyclone® V, Arria® V,and Stratix® V transceiver dynamic reconfiguration MIF files are only generated by the Quartus® II software for devices with full programming file support.
www.altera.com/support/kdb/solutions/rd07172013_727.html - 2014-01-07

2014-01-06 0 0 Why does PCIe core transmit corrupted TLP when using Descriptor Data interface with MSI?

When using the PCIe® Incremental Compile Module(ICM) for the Descriptor/Data interface and a MSI transaction is sent while a TLP is being transmitted. This TLP will get corrupted o…
www.altera.com/support/kdb/solutions/rd07152011_543.html - 2014-01-06

2014-01-06 0 0 How do I run a Quartus II compilation on Windows and simulate the results on Linux?

If you use a Cadence or Synopsys simulation tool that only works on Linux, but do not want to install the Quartus® II software on your Linux machine, you can download and install…
www.altera.com/support/kdb/solutions/rd10082013_758.html - 2014-01-06

2014-01-06 120100 12.1 0 Internal Error: Sub-system: BAL, File: /quartus/synth/bal/bal_ec_balancer.cpp, Line: 1463

Due to a problem in the Quartus® II software version 12.1 and later, you may see this error during Analysis & Synthesis when compiling designs with high RAM Block usage.…
www.altera.com/support/kdb/solutions/rd11072013_978.html - 2014-01-06

2014-01-06 0 0 Internal Error: Sub-system: FPP, File: /quartus/periph/fpp/fpp_cell.cpp, Line: 97

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this Internal Error in your Arria® V, Cyclone® V or Stratix® V design. This error occur…
www.altera.com/support/kdb/solutions/rd01032014_404.html - 2014-01-06

2014-05-19 120100 12.1 0 Why does the Quartus II programmer fail to program the Encyption Key Programming file?

Due to a problem in Quartus® II software, when you program the Encyption Key Programming (.ekp) file to Stratix® V, Arria® V or Cyclone® V device using Quartus II pr…
www.altera.com/support/kdb/solutions/rd11182013_331.html - 2014-01-06

2014-01-06 120101 12.1 SP1 0 Why does the ALTECC decoder simulation have glitches when the parity bit is incorrect?

In the Quartus II software version 12.1 SP1 and later, on the output of the ALTECC decoder megafunction you may see glitches on the parity bit for all single-bit errors.&…
www.altera.com/support/kdb/solutions/rd04262013_335.html - 2014-01-06

2014-01-06 0 0 Why is the captured register waveform in SignalTap II Logic Analyzer inverted from the expected signal value?

You may see this behavior when you tap post-fit nodes in the SignalTap™ Logic Analyzer if the register has been implemented with NOT gate push back. This is the correct behavi…
www.altera.com/support/kdb/solutions/rd12092013_388.html - 2014-01-06

2014-01-06 120100 12.1 130000 13.0 Why is the resoure usage for mixed-width dual-port memory incorrectly reported?

Due to an problem in the Quartus® II software version 12.1, you may see the reported resource usage reported as twice the correct value. This problem does not …
www.altera.com/support/kdb/solutions/rd12122013_879.html - 2014-01-06

2014-01-06 130000 13.0 130001 13.0 SP1 Why does the SignalTap II Logic Analyzer trigger before the advanced trigger condition has been met?

Due to a problem in the Quartus® II software version 13.0, you may see the SignalTap™ II Logic Analyzer trigger immediately rather than when the advanced trigger condition is met. …
www.altera.com/support/kdb/solutions/rd11082013_189.html - 2014-01-06

2014-08-27 130001 13.0 SP1 0 Why do I see setup time violation on my I/O paths in the Quartus II software version 13.0 SP1?

You may see setup time violations on your I/O paths that use Hard Memory Controller (HMC) pins as I/O pins on Cyclone® V devices in the Quartus® …
www.altera.com/support/kdb/solutions/rd07302013_370.html - 2014-01-03

2013-12-26 110100 11.1 130100 13.1 CPRI MegaCore Function User Guide Missing Description of map_tx_start_mode field in CPRI_MAP_CONFIG register

The CPRI IP core CPRI_MAP_CONFIG register includes a map_tx_start_mode field at bit [5], starting in the CPRI IP core v11.1 release. However, the CPRI MegaCore Function User Guide…
www.altera.com/support/kdb/solutions/fb139293.html - 2013-12-27

2014-09-30 130100 13.1 0 Critical Warning (11887): The following pin <data pin> was placed in a reserved GND location. This may cause decreased performance for HMC. Altera recommends the pin location to be grounded

The following critical warning may appear after the fitter stage an unused data pin is placed on a reserved hard memory controller (HMC) GND pin. Cri…
www.altera.com/support/kdb/solutions/rd12222013_194.html - 2013-12-26

2013-12-26 0 0 Why does the DDR3 hard memory controller with UniPHY return invalid read data after the individual multi-port front end port is reset?

Due to a problem in the Quartus® II software, the DDR3 hard memory controller with UniPHY may return invalid read data after an individual multi-port front end (MPFE) port is reset…
www.altera.com/support/kdb/solutions/rd12192013_688.html - 2013-12-26

2013-12-20 0 0 Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device?

The center PLLs at the bottom only have access to one PHYCLK network in the Stratix® V device.
www.altera.com/support/kdb/solutions/rd12032013_135.html - 2013-12-20