Stratix III Webcasts and Videos | |
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5 Reasons to Use a Soft-Core MIPS Processor in Your Next Custom Design Watch this video to learn five reasons why you should use a soft-core MIPS processor in your next custom design. You'll get insights about the MP32 processor, the first 100 percent MIPS-compatible soft processor available for Altera® FPGAs and HardCopy® ASICs. Cal Ruben, Applications Engineer, Embedded Technology |
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Enhance Your Productivity with Faster Design Compile Times When choosing your FPGA design software, be sure to consider compile time, a key productivity advantage. In this webcast, you'll learn how Altera's Quartus® II design software delivers a 2X to 3X compile time advantage over competitive software. Richard Yang, Product Marketing Engineer |
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Build up to 96-Port SGMII GigE With Stratix III FPGAs See how Stratix III FPGAs support SGMII GigE operation on LVDS I/O pins at 1.25 Gbps. With Stratix III FPGAs, you can build communications systems requiring single or multiple (up to 96) Ethernet links quickly and simply while meeting jitter and tolerance requirements. Zhi Wong, Sr. Technical Manager |
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Compare Stratix III and Virtex-5 Core Power Consumption Altera's proprietary Programmable Power Technology enables the Stratix III logic fabric to consume less core power than Virtex-5. See a side-by-side comparison and see how this is possible with Stratix III FPGAs. Seyi Verma, Sr. Product Marketing Engineer |
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Interfacing 1,067-Mbps DDR3 Memory to Stratix III FPGAs High-speed DDR3 memory design can be challenging because DDR3 introduces deliberately staggered data at higher frequencies. Without leveling built directly into an FPGA I/O structure, connecting to a DDR3 SDRAM DIMM is costly and time-consuming. Watch this demo to see how easy it is to interface 1,067 Mbps DDR3 memories to Stratix III FPGAs. Paul Evans, Stratix III Product Marketing Manager |
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Implementing High-Speed DDR3 Interfaces Learn more about the challenges of implementing DDR3 as well as available solutions. You’ll learn the JEDEC requirements for DDR3; how to address read/write leveling in your system; and how to reduce power consumption on your board and track PVT. Salman Jiva, Sr. Product Marketing Engineer |
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Signal & Power Integrity Design Techniques for SSN This webcast teaches you signal integrity design techniques for mitigating simultaneous switching noise (SSN) and maintaining power integrity. You’ll learn measurement criteria, measured results, data on design prototypes, simulation predictions, and how to improve SSN on your system. Larry D. Smith, Principal Engineer |
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Intel + Altera = Efficient HPC Processing Using the Front-Side Bus, Altera’s FPGAs communicate with Intel processors to accelerate algorithms and applications up to 100x. See how you can take advantage of these new efficiencies to raise the bar on your HPC application’s performance. Misha Burich, Senior Vice President, Research and Development |
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Meet Your FPGA Design Requirements with Maximum Productivity This webcast shows how Stratix III FPGAs and Quartus II software maximize your productivity while enabling the fastest time to market. Learn how the device and software can deliver the performance and power advantages compared to nearest competitor. Paul McHardy, Supervising Member of Technical Staff, Software and Systems Engineering |
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Learn How FPGAs Interface with DDR3 SDRAM View this webcast to understand how DDR3 works and what's required in an FPGA to effectively implement DDR3. Paul Evans, Product Marketing Manager |
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