FPGAs

The table below lists the FPGAs documentation that was updated in the past 60 days.

Title	Release Date
100G Development Kit, Stratix V GX Edition Reference Manual	Jan 31, 2012
100G Development Kit, Stratix V GX Edition User Guide	Feb 9, 2012
Altera Transceiver PHY IP Core User Guide	Dec 23, 2011
ALTGX Transceiver Setup Guide for Stratix IV Devices	Dec 23, 2011
AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core	Jan 18, 2012
Arria II GX, Arria II GZ and Arria V PowerPlay Early Power Estimator	Jan 25, 2012
Clock Networks and PLLs in the Cyclone III Device Family	Dec 28, 2011
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide	Feb 2, 2012
Configuration, Design Security, and Remote System Upgrades in Arria II Devices	Dec 29, 2011
Configuration, Design Security, and Remote System Upgrades in Stratix V Devices	Dec 21, 2011
Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family	Dec 28, 2011
Configuration, Design Security, Remote System Upgrades with Stratix IV Devices	Dec 23, 2011
Cyclone III Device Data Sheet	Dec 28, 2011
Cyclone III Device Family Overview	Dec 28, 2011
Cyclone III LS Device Data Sheet	Dec 28, 2011
Cyclone III, Cyclone IV and Cyclone V PowerPlay Early Power Estimator	Jan 25, 2012
Cyclone IV Device Family Errata Sheet	Feb 6, 2012
DC and Switching Characteristics for Stratix IV Devices	Dec 23, 2011
DC and Switching Characteristics for Stratix V Devices	Dec 21, 2011
Device Datasheet for Arria II Devices	Dec 29, 2011
Dynamic Reconfiguration in Stratix IV Devices	Dec 23, 2011
Dynamic Reconfiguration in Stratix V Devices	Dec 21, 2011
Embedded Multipliers in the Cyclone III Device Family	Dec 28, 2011
External Memory Interfaces in the Cyclone III Device Family	Dec 28, 2011
High Speed Differential I/O Interfaces with DPA in Stratix IV Devices	Dec 23, 2011
High-Speed Differential I/O Interfaces and DPA in Arria II Devices	Dec 29, 2011
Hot-Socketing and Power-On Reset in the Cyclone III Device Family	Dec 28, 2011
I/O Features in Arria II Devices	Dec 29, 2011
I/O Features in the Cyclone III Device Family	Dec 28, 2011
IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family	Dec 28, 2011
JTAG Boundary-Scan Testing in Stratix V Devices	Dec 21, 2011
Logic Elements and Logic Array Blocks in the Cyclone III Device Family	Dec 28, 2011
Memory Blocks in Arria II Devices	Dec 29, 2011
Memory Blocks in the Cyclone III Device Family	Dec 28, 2011
Overview for the Arria II Device Family	Dec 29, 2011
Stratix V Pin-Out File (5SGSD3)	Jan 13, 2012
Stratix V Pin-Out File (5SGSD4)	Jan 13, 2012
Stratix V Pin-Out File (5SGXA3)	Jan 13, 2012
PowerPlay Early Power Estimator User Guide	Jan 20, 2012
Reset Control and Power Down in Stratix IV Devices	Dec 23, 2011
SCFIFO and DCFIFO Megafunctions User Guide	Feb 9, 2012
SEU Mitigation in the Cyclone III Device Family	Dec 28, 2011
Stratix III, Stratix IV, Stratix V, HardCopy III and HardCopy IV PowerPlay Early Power Estimator	Jan 25, 2012
Stratix IV E Errata Sheet	Feb 6, 2012
Stratix IV GT Errata Sheet	Feb 6, 2012
Stratix IV GX Errata Sheet	Feb 6, 2012
Stratix V Device Family Overview	Dec 21, 2011
Stratix V ES Errata Sheet and Guidelines	Jan 20, 2012
Transceiver Architecture in Arria II Devices	Dec 29, 2011
Transceiver Architecture in Stratix IV Devices	Dec 23, 2011
Transceiver Architecture in Stratix V Devices	Dec 21, 2011
Transceiver Clocking in Stratix V Devices	Dec 21, 2011
Transceiver Configurations in Stratix V Devices	Dec 21, 2011
Transceiver Loopback Support in Stratix V Devices	Dec 21, 2011
Transceiver Reset Control in Stratix V Devices	Dec 21, 2011
Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Guide	Feb 7, 2012
Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Guide	Jan 6, 2012
TriMatrix Embedded Memory Blocks in Stratix IV Devices	Dec 23, 2011

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