Arria V Device Handbook (17 MB)
Arria V Device Handbook, Volume 1: Device Overview and Datasheet (ver 1.3, Feb 2012, 2 MB)
Chapter 1. Overview for Arria V Device Family (ver 1.3, Feb 2012, 525 KB) - Chapter 2. Device Datasheet for Arria V Devices (ver 1.3, Feb 2012, 1,005 KB)
Arria V Device Handbook, Volume 2: Device Interfaces and Integration (ver 1.3, Feb 2012, 5 MB)
- Chapter 1. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices (ver 1.1, Nov 2011, 617 KB)
- Chapter 2. Memory Blocks in Arria V Devices (ver 1.1, Nov 2011, 200 KB)
- Chapter 3. Variable Precision DSP Blocks in Arria V Devices (ver 1.1, Nov 2011, 315 KB)
- Chapter 4. Clock Networks and PLLs in Arria V Devices (ver 1.1, Nov 2011, 818 KB)
- Chapter 5. I/O Features in Arria V Devices (ver 1.2, Feb 2012, 540 KB)
- Chapter 6. High-Speed Differential I/O Interfaces and DPA in Arria V Devices (ver 1.1, Nov 2011, 794 KB)
- Chapter 7. External Memory Interfaces in Arria V Devices (ver 1.1, Nov 2011, 765 KB)
- Chapter 8. Configuration, Design Security, and Remote System Upgrades in Arria V Devices (ver 1.1, Nov 2011, 213 KB)
- Chapter 9. SEU Mitigation in Arria V Devices (ver 1.1, Nov 2011, 151 KB)
- Chapter 10. JTAG Boundary-Scan Testing in Arria V Devices (ver 1.2, Feb 2012, 131 KB)
- Chapter 11. Power Management in Arria V Devices (ver 1.3, Feb 2012, 127 KB)
Arria V Device Handbook, Volume 3: Transceivers (ver 1.1, Nov 2011, 5 MB)
- Chapter 1. Transceiver Architecture in Arria V Devices (ver 1.1, Nov 2011, 1 MB)
- Chapter 2. Transceiver Clocking in Arria V Devices (ver 1.1, Nov 2011, 1 MB)
- Chapter 3. Transceiver Reset Control and Power Down in Arria V Devices (ver 1.1, Nov 2011, 370 KB)
- Chapter 4. Transceiver Protocol Configurations in Arria V Devices (ver 1.1, Nov 2011, 1 MB)
- Chapter 5. Transceiver Custom Configurations in Arria V Devices (ver 1.1, Nov 2011, 878 KB)
- Chapter 6. Transceiver Loopback Support in Arria V Devices (ver 1.1, Nov 2011, 350 KB)
- Chapter 7. Dynamic Reconfiguration in Arria V Devices (ver 1.1, Nov 2011, 141 KB)
Arria V Device Handbook, Volume 4: Device Basics (ver 1.2, Dec 2011, 6 MB)
- Chapter 1. Device Interfaces and Integration Basics for Arria V Devices (ver 1.2, Dec 2011, 5 MB)
- Chapter 2. Transceiver Basics for Arria V Devices (ver 1.1, Nov 2011, 1 MB)
Related Documentation
External Memory Interfaces
- Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions (ver 1.0, Nov 2011, 589 KB)
Power and Thermal Management
- AN657: Thermal Management and Mechanical Handling for Altera FCmBGA Devices (ver 1.0, Jan 2012, 1 MB)
- Meeting the Low Power Imperative at 28 nm (ver 2.0, Nov 2011, 974 KB)
- PowerPlay Early Power Estimator User Guide (ver 6.0, Jan 2012, 2 MB)
I/O Interfaces, Protocols and Signal Integrity
- Arria V Hard IP for PCI Express User Guide (ver 1.0, Nov 2011, 4 MB)
- AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core (ver 1.0, Jan 2012, 856 KB)
an653_Reference_Design_File (346 KB)
- Early SSN Estimator User Guide for Altera Programmable Devices (ver 1.0, Nov 2009, 788 KB)
Arria V Early SSN Estimator (528 KB)
Device Configuration and Remote System Upgrades
- Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide (ver 1.1, Feb 2012, 2 MB)
Design Guidelines
- AN 652: Arria V Timing Optimization Guidelines (ver 1.0, Nov 2011, 1 MB)
- Tips and Techniques for 28-nm Design Optimization (ver 1.0, Nov 2011, 704 KB)
PCB Layout and Packaging
- AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array (ver 1.0, Mar 2012, 980 KB)
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )
- AN657: Thermal Management and Mechanical Handling for Altera FCmBGA Devices (ver 1.0, Jan 2012, 1 MB)
End Applications
- A Validated Methodology for Designing Safe Industrial Systems on a Chip (ver 1.0, Sep 2011, 371 KB)
- Optimize Motor Control Designs with an Integrated FPGA Design Flow (ver 1.2, May 2012, 811 KB)
General Device Documentation
- Altera QAM Design Solution for HD Video (ver 1.0, Nov 2011, 339 KB)
- Altera's User-Customizable ARM-Based SoC FPGAs (ver 1.0, Oct 2011, 3 MB)
- Designing Polyphase DPD Solutions with 28-nm FPGAs (ver 1.0, Jan 2012, 800 KB)
- Industrial Motor Drive on a Single FPGA (ver 2.0, Mar 2012, 370 KB)
- Jump-Start Software Development with the SoC FPGA Virtual Target (ver 1.0, Oct 2011, 370 KB)
- Robust Image Format Conversion Solutions (ver 1.0, Nov 2011, 240 KB)
