Configuration Comparison

For a comparison of the various configuration schemes, refer to Table 1.

Notes:

1. Different devices using the same configuration scheme may support a different external controller and/or configuration device. Refer to the configuration chapter of the respective Altera^® device in the Configuration Handbook for more information.
2. Configuration time is presented as a relative comparison and serves only as a general guideline. Configuration time varies for different configuration schemes and depends on the configuration file size, configuration data width, frequency of the driving clock, and flash access time.

Active and Passive Configuration Schemes

In general, Altera configuration schemes are categorized into active configuration schemes or passive configuration schemes. In the active configuration schemes, the device controls the configuration process and gets the configuration data from an external memory device. Active serial (AS) and active parallel (AP) are active configuration schemes. The memory device is a serial configuration (EPCS) device (PDF) for AS configuration and a supported parallel flash memory for AP configuration. In the passive configuration schemes, the configuration device controls the configuration process and supplies the configuration data. The configuration device can be an external intelligent host, such as a PC, an enhanced configuration (EPC) device (PDF), a microprocessor, or a MAX II CPLD. Passive serial (PS), fast passive parallel (FPP), passive parallel asynchronous (PPA), passive parallel synchronous (PPS), and JTAG are passive configuration schemes.

External Memory and/or Configuration Device

All configuration schemes require either an external memory or a configuration device. These external devices are necessary to store configuration data and/or configure the Altera FPGA when using a particular configuration scheme. For example, an external memory device can be a serial configuration (EPCS) device (PDF) or a supported parallel flash memory device. A configuration controller can be an enhanced configuration (EPC) device (PDF), a microprocessor, or a MAX II or MAX3000A/7000 CPLD. Note that different configuration schemes are supported by different external memories and/or configuration devices. The MAX II CPLD supports Parallel Flash Loader IP to program common flash interface (CFI) flash memory devices through the JTAG interface and provides the logic to control configuration (PS and FPP) from the flash memory device to the Altera FPGA. 

• Parallel Flash Loader for Max II CPLDs
• AN 386: Using the MAX II Parallel Flash Loader with the Quartus II Software (PDF)
• MAX Series Configuration Controller Using Flash Memory white paper (PDF)

Width of DATA Bus

The width of the DATA bus determines the number of bits transmitted per DCLK cycle for the configuration scheme. In general, the configuration schemes can also be grouped in either serial configuration schemes or parallel configuration schemes. Serial configuration schemes transmit 1 bit per DCLK cycle. PS, AS, and JTAG are serial configuration schemes. On the other hand, parallel configuration schemes transmit more than 1 bit per DCLK cycle. The FPP, PPA, and PPS configuration schemes transmit 8 bits per DCLK cycle. The AP configuration scheme transmits 16 bits per DCLK cycle. Generally, the higher number of DATA bits transmitted per DCLK cycle contributes to a shorter configuration time.

Relative Configuration Time

The configuration cycle consists of three stages: reset, configuration, and initialization. The relative configuration times here refer only to the configuration stage. The time it takes for the device to enter user mode is actually longer.

Configuration time varies for different configuration schemes and depends on the configuration file size, configuration data width, frequency of the driving clock, and flash access time. You can estimate the relative configuration time between various configuration schemes of the same device family and density.

AS configuration time is dominated by the time it takes to transfer data from the EPCS to the FPGA device. The AS interface is clocked by the FPGA DCLK output generated from an internal oscillator. The DCLK minimum frequency when using the 40-MHz oscillator is 20 MHz (50 ns). For example, the maximum AS configuration time estimate for an EP3C10 device is (2.5 MBits of uncompressed data) = RBF Size x (maximum DCLK period / 1 bit per DCLK cycle) = 2.5 MBits x (50 ns / 1 bit) = 125 ms.

AP configuration time is dominated by the time it takes to transfer data from the supported parallel flash memory to the device. This AP interface is clocked by the device's DCLK output generated from an internal oscillator. The DCLK minimum frequency when using the 40-MHz oscillator is 20 MHz (50 ns). For example, the maximum AP configuration time estimate for an EP3C10 device is (2.5 MBits of uncompressed data) = RBF Size x (maximum DCLK period / 16 bits per DCLK cycle) = 2.5 MBits x (50 ns / 16 bits) = 7.8125 ms.

In general, AP and FPP configuration schemes have the shortest configuration times, followed by PPS and PPA. Similar to FPP, the configuration frequency for PPS and PPA is controlled by the external device. The AS, PS, and JTAG configuration schemes have a relatively slower configuration time. However, the relative configuration time is just an estimate. The actual configuration time depends heavily on the configuration data width, the configuration frequency at which the device is clocked, the configuration file size, and the flash access time. Enabling compression reduces the amount of configuration data that is transmitted to the Altera device, which also reduces configuration time. On average, compression reduces configuration time by 50 percent.

Support for CLKUSR Feature

In some devices, the CLKUSR pin is an optional pin that inputs a user-supplied clock to synchronize the initialization of one or more devices after configuration. This feature allows one or more devices to enter user mode at the same time. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in Quartus^® II software.

Refer to the configuration chapter of the respective Altera device in the Configuration Handbook for more information.

Scalability

The Altera serial configuration (EPCS) devices (PDF) support a single-device configuration solution for Stratix^® series (except for Stratix and Stratix GX) and Cyclone^® series FPGAs. The enhanced configuration (EPC) devices (PDF) provide configuration support for Stratix series, Cyclone series, APEX^TM II, APEX 20K, Mercury^TM, ACEX^® 1K, and FLEX 10K^® devices.

To choose the appropriate configuration device, you must determine the total configuration space required for your target FPGA or chain of FPGAs. If you are configuring a chain of FPGAs, you must add the configuration file size for each FPGA to determine the total configuration space needed.

Refer to the Altera Configuration Devices (PDF) to determine which configuration device fulfills your configuration space requirements.