Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Design Examples   |   mySupport   |   Reference Designs  

 FPGAs
      Stratix IV (E and GX)
      Stratix III
      Stratix II/Stratix II GX
      Stratix/Stratix GX
      Arria GX
      Cyclone III
      Cyclone II
      Cyclone
  
 CPLDs
      MAX II
      MAX 3000A
      MAX 7000
  
 ASICs
      HardCopy III
      HardCopy II
      HardCopy Stratix
      HardCopy APEX 20K
  
 Downloads
      Device Pin-Outs
      Gerber Files
      IBIS Models
   BSDL/BST
      PCB Symbols
  
 Configuration/Programming
   Configuration
       Schemes
          Guidelines
          Comparison
          Features
          Configuration Devices
          Solutions
          Stratix IV
          Stratix III
          Stratix II/Stratix II GX
          Stratix/Stratix GX
          Cyclone III
          Cyclone II
          Cyclone
          APEX II
          APEX 20K/E/C
          Mercury
          ACEX 1K
          FLEX 10K/E/A
   Programming
   Programming Tools
  
 Power
   Power Management
      Early Power Estimators
      Certified Power Solutions
  
 I/O
      Features
      Specifications
      Hot Socketing
  
 PLL & Clock Management
      Overview
      PLL Basics
      Using PLLs in Software
      Jitter Information
      Clock Networks
      Glossary
  
 Packaging & Board Design
      Specification
      Thermal Resistance
      Sockets and Layout
      Manufacturing
  
 Quality & Reliability
      MSL Calculator
      Certifications
   Environmental
      PCNs & Advisories
   Reports
      Single Event Upset
  
 Failure Analysis
      Overview
      Capabilities
  

Cyclone II Configuration

Configuration Scheme Overview

CycloneTM II devices support the following configuration schemes:

How to Configure Cyclone II Devices

  • For Prototyping or Debugging
    • Using Altera Programming Cables
      • The Quartus® II programmer supports configuring Cyclone II devices directly using PS or JTAG interfaces via Altera® programming cables.
  • In the Field

Frequently Asked Questions

  1. Which of the Altera devices support CONFIG_IO instruction?
  2. What solutions does Altera offer for soft-error/SEU mitigation?
  3. What is a serial configuration (EPCS) device?
  4. Can you cascade serial configuration devices?
  5. What input file should be used to program an EPCS?
  6. How many times can I program and erase the serial configuration devices (EPCS1 and EPCS4)?
  7. What is CONFIG_IO?
  8. Do I need to make any change to the Raw Binary File (.rbf) when I use JRunner to configure Cyclone devices?
  9. How can I create a compressed configuration bitstream to take advantage of my Cyclone FPGA's on-chip decompression feature?
  10. The option "Auto-restart configuration after error" is available for AS mode according to the datasheet. However, if you search for this feature in Quartus II version 4.2 SP1 help, it says it only applies to PS mode. Which is correct?

  Please Give Us Feedback