Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Design Examples   |   mySupport   |   Reference Designs  

 FPGAs
      Stratix IV (E and GX)
      Stratix III
      Stratix II/Stratix II GX
      Stratix/Stratix GX
      Arria GX
      Cyclone III
      Cyclone II
      Cyclone
  
 CPLDs
      MAX II
      MAX 3000A
      MAX 7000
  
 ASICs
      HardCopy III
      HardCopy II
      HardCopy Stratix
      HardCopy APEX 20K
  
 Downloads
      Device Pin-Outs
      Gerber Files
      IBIS Models
   BSDL/BST
      PCB Symbols
  
 Configuration/Programming
   Configuration
       Schemes
          Guidelines
          Comparison
          Features
          Configuration Devices
          Solutions
          Stratix IV
          Stratix III
          Stratix II/Stratix II GX
          Stratix/Stratix GX
          Cyclone III
          Cyclone II
          Cyclone
          APEX II
          APEX 20K/E/C
          Mercury
          ACEX 1K
          FLEX 10K/E/A
   Programming
   Programming Tools
  
 Power
   Power Management
      Early Power Estimators
      Certified Power Solutions
  
 I/O
      Features
      Specifications
      Hot Socketing
  
 PLL & Clock Management
      Overview
      PLL Basics
      Using PLLs in Software
      Jitter Information
      Clock Networks
      Glossary
  
 Packaging & Board Design
      Specification
      Thermal Resistance
      Sockets and Layout
      Manufacturing
  
 Quality & Reliability
      MSL Calculator
      Certifications
   Environmental
      PCNs & Advisories
   Reports
      Single Event Upset
  
 Failure Analysis
      Overview
      Capabilities
  

Cyclone III Device Configuration

Configuration Scheme Overview

Cyclone® III devices support the following configuration schemes:

  • Serial - To Conserve Pins
    • Active Serial (AS)
    • Passive Serial (PS)
      • Uses an external intelligent host such as a PC or a microprocessor to control the configuration process synchronously and supply the configuration data serially to a Cyclone III device.
    • JTAG
      • Configures Cyclone III devices via the IEEE Standard 1149.1 interface.
  • Parallel - For Faster Configuration
    • Active Parallel (AP)
      • Uses the Cyclone III device to control the configuration process and get the configuration data from a supported parallel flash memory.
    • Fast Passive Parallel (FPP)
      • Uses an external intelligent host such as a PC or a microprocessor to control the configuration process synchronously and supply the configuration data in a parallel manner to the Cyclone III device.

How to Configure Cyclone III Devices

  • For Prototyping or Debugging
    • Using Altera Programming Cables
      • The Quartus® II programmer supports configuring Cyclone III devices directly using PS or JTAG interfaces via Altera® programming cables.
  • In the Field
    • Using an EPCS Device (PDF) 
      • The Cyclone III device gets its configuration data from the EPCS device automatically after power up. However, you need to program the EPCS device first.
    • Using a Supported Parallel Flash Memory
      • The Cyclone III device gets its configuration data from the supported parallel flash memory automatically after power up. However, you need to program the flash memory first.
    • MAX Series Configuration Controller Using Flash Memory (PDF) 
      • A MAX® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs.
      • Source code (ZIP)

  Please Give Us Feedback