Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Reference Designs   |   Design Examples   |   mySupport

FPGAs       Stratix IV (E and GX)       Stratix III       Stratix II/Stratix II GX       Stratix/Stratix GX       Arria GX       Cyclone III       Cyclone II       Cyclone     CPLDs       MAX II       MAX 3000A       MAX 7000     ASICs       HardCopy III       HardCopy II       HardCopy Stratix       HardCopy APEX 20K     Downloads       Device Pin-Outs       Gerber Files       IBIS Models    BSDL/BST       PCB Symbols     Configuration/Programming    Configuration        Schemes                AP                AS                FPP                JTAG                PPA                PPS                PS           Guidelines           Comparison           Features           Configuration Devices           Solutions           Stratix IV           Stratix III           Stratix II/Stratix II GX           Stratix/Stratix GX           Cyclone III           Cyclone II           Cyclone           APEX II           APEX 20K/E/C           Mercury           ACEX 1K           FLEX 10K/E/A    Programming    Programming Tools     Power    Power Management       Early Power Estimators       Certified Power Solutions     I/O       Features       Specifications       Hot Socketing     PLL & Clock Management       Overview       PLL Basics       Using PLLs in Software       Jitter Information       Clock Networks       Glossary     Packaging & Board Design       Specification       Thermal Resistance       Sockets and Layout       Manufacturing     Quality & Reliability       MSL Calculator       Certifications    Environmental       PCNs & Advisories    Reports       Single Event Upset     Failure Analysis       Overview       Capabilities

Home > Support > Devices > Configuration > Schemes > JTAG Print This Page Subscribe to Email JTAG Configuration The JTAG configuration scheme uses the IEEE Standard 1149.1 JTAG interface pins and supports the JAM Standard Test and Programming Language (STAPL) standard. Altera® devices are designed such that JTAG instructions have precedence over any device configuration mode. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. JTAG configuration can be performed using an Altera download cable or an intelligent host, such as a microprocessor. Configuration Method in JTAG Mode Using a download cable for in-system programmability (ISP) and prototyping For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook. Embedded Solutions JRunner (PDF) Portable software driver used to configure an FPGA via a JTAG interface Works on a PC using a ByteBlaster™ II or ByteBlasterMV™ download cable Source code (ZIP) available for porting to an embedded or other platform Jam STAPL player (PDF) Offers in-system programming (ISP) via JTAG interface Works on a PC or embedded processors using a ByteBlaster II or ByteBlasterMV download cable Related Literature IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix IV Devices (PDF) IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices (PDF) IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II and Stratix II GX Devices (PDF) IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices (PDF) IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices (PDF) IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices (PDF) AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices (PDF) Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Knowledge Database | Devices | Design Software | Intellectual Property | Reference Designs | Design Examples | mySupport  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation