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Home > Support > Devices > Configuration > Schemes > PS Print This Page Subscribe to Email Passive Serial Configuration Passive serial (PS) configuration can be performed using an Altera® download cable, an Altera configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle. Configuration Methods in Passive Serial Mode Using a download cable for in-system programmability (ISP) and prototyping Using a configuration device Using a MAX® II device as an external host Using a microprocessor For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook. Embedded Solutions MicroBlaster™ Software Driver (PDF) Portable software driver used to configure an FPGA via a PS interface Works on a PC using a ByteBlasterTM II or ByteBlasterMVTM download cable Source code (ZIP) available for porting to an embedded or other platform MicroBlaster Embedded Version (PDF) Please refer to the Implementing the MicroBlaster Configuration on the ColdFire Development Board white paper (PDF) Source code (ZIP) available for porting to an embedded or other platform Application Note AN 386: Using the Parallel Flash Loader with the Quartus II Software (PDF) Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the FPGA Reference Design MAX Series Configuration Controller Using Flash Memory white paper (PDF) Using a MAX or MAX II device as a configuration controller to configure Altera FPGAs from flash memory Source code (ZIP) in Verilog and VHDL Related Literature Altera Configuration Devices (PDF) Enhanced Configuration Devices Data Sheet (PDF) Rate This Page

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