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Home > Support > Devices > Configuration > Stratix IV Print This Page Subscribe to Email Stratix IV Device Configuration Configuration Scheme Overview Stratix® IV FPGAs support the following configuration schemes: Serial—To Conserve Pins Active Serial (AS) Uses the Stratix IV FPGA to control the configuration process and get the configuration data from a serial configuration (EPCS) device (PDF). Passive Serial (PS) Uses an external intelligent host such as a PC or a microprocessor to control the configuration process synchronously and supply the configuration data serially to a Stratix IV FPGA. JTAG Configures Stratix IV FPGAs via the IEEE Standard 1149.1 interface. Parallel—For Faster Configuration Fast Passive Parallel (FPP) Uses an external intelligent host, such as a PC or a microprocessor to control the configuration process synchronously and supply the configuration data in a parallel manner to the Stratix IV FPGA. How to Configure Stratix IV Devices For Prototyping or Debugging Using Altera® Programming Cables The Quartus® II programmer supports configuring Stratix IV FPGAs directly using PS or JTAG interfaces via Altera® programming cables. In the Field Using Serial Configuration Device (PDF) The Stratix IV FPGA gets its configuration data from the EPCS device automatically after power up. However, you need to program the EPCS device first. MAX Series Configuration Controller Using Flash Memory white paper (PDF) A MAX® or MAX II CPLD is used as a flash memory configuration controller to configure Altera FPGAs. Source code (ZIP) Frequently Asked Questions What is CONFIG_IO? Where can I find more information on the design security feature available in Altera's Stratix II device family? Rate This Page

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