Ionizing radiation can cause unwanted effects in semiconductor devices, such as flipping the state of memory cells. These unwanted changes are known as soft errors and are the most common type of single event upsets (SEUs). While statistically unlikely during the operating lifetime of even the largest FPGAs, circuit components within programmable logic devices (PLDs) such as configuration memory cells, user memory, and registers can be affected.
Two types of radiation have been the primary causes of SEUs in semiconductor devices: alpha particle radiation and atmospheric neutrons, originating from the effects of cosmic rays hitting the earth's atmosphere. Studies conducted over the last 20 years have led to high purity package materials minimizing SEU effects caused by alpha particle radiation. Unavoidable atmospheric neutrons remain the primary cause for SEU effects today.
Experiments testing the effects of cosmic ray radiation on Altera® FPGAs revealed the following:
- SEUs do not induce latch-up in Altera FPGAs
- An SEU causes only single-bit errors within the configuration memory
- Mean time between functional interrupt
Altera has been studying the effects of SEUs on its devices for many process generations and has built up extensive experience in both the reduction of soft-error rates through SEU-optimized physical layout and process technology and in soft-error mitigation techniques. Altera introduced the industry's first automatic cyclical redundancy check (CRC) and removed the extra logic and complexity requirements common to other error checking solutions. Altera's device families are all tested for SEU behavior and performance using facilities such as Los Alamos Weapons Neutron Research (WNR).
Built-in Dedicated Hard Circuitry
Dedicated hard circuitry comes built-in to Stratix® and Cyclone® series devices to continually and automatically check the configuration contents at no extra cost. You can easily set up the CRC through Quartus® II software. In addition, the feature set of Stratix III FPGAs builds on this by allowing "don't care" configuration soft errors to be ignored and by integrating error correction coding (ECC) support for user memory. You can find further information regarding the SEU mitigation features for specific devices by following the links below.
For more information regarding other mitigation techniques and for further details about SEU testing of Altera devices, please contact your local Altera sales representative or distributor.
Related Links
- SEU Mitigation in Cyclone IV Devices (PDF)
- SEU Mitigation in Cyclone III Devices (PDF)
- SEU Mitigation in Arria II GX Devices (PDF)
- SEU Mitigation in Stratix Series FPGAs
- Cyclical Redundancy Check (CRC) in Stratix Series FPGA
- AN357: Error Detection and Recovery Using CRC in Altera FPGA Devices (PDF)
- AN539: Test Methodology of Error Detection and Recovery Using CRC in Altera FPGA Devices (PDF)
