Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Design Examples   |   mySupport   |   Reference Designs  

 CPLDs
      MAX II
      MAX 3000A
      MAX 7000
  
 FPGAs
      Cyclone III
      Cyclone II
      Cyclone
      Stratix III
      Stratix II/Stratix II GX
      Stratix/Stratix GX
      Arria GX
  
 Structured ASICs
      HardCopy II
      HardCopy Stratix
      HardCopy APEX 20K
  
 Downloads
      Device Pin-Outs
      Gerber Files
      IBIS Models
   BSDL/BST
      PCB Symbols
  
 Configuration/Programming
   Configuration
   Programming
   Programming Tools
       Altera Programming Tools
       In-Circuit Testers
       Boundary-Scan Tools
               Vendor Support
          Third Party
          IEEE 1532
       Jam STAPL
  
 Power
   Power Management
      Early Power Estimators
      Certified Power Solutions
  
 I/O
      I/O Specifications
      Hot Socketing
  
 PLL & Clock Management
      Overview
      PLL Basics
      Using PLLs in Software
      Jitter Information
      Clock Networks
      Glossary
  
 Packaging & Board Design
      Specification
      Thermal Resistance
      Sockets and Layout
      Manufacturing
  
 Quality & Reliability
      MSL Calculator
      Certifications
   Environmental
      PCNs & Advisories
   Reports
      Single Event Upset
  
 Failure Analysis
      Overview
      Capabilities
  

Boundary-Scan Tool

Boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. This BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. Boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results. Figure 1 illustrates the concept of boundary-scan testing.

Figure 1. IEEE Std. 1149.1 Boundary-Scan Testing

Figure 1. IEEE Std. 1149.1 Boundary-Scan Testing

Boundary-scan tools feature an in-system programmability (ISP) capability which utilizes the IEEE Standard 1149.1 controller for Altera® devices including MAX® II, MAX 3000A, MAX 7000AE and MAX 7000B devices. These devices also support IEEE 1532 programming which utilizes the IEEE Standard 1149.1 Test Access Port (TAP) interface.

Related Documents

Frequently Asked Questions

Related Links


Learn About Altera's IEEE 1532 Solution

Learn the Secrets of MAX II

  Please Give Us Feedback