AHDL: Cycle-Shared Dual-Port RAM (csdpram)
This example implements a dual-port RAM block with two inputs
that are 4 bits wide and 16 words deep. You can change the width
(LPM_WIDTH) and depth (LPM_WIDTHAD)
parameters as needed for your design. The ports of the LPM function are defined in a
Function Prototype Statement (shown in blue text). An Instance Declaration (shown in red text) implements an instance of
the function.
If you are using this function in a FLEX 10K design, MAX+PLUS II will implement the RAM in
embedded array blocks (EABs).
For more information on using this example in your project, go to:
csram.tdf
FUNCTION csdpram (dataa[3..0], datab[3..0], addressa[3..0],
addressb[3..0], wea, web, clock,clockx2)
WITH (LPM_WIDTH = 4, LPM_WIDTHAD = 4)
RETURNS (qa[3..0], qb[3..0], busy);
SUBDESIGN csram
(
dataa[3..0] : INPUT;
datab[3..0] : INPUT;
addressa[3..0] : INPUT;
addressb[3..0] : INPUT;
qa[3..0] : OUTPUT;
qb[3..0] : OUTPUT;
wea : INPUT;
web : INPUT;
clock : INPUT;
clockx2 : INPUT;
)
VARIABLE
csdpramtest : csdpram;
BEGIN
csdpramtest.clock = clock;
csdpramtest.clockx2 = clockx2;
csdpramtest.dataa[3..0] = dataa[3..0];
csdpramtest.datab[3..0] = datab[3..0];
csdpramtest.addressa[3..0] = addressa[3..0];
csdpramtest.addressb[3..0] = addressb[3..0];
csdpramtest.wea=wea;
csdpramtest.web=web;
qa[3..0]=csdpramtest.qa[3..0];
qb[3..0]=csdpramtest.qb[3..0];
END;
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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