Date December 8, 2008
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Design Description
A design showing 4 x72 DDR3 SDRAM DIMM high-performance controllers fitting in a EP4SGX530 F1932 package. No resources was shared in this design. This design is to show that four DIMMs can fit in one FPGA and to also show how to stamp out four exact controllers with one ALTMEMPHY instantiation. The SDC and report_timing.tcl will be able to constrain and report the timing result for all four controllers without additional work.

This design was never simulated or tested on the board

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Quartus Version 8.0 SP1
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Spec
-> Type of Controller               : DDR3 SDRAM High-Performance Controller
-> Speed                            : 400 MHz
-> Width                            : 4 x72 bit
-> F/H Rate                         : Half-Rate
-> Latency                          : Typical (See the DDR3 SDRAM High-Performance Controller User Guide)
-> Burst Length                     : 4
-> IO Standards                     : 1.5-V SSTL
-> OCT                              : 
   -> Signal                        : DQ/DQS
      -> Type                       : 50-ohm
      -> Calibration                : Power-up
      -> Dynamic                    : Yes
   -> Signal                        : CK/CK#
      -> Type                       : 50-ohm series
      -> Calibration                : No
      -> Dynamic                    : No
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FPGA Device                         : EP4SGX530NF45C3
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Memory Device                        
-> DIMM
   -> Base Device                   : MT9JSF12872AY-1G1BZES
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Design Name                         : mem_int_top
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Design Language                     : BDF + Verilog + encrypted controller
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Files                               : Default files from the DDR3 SDRAM High-Performance Controller
   -> mem_int_top.bdf               : top level design