Viterbi BER Measurement Design Example v1.0.0 README File This readme file contains the following sections: o Package Contents o Tool Requirements o Description of Design Example o Simulation in Simulink o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Viterbi BER Measurement Design Example v1.0.0 Design files include: o Viterbi_BER.mdl - DSP Builder design file implementing the logic to measure the bit error rate (BER) performance of the Viterbi decoder. o Viterbi_BER_HIL.mdl - DSP Builder design file implementing the same functionality as the design above with the exception of replacing the Viterbi Decoder block with a Hardware in the loop (HIL) block implemented in actual hardware to speed up simulation. o init.m - MATLAB script to initialize the noise level in the channel (Eb/No), number of soft bits, traceback length and the puncturing pattern. o Viterbi.vhd - VHDL wrapper file for the Viterbi Decoder IP generated by IPToolbench. o Viterbi_BER.ber - BERTool session to analyze the BER performance based on the HIL design Tool Requirements ================= This design example requires the following software package: o Quartus II 5.1 o DSP Builder v5.1 o Viterbi Compiler v4.2.3 o MATLAB/Simulink R14 SP2 o Signal Processing Blockset v6.1 o Communications Blockset v3.1 o Communications Toolbox v3.1 Please contact your local sales representative if you do not have one of these software tools. To run the Hardware in the Loop version of the design example, you require any of the following Altera development boards: o Stratix DSP Development Board o Stratix II DSP Development Board o Cyclone II DSP Development Board Description of Design Example ============================= The design example describes the measurement of bit error rate (BER) for the Altera Viterbi decoder. The design includes the communication channel with a transmit and receive block. The Viterbi decoder is implemented using a combination of the DSP Builder blocks and the Altera Viterbi Compiler IP MegaCore while the rest of the system is implemented using Simulink blocks. There are two versions of the design: the first uses the Viterbi decoder simulation model generated by the IPToolbench, and the other uses the hardware in the loop (HIL) feature to accelerate the simulation in Simulink. To get more details on the Viterbi Compiler IP MegaCore, refer to the Viterbi Compiler User Guide located at: http://www.altera.com/literature/ug/ug_viterbi-compiler.pdf Simulation in Simulink ====================== To compile and simulate the non-HIL version of the design example, perform the following steps: 1. Open the Viterbi_BER.mdl file. When the deisgn is loaded, it runs the init.m MATLAB script. The script initializes the noise level in the channel (Eb/No), number of soft bits, traceback length and the puncturing pattern. It also sets the limits on the maximum number of bits and maximum number of errors count for the BER calculation. 2. Push into the Viterbi_MegaCore_wrapper subsystem. In the Viterbi_BER/Viterbi_MegaCore_wrapper window, double-click on the viterbi core. This brings up the IP Toolbench for Viterbi Compiler. 3. Review the parameters for the Viterbi Decoder and regenerate the core. Upon completion, exit IP Toolbench. DSP Builder performs an additional step of optimizing the model for use in Simulink. 4. In the Viterbi_BER.mdl top-level window, double-click on the Signal Compiler block. Click on Analyze. 5. On page 2 of the Signal Compiler window, click on "Execute steps 1, 2, and 3" to compile the project. 6. To start simulation, select "Start" (Simulation menu). At the end of simulation, double-click on the scope to view the simulation results. To compile and simulate the HIL version of the design example, perform the following steps: 1. Open the Viterbi_BER_HIL.mdl file. When the deisgn is loaded, it runs the init.m MATLAB script. The script initializes the noise level in the channel (Eb/No), number of soft bits, traceback length and the puncturing pattern. It also sets the limits on the maximum number of bits and maximum number of errors count for the BER calculation. 2. Double-click on the HIL block. On page 1 of the HIL window, select the "Viterbi_BER.qpf" Quartus II project. This is the project compiled in the section above. 3. Select the "Signed" option for the input ports, and burst mode with burst length set to 1024. 4. Enable the "Assert Slcr before starting the simulation" checkbox. Click on Next. 5. On page 2, enter the target device based on the DSP development board you have (e.g. EP2S60F1020C4ES) Click on the Compile button. When the compilation is completed, it generates the configuration file (SOF). 6. In the "Program the FPGA" section, select the appropriate JTAG Cable, and the "Device in chain" text box shouuld be automatically populated with the correct device. Click on the "Configure FPGA" button. 7. Exit the HIL window by clicking on Close. 8. To start simulation, select "Start" (Simulation menu). At the end of simulation, double-click on the scope to view the simulation results. To plot a set of data to generate the BER curve using the bertool (Communications Toolbox), perform the following steps: 1. In the MATLAB workspace, type >> bertool 2. In the Bit Error Rate Analysis Tool window, open the Viterbi_BER.ber file (File menu). Click on the Monte Carlo tab to review the parameters. It is recommended that you select the Viterbi_BER_HIL.mdl version of the design as the simulation model to speed up simulation. 3. Click on Run to start the simulation. You can choose to modify any of the parameters in the init.m file prior to simulation. If you change the n_bits (number of soft bits) parameter, constraint length, or maximum traceback length, you have to rerun IPToolbench for the Viterbi Decoder IP MegaCore and recompile the design using the steps listed above. To get more details on the design flow using DSP Builder, refer to the DSP Builder User Guide located at: http://www.altera.com/literature/ug/ug_dsp_builder.pdf Release History =============== Version 1.0.0 ------------- Initial release Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2005 Altera Corporation. All rights reserved.