Date: January 2010
===============
Design Description: This example design shows an interface with a 64-bit wide 1-Gb Micron MT8HTF12864HDY-800G1 400-MHz DDR2 SDRAM SODIMM.


===============
Quartus Version 9.1
Modelsim Version 6.5
================
Spec
-> Type of Controller               : DDR2 SDRAM High Performance Controller II
-> Speed                            : 267 MHz
-> Width                            : x 64
-> F/H Rate                         : Half-Rate 
-> Latency                          : 6
-> Burst Length                     : 8 (For High Performance Controller II) 
-> IO Standards                     : SSTL-18 Class I   
-> OCT                              : Enabled
     
================
FPGA Device                         : EP2AGX125EF35C5
================
Memory Device                       : 
-> DIMM                             : MT8HTF12864HY-800G1
   -> Base Device                   : MT47H128M8
-> Component                        : 
================
Design Name                         : ddr2_sodimm
================
Design Language                     : Verilog HDL
================

ddr2_sodimm_example_top 										: top level design
	-> ddr2_sodimm 											: DDR2 SDRAM High Performance Controller Megawizard
		->ddr2_sodimm_controller_phy								: Top level design of phy and memory controller
			->ddr2_sodimm_alt_ddrx_controller_wrapper					: a wrapper that configures DDRx controller.   
				->alt_ddrx_controller 							: Top level file that instantatiates all the controller blocks
					->alt_ddrx_addr_cmd 						: address and command decoder
					->alt_ddrx_afi_block  						: AFi block
					->alt_ddrx_bank_tracking
					->alt_ddrx_csr
					->alt_ddrx_ecc
					->alt_ddrx_input_if 						: Altera Input Interface block
						->alt_ddrx_avalon_if					: Altera Avalon Interface block
						->alt_ddrx_cmd_queue					: Altera Command Queue block
						->alt_ddrx_wdata_fifo 					: Altera Write Data FIFO block
					->alt_ddrx_odt_gen 						: ODT signal generator block
						-> alt_ddrx_ddr3_odt_gen 				: DDR2 ODT signal generator block
					->alt_ddrx_state_machine 					: state machine
					->alt_ddrx_timers						
						->alt_ddrx_timers_fsm
			->ddr2_sodimm_phy								: DDR2 ALTMEMPHY MegaWizard Plug In
				->ddr2_sodimm_phy_alt_mem_phy
					->ddr2_sodimm_phy_alt_mem_phy_pll				: PLL Megafunction Wizard
	->ddr2_sodimm_example_driver 
		->ddr2_sodimm_ex_lfsr8									: LFSR pattern for self checking on DDR2



-> ddr2_sodimm_phy_autodetectedpins.tcl		
-> ddr2_sodimm_phy_ddr_pins.tcl
-> ddr2_sodimm_phy_ddr_timing.tcl			: memory timing model
-> ddr2_sodimm_phy_report_timing.tcl    		: Generates a detailed timing report for all timing paths in the ALTMEMPHY instance.
-> ddr2_sodimm_phy_report_timing_core.tcl  		: perform flexible timing analysis
-> ddr2_sodimm_pin_assignments.tcl			: Adds I/O standard settings for all memory interface pins, and adds output enable group assignments to ensure VREF rules are met when the design contains input/bi-directional pins.
-> ARRIAIIGX_DDR2_BTModels.tcl				: Altera-provided tcl for Board Trace Model assignments for this design	
-> ARRIAIIGX_DDR2_PinLocations.tcl			: Altera-provided tcl for pin locations assignments for this design.
-> ARRIAIIGX_DDR2_exdriver_vpin.tcl			: Altera-provided tcl for virtual pins assignments for this design.
-> ddr2_sodimm_phy_ddr_timing.sdc			: Sets timing constraints for the ALTMEMPHY megafunction instance.
-> ddr2_sodimm_example_top.sdc				: constrains the ALTMEMPHY memory interface PHY.
-> altera_avalon_half_rate_bridge_constraints.sdc 	: Constraint multicycle path for "Altera Avalon MM DDR Memory Half Rate Bridge".



================
Features 
================
Simulation
-> testbench/ddr2_sodimm_example_top_tb.v       : Design test bench for simulation
-> testbench/ddr2_sodimm_mem_model.v		: DDR2 verilog model
-> simulation/modelsim/vsim.wlf			: Simulation waveforms result

================
Board                               : Arria II GX Development Kit
================
Instructions                        : Refer to the Using DDR, DDR2, and DDR3 SDRAM in Arria II GX devices chapter in Volume 6, Section I of the External Memory Interface Handbook
================