Date: October 2009
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Design Description: Demo 150MHz DDR2 SDRAM interface in Cyclone III device using SOPC Buider flow.
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Quartus Version 9.1
Modelsim Version 6.5b
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Spec
-> Type of Controller               			: DDR2 High Performance Controller II
-> Speed                            			: 150MHz
-> Width                            			: x8 single DDR2 SDRAM component
-> F/H Rate                         			: Full-rate with Half-Rate Bridge
-> Latency                          			: CAS 3.0
-> Burst Length                     			: 4
-> IO Standards                     			: 18 SSTL IO Standard class I
-> OCT                              			: None
-> Current strength		    			: 
	-> Command and address signals			: Maximum current strength 
	-> DQ, DQS, DM, and memory clock signals	: 12mA
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FPGA Device                         			: EP3C120F780C7
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Memory Device                       			: 
-> DIMM							: None
   -> Base Device                  			: None
-> Component                       			: MT47H32M16CC-3 
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Design Name                         			: DDR2
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Design Language                     			: Verilog HDL
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Files (HDL, TCL, SDC ...)           			: 
-> hb_emi_ddr2_ciii_sopcb.qar				: QuartusII v9.1 Complete Archive
-> DDR2.bdf		 				: Top Level Design
-> altmemddr(Standard CIII v9.1 DDR2 HP Controller)	: Std file list, refer to 9.1 EMI handbook, HP controller section
-> Led_pio.v						: Parallel I/O core design file
-> cpu.v						: NIOS II processor design file
-> dma.v						: DMA controller design file
-> jtag_uart.v						: JTAG Uart core design file


-> cycloneIII_3c120_generic.sdc				: Top level constraint file to drive the input clock frequency
-> altera_avalon_half_rate_bridge_constraints.sdc	: Constraint file for half-rate bridge with added derive_pll_clocks command to derive the pll clock
-> C3_Dev_DDR2_BTModels.tcl 				: Board Trace Models for Cyclone III & MT47H32M16CC-3  Boards
-> C3_Dev_DDR2_Sopc_Pin_Location.tcl			: Pin location assignments for Cyclone III Developement Board DDR2 SDRAM Interface
-> DDR_TEST.c						: Example program file

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Features 
-> Advanced IO Timing, Board Trace Models, SignalTapII	: Launch SignalTapII, program device, view signals
-> NIOS II IDE						: Launch the NIOS II IDE to run the DDR_TEST program
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Simulation
-> sopc_top.v              				: Simulation top level test bench file 
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Board                               			: Cyclone III F780 Development Board
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Instructions 						
-> Simply un-archive the QAR and recompile.
-> Launch SignalTapII and NIOS II IDE, program device, view signals
Refer to the Using High-Performance DDR, DDR2,and DDR3 SDRAM with SOPC Builder chapter in Volume 6, Section I of the External Memory Interface Handbook
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Contact Altera
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Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered.
If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please
contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documention provided with this
function, please contact Altera Applications:

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