Date October 2009
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Design Description: This example design shows an interface with a 16-bit wide 1-Gb Micron MT41J64M16LA-15E DDR3 SDRAM component.
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Quartus Version 9.1
Modelsim Version 6.5
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Spec
-> Type of Controller               : DDR3 SDRAM High Performance Controller II
-> Speed                            : 300 MHz
-> Width                            : x 16
-> F/H Rate                         : Half-Rate 
-> Latency                          : 9
-> Burst Length                     : on the fly
-> IO Standards                     : SSTL-15 Class I   
-> OCT                              : Enabled
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FPGA Device                         : EP2AGX125EF35C4
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Memory Device                       : 
-> Component                        : MT41J64M16LA-15E
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Design Name                         : ddr3
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Design Language                     : Verilog HDL
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ddr3_example_top 							: top level design
	-> ddr3 							: DDR3 SDRAM High Performance Controller Megawizard
		->ddr3_controller_phy					: Top level design of phy and memory controller
			->ddr3_alt_ddrx_controller_wrapper		: a wrapper that configures DDRx controller.   
				->alt_ddrx_controller 			: Top level file that instantatiates all the controller blocks
					->alt_ddrx_addr_cmd 		: address and command decoder
					->alt_ddrx_afi_block  		: AFi block
					->alt_ddrx_bank_tracking
					->alt_ddrx_csr
					->alt_ddrx_ecc
					->alt_ddrx_input_if 		: Altera Input Interface block
						->alt_ddrx_avalon_if	: Altera Avalon Interface block
						->alt_ddrx_cmd_queue	: Altera Command Queue block
						->alt_ddrx_wdata_fifo 	: Altera Write Data FIFO block
					->alt_ddrx_odt_gen 		: ODT signal generator block
						-> alt_ddrx_ddr3_odt_gen: DDR3 ODT signal generator block
					->alt_ddrx_state_machine 	: state machine
					->alt_ddrx_timers						
						->alt_ddrx_timers_fsm
			->ddr3_phy					: DDR3 ALTMEMPHY MegaWizard Plug In
				->ddr3_phy_alt_mem_phy
					->ddr3_phy_alt_mem_phy_pll	: PLL Megafunction Wizard
	->ddr3_example_driver 
		->ddr3_ex_lfsr8						: LFSR pattern for self checking on DDR3
-> ddr3_phy_autodetectedpins.tcl		
-> ddr3_phy_ddr_pins.tcl
-> ddr3_phy_ddr_timing.tcl			: memory timing model
-> ddr3_phy_report_timing.tcl    		: Generates a detailed timing report for all timing paths in the ALTMEMPHY instance.
-> ddr3_phy_report_timing_core.tcl  		: perform flexible timing analysis
-> ddr3_pin_assignments.tcl			: Adds I/O standard settings for all memory interface pins, and adds output enable group assignments to ensure VREF rules are met when the design contains input/bi-directional pins.
-> ARRIAIIGX_DDR3_BTModels.tcl			: Altera-provided tcl for Board Trace Model assignments for this design	
-> ARRIAIIGX_DDR3_PinLocations.tcl		: Altera-provided tcl for pin locations assignments for this design.
-> ARRIAIIGX_DDR3_exdriver_vpin.tcl		: Altera-provided tcl for virtual pins assignments for this design.
-> ddr3_phy_ddr_timing.sdc			: Sets timing constraints for the ALTMEMPHY megafunction instance.
-> ddr3_example_top.sdc				: constrains the ALTMEMPHY memory interface PHY.
-> altera_avalon_half_rate_bridge_constraints.sdc: Constraint multicycle path for "Altera Avalon MM DDR Memory Half Rate Bridge".
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Features 
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Simulation
-> testbench/ddr3_example_top_tb.v      : Design test bench for simulation
-> testbench/ddr3_mem_model.v		: DDR3 verilog model
-> simulation/modelsim/vsim.wlf		: Simulation waveforms result
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Board                               : Arria II GX dev kit
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Instructions                        : Refer to the Using DDR3 SDRAM in Stratix III and Stratix IV devices chapter in Volume 6, Section I of the External Memory Interface Handbook
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Contact Altera
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Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered.
If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please
contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documention provided with this
function, please contact Altera Applications:

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                           http://www.altera.com/support

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Copyright (c) 2009 Altera Corporation. All rights reserved.