Date 18-May-20111
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Demo 533MHz RLDRAMII SDRAM interface in Stratix IV device.
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Quartus Version 11.0
Modelsim Altera Version 6.6d
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Spec
-> Type of Controller               			: RLDRAM II Controller with UniPHY v11.0
-> Speed                            			: 533MHz
-> Width                            			: x36 single RLDRAMII SDRAM component
-> F/H Rate                         			: Half-Rate Controller
-> Latency                          			: RL6
-> Burst Length                     			: 4
-> IO Standards                     			: 18 HSTL IO Standard class I
-> OCT                              			:
   -> DQ, QK, DK, DM, and memory clock signals          : 
      -> Type                       			: 50 ohms series/50 ohm parallel
      -> Calibration                			: Power up
      -> Dynamic                    			: Yes
-> Current strength		    			: 
	-> Command and address signals			: Maximum current strength 
	
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FPGA Device                         			: EP4SE530H35C2
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Memory Device                       			: 
-> DIMM							: None
   -> Base Device                  			: None
-> Component                       			: MT49H16M36HT-18
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Design Name                         			: rldram_example_top
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Design Language                     			: Verilog HDL
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Files (HDL, TCL, SDC ...)           			: 
-> hb_emi_rldramii_siv_uniphy.qar								: QuartusII v11.0 Complete Archive
-> rldram_example.v               								: Top level design. For the subsequence level of the design files please refer to the project hierarchy.
	
-> rldram_example_if0_p0_pin_assignments.tcl					: Adds I/O standard settings for all memory interface pins, and adds output enable group assignments to ensure VREF rules are met when the design contains input/bi-directional pins.
-> rldram_example_if0_p0_report_timing.tcl						: Generates a detailed timing report for all timing paths in the UniPHY instance.
-> rldram_example_if0_p0.sdc									: Sets timing constraints for the UniPHY megafunction instance.  
-> rldram_example_if0_p0_timing.tcl									: Contains timing constraints for your UniPHY variation.
-> rldram_example_if0_p0_parameters.tcl							: Contains parameters that describe geometry of the core and PLL configuration.
-> rldram_example_if0_p0_pin_map.tcl							: Contains the traversal routines that are used by both rldram_example_if0_p0_pin_assignments.tcl and rldram_example_if0_p0.sdc scripts.			
-> rldram_example_if0_p0_report_timing_core.tcl      			: Contains timing analysis procedure for all the paths.


-> S4_Host_RLDRAM_BTModal.tcl 				: Board Trace Models for SIV & MT49H16M36HT-18 Boards
-> S4_Host_RLDRAM_PinLocations.tcl			: Pin Location Assignments for SIV E F1152 Developement Board RLDRAMII SDRAM Interface

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Features (e.g. Advanced IO Planner, DTW ...)
-> Advanced IO Timing, Board Trace Models, SignalTapII	: Launch SignalTapII, program device, view signals

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Simulation
-> Un-archive the hb_emi_rldramii_siv_uniphy_sim.qar, perform Synthesis & Analysis, then perform simulation.

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Board                               			: Stratix IV E F1152 Development Board
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Instructions 
-> Simply Un-archive the QAR and recompile.
-> Launch SignalTapII, program device, and view the signals
-> Refer to Volume 6, Section II of the External Memory Interface Handbook for full design guidelines and flow                       	
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Contact Altera
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Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered.
If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please
contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this
function, please contact Altera Applications:

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