Date: October 2008
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Design Description: This design features 3 DDR3 controllers on top edge (two x16 interfaces & one x32 interface) operating at 400-MHz/800-Mbps. This example design uses the ALTMEMPHY megafunction-based DDR3 SDRAM High Performance Controller MegaCore, and was generated using the example walkthrough described in AN436. In addition, one DLL & 3 static PLL clocks are shared across all controllers as described in AN462. This timing closed design can used as an example showing feasibility for 3 controllers on one side of device with DLL/PLL sharing.
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Quartus Version: Quartus II 8.1
Modelsim Version: N/A
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Spec
-> Type of Controller               : Half-rate DDR3 SDRAM High-Performance Controller (ALTMEMPHY-based)
-> Speed                            : 400-MHz/800-Mbps	
-> Width                            : Two x16 interfaces & one x32 interface on top edge
-> F/H Rate                         : Half rate
-> Latency                          : Default
-> Burst Length                     : Default
-> IO Standards                     : 1.5-V SSTL
-> OCT                              : Enabled
	-> DQ/DQS signals             : Series 50 Ohm with Calibration & Parallel 50 Ohm with Calibration
	-> DM signals                 : Series 50 Ohm with Calibration
	-> CK/CK# signals             : Series 50 Ohm without Calibration
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FPGA Device                         : EP4SGX230KF40C3
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Memory Device                       : Discrete components (Micron MT41J256M8JE-25)
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Design Name                         : ddr3_2inst.qpf
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Design Language                     : VHDL
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Files (HDL, TCL, SDC ...)           : Default DDR2 HP Contoller example design file structure
-> DDR3_ex_top_3inst.vhd	      : top level design
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Simulation                          : N/A
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Board                               : N/A
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Instructions                        : Refer to AN436 & AN462 for design flow used to create this example design.
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