Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Design Examples   |   mySupport   |   Reference Designs  

 Products
      MAX/MAX II
      Stratix/Stratix GX
      Nios II
  
 Functionality
      Arithmetic
      Memory
      Bus & I/O
      Logic
      Interfaces & Peripherals
      DSP
      Communications
      PLL & Clocking
  
 Design Entry
      Quartus II Project
      Tcl
      VHDL
      Verilog HDL
      C Code Examples
      DSP Builder
      TimeQuest
   On-Chip Debugging
  
 Simulation Tools
      Mentor Graphics ModelSim
      Cadence NCsim
      Synopsys VCS
  
 Legacy Examples
      Graphic Editor
      AHDL
  

2D Sharpening FIR Filter Design Example

This design example shows how to perform a two-dimensional finite impulse response (FIR) filtering operation on video stream data in DSP Builder. The model consists of an image stream source block, a 2D sharpening filtering block, and an image stream sink block. The image stream source block reads the input binary file and feeds the data stream to the 2D FIR filtering block. The image stream sink block writes the filtered data stream to an output binary file. The package also includes the utility to convert an avi video file format to and from a binary file format.

Download the files used in this example:

Files in the zip download include:

  • example_fir_2d.mdl - DSP Builder design file 
  • fir_filter_2d.vhd - Wrapper file to generate the Altera® 2D FIR intellectual property (IP) core
  • avi-is-avi.exe - DOS executable to convert an avi file to and from a binary file.

Figure 1 shows the top-level diagram of the 2D FIR design example in DSP Builder.

Figure 1. 2D Sharpening FIR Filter Design Example

Figure 1. 2D Sharpening FIR Filter Design Example
View full size

Table 1 lists the ports and gives a description for each.

Table 1. 2D FIR Port Listing
Port Name Type Description
din_data[7:0] Input Data input bus
din_valid Input Data valid signal that indicates the validity of the input data signals
dout_ready Input Data output ready signal
reset Input Reset signal
din_ready Output Data input ready signal
dout_data[7:0] Output Data output bus
dout_valid Output Data valid signal that indicates the validity of the output data signals

Related Links

  Please Give Us Feedback