The Designing Digital Down Conversion Systems design example, featuring the Altera® CIC and FIR MegaCore® functions, demonstrates a multichannel, multirate digital system using Altera's DSP MegaCore intellectual property (IP).
Sample rate conversion has a wide range of applications in modern digital systems, especially wireless communications systems such as WCDMA and WiMAX systems. Efficient implementation of decimation and interpolation can be accomplished by concatenating cascaded-integrator-comb (CIC) and finite impulse response (FIR) filters.
This example demonstrates a data rate down conversion system that can be commonly seen in time division multiplexing (TDM) WiMAX receivers. The overall system diagram is shown in Figure 1. For more details about Altera wireless digital up/down solutions please refer to AN421: Accelerating WiMAX DDC & DDC System Designs (PDF).
Figure 1. TDM Digital Down Conversion System Block Diagram
Model
The input to the design example is from two independent data sources, such as the inphase (I) and quadrature (Q) components of a digital communications system. The inphase signal is a sine wave with a center frequency of 4.57 MHz. The quadrature signal is a cosine wave also centered at 4.57 MHz. The combined, time multiplexed input data stream is sampled at 182.784 MHz, so the corresponding data rate for the inphase and quadrature signals is 91.392 MHz. Part of the input signal is corrupted by high-frequency additive noise.
The CIC and FIR filters convert inphase and quadrature signals sample rate to 11.484 MHz while maintaining the input signals spectrum information. The decimation filters also reject out-of-band noise. Therefore, the output of this rate conversion system should be noiseless down sampled sinusoidal waves of frequency 4.57 MHz. For well defined rate change systems, the narrow band information signal should maintain its spectrum from input to output, as demonstrated in this design example.
Features
- Decimation or interpolation is implemented efficiently using the Altera CIC Compiler MegaCore function.
- Altera's FIR Compiler is configured to have an inverse sinc frequency response to compensate CIC filter droop.
- A MATLAB script designing CIC compensating filter is provided for your reference. The script uses the frequency sampling method to design a FIR filter that has an inverse sinc frequency response. The overall system response is plotted for you to verify key system specifications such as the pass-band ripple and stop-band attenuation.
- Multiple input data sources are supported. For wireless and wireline applications, input data can be viewed as time division multiplexed. For other applications, data sources can be viewed as interleaved.
- Altera's Packet Format Converter is included to properly de-interleave multiple data sources for display.
- Altera's Avalon® Streaming Interface (ST) transfers packet data from multiple data sources between cores. For more information about Avalon-ST, please refer to the Avalon Interface Specifications (PDF).
Files
Download the files used in this example:
- Download DDC Example Design File (Version 71)
- Download DDC Example README File (Version 71)
- Download DDC Example Design File (Version 61)
- Download DDC Example README File (Version 61)
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- TDMDDC.mdl - DSP Builder design file
- ciccomp.m - MATLAB script for designing an inverse sinc CIC compensation filter
- cic.vhd - wrapper file to generate the Altera CIC Compiler IP core
- fir.vhd - wrapper file to generate the Altera FIR Compiler IP core
- fdcoeffR4N8M1L110.txt - pre-generated compensating FIR filter coefficients
Parameters
Figure 2 shows the top-level diagram of the CIC and compensation FIR design example in DSP Builder.
Figure 2. CIC and Compensation FIR Design Example in DSP Builder
Table 1 shows the overall frequency response specifications. Select parameters for CIC and FIR filters (see Tables 2 and 3) based on the frequency response requirement.
| Table 1. WiMAX DDC Example Total Spectrum Requirement | |
| Parameters | Value |
|---|---|
| Input Sampling Frequency | 91.392 MHz |
| Output Sampling Frequency | 11.424 MHz |
| Pass-Band Edge | 4.75 MHz |
| Pass-Band Ripple | < 0.05 dB |
| Stop-Band Attenuation | > 90 dB |
| Table 2. Parameters for CIC Filter | |||
| CIC Parameters | Value | ||
|---|---|---|---|
| Filter Type | Decimation | ||
| Number of Stages | 8 | ||
| Rate Change Factor | 4 | ||
| Differential Delay | 1 | ||
| Number of Interfaces | 1 | ||
| Number of Channels Per Interface | 2 | ||
| Input Data Width | 8 | ||
| Output Data Width | 16 | ||
| Hogenauer Pruning | On | ||
| Output Rounding | Convergent | ||
| Table 3. Parameters for FIR Filter | |||
| FIR Parameters | Value | ||
|---|---|---|---|
| Rate Specification | Decimation by 2 | ||
| Input Channels | 2 | ||
| Input Bitwidth | Signed binary 16 | ||
| Output Bitwidth | Full resolution | ||
| Coefficient Scaling | None | ||
| Device Family | Stratix® II | ||
| Structure | MCV | ||
| Pipeline Level | 2 | ||
| Clocks per Output Data | 2 | ||
| Data Storage | M4K | ||
| Coefficient Storage | M512 | ||
| Multiplier | DSP blocks | ||
| Coefficients Input | From file | ||
Related Links
- DSP Builder
- DSP Builder User Guide (PDF)
- DSP Builder Reference Manual (PDF)
- WiMAX DUC DDC Reference Design Webpage
- AN 421: Accelerating WiMAX DUC & DDC System Design (PDF)
- CIC Compiler User Guide (PDF)
- FIR Compiler User Guide (PDF)
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
