BER Performance Measurement of Viterbi Decoder
The design example describes the measurement of bit error rate (BER) for the Altera® Viterbi decoder. The design includes the communication channel with a transmit and receive block. The Viterbi decoder is implemented using a combination of the DSP Builder blocks and the Altera Viterbi Compiler IP MegaCore® while the rest of the system is implemented using Simulink blocks. There are two versions of the design: the first uses the Viterbi decoder simulation model generated by the IP Toolbench, and the other uses the hardware in the loop (HIL) feature to accelerate the simulation in Simulink.
The transmitter block consists of components from the communications blockset including the Viterbi encoder, puncture, and BPSK modulator blocks. The channel is modeled using the AWGN block where the user controls the noise level. The receiver block consists of components including the quantization block which maps the channel output to the range dictated by the number of soft bits specified in the Viterbi decoder to implement soft decision decoding. This is followed by the ‘Insert Zero’ block to reinsert null symbols based on the same deterministic puncturing pattern used in the transmitter. Finally, the de-punctured data stream and the erasure indicator (based on puncturing pattern) are recombined, feeding into the Viterbi decoder. The BER calculation block compares the output of the Viterbi decoder with a delayed version of the source data which is generated by a random generator.
Download the files used in this example:
Files in the zip download include:
- Viterbi_BER.mdl—DSP Builder design file implementing the logic to measure the bit error rate (BER) performance of the Viterbi decoder.
- Viterbi_BER_HIL.mdl—DSP Builder design file implementing the same functionality as the design above with the exception of replacing the Viterbi decoder block with a HIL block implemented in actual hardware to speed up simulation.
- init.m—MATLAB script to initialize the noise level in the channel (Eb/No), number of soft bits, traceback length, and the puncturing pattern.
- Viterbi.vhd—VHDL wrapper file for the Viterbi decoder IP generated by IPToolbench.
- Viterbi_BER.ber—BERTool session to analyze the BER performance based on the HIL design
Figure 1 shows the top-level diagram of the BER measurement of Viterbi decoder design example in DSP Builder.
Figure 1. BER Measurement of Viterbi Decoder Top-Level Diagram
View full size
Table 1 lists the ports and gives a description for each.
| Table 1. BER Measurement of Viterbi Decoder Port Listing |
| Port Name |
Type |
Description |
Sample_1[n_bits-1:0]
Sample_2[n_bits-1:0] |
Input |
Parallel data input to the Viterbi decoder, N*n_bits wide,
where N = encoded bits =2, and n_bits = number of soft bits = 3 |
sclrp |
Input |
System reset (implicit) |
clock |
Input |
System clock (implicit) |
Pattern_CA
Pattern_CB |
Input |
Indicates the puncturing pattern for the two symbol streams (N = 2) |
Decoded_bit |
Output |
Decoded output from the Viterbi decoder |
Related Links
For more information on related features used in this design example in your project, go to:
|
Literature
> 
