Deinterlacer Using Weave Mode
This design example shows you how to convert interlaced video into a non-interlaced format in DSP Builder. Interlaced video is composed of a sequence of fields and must be converted to a sequence of frames before display in certain applications.
The Altera® Deinterlacer MegaCore® function supports two deinterlacing methods: bob and weave. In this example with weave deinterlacing, the Deinterlacer MegaCore function stitches the consecutive fields together into a frame. Weave deinterlacer works well when changes are minimal between two adjacent frames. When changes are visible, the pixels in one frame do not line up with the pixels in the other, resulting in jagged vertical edges, commonly known as the "mouse teeth" artifact.
The model consists of an image stream source block, a deinterlacing_weave block, an external RAM block, and an image stream sink block. The image stream source block reads the input binary file and feeds the data stream to the deinterlacing_weave block. The external RAM block stores the previous field's data and writes back to the deinterlacing_weave block to combine with the current field's data. The image stream sink block writes the deinterlaced data stream to an output binary file. The package also includes the utility to convert an avi video file format to and from a binary file format.
Download the files used in this example:
Files in the zip download include:
- example.mdl - DSP Builder design file
- deinterlacer_weave.vhd - Wrapper file to generate the Deinterlacer intellectual property (IP) MegaCore function
- avi-is-avi.exe - DOS executable to convert an avi file to and from a binary file (also includes some necessary .dll files)
Figure 1 shows the top-level diagram of the Deinterlacer MegaCore function using the weave mode design example in DSP Builder.
Figure 1. Deinterlacer Using Weave Mode Design Example
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Table 1 lists the ports and gives a description for each.
| Table 1. Deinterlacer Using Weave Mode Port Listing |
| Port Name |
Type |
Description |
din_data[7:0] |
Input |
Data input bus |
din_valid |
Input |
Data valid signal that indicates the validity of the input data signals |
dout_ready |
Input |
Data output ready signal |
reset |
Input |
Reset signal |
read_master_av_readdata[63:0] |
Input |
Avalon® read data bus |
read_master_av_readdatavalid |
Input |
Avalon read data valid signal |
read_master_av_waitrequest |
Input |
Avalon read wait request signal |
| write_master_av_waitrequest |
Input |
Avalon write wait request signal |
din_ready |
Output |
Data input ready signal |
dout_data[7:0] |
Output |
Data output bus |
dout_valid |
Output |
Data valid signal that indicates the validity of the output data signals |
read_master_av_address[31:0] |
Output |
Avalon read address bus |
read_master_av_read |
Output |
Avalon read signal |
write_master_av_address[31:0] |
Output |
Avalon write address bus |
write_master_av_write |
Output |
Avalon write signal |
write_master_av_writedata[63:0] |
Output |
Avalon write data bus |
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