Table 1 contains bus and I/O design examples for use in designs for Altera® devices.
| Table 1. Bus and I/O Design Examples | |
| Function | Design Entry Method |
|---|---|
| High-Speed Differential I/O Capability | Verilog HDL |
Examples for altpll_reconfig Megafunction User Guide  |
Quartus® II Software |
| Examples for altremote_update Megafunction User Guide |
Quartus II Software |
| Examples for altpll Megafunction User Guide | Quartus II Software |
| Creating Differential Pin Pair |
Verilog HDL |
| Tri-State Instantiation | Verilog HDL |
| Bidirectional Bus | VHDL |
| Bidirectional Pin | Verilog HDL |
| Legacy Examples | |
Parameterized Tri-State Bus (lpm_bustri) |
AHDL |
| Tri-State Buses Connected to a Bidirectional Bus | AHDL |
| Tri-State Buses Converted to a Multiplexer | AHDL |
| Tri-State Buses in Altera Devices | MAX+PLUS® II Graphic Editor VHDL |
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
