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Home > Support > Design Examples > Bus & I/O Print This Page Subscribe to Email Bus & I/O Design Examples Table 1 contains bus and I/O design examples for use in designs for Altera® devices. Table 1. Bus & I/O Design Examples Function Design Entry Method High-Speed Differential I/O Capability Examples for altpll_reconfig Megafunction User Guide Examples for altremote_update Megafunction User Guide Examples for altpll Megafunction User Guide Tri-State Instantiation Bidirectional Bus Bidirectional Pin Legacy Examples Parameterized Tri-State Bus (lpm_bustri) Tri-State Buses Connected to a Bidirectional Bus Tri-State Buses Converted to a Multiplexer Tri-State Buses in Altera Devices The following icons indicate the entry method(s) used in each example:  Altera hardware description language (AHDL)  VHDL  MAX+PLUS® II graphic editor  Verilog HDL  Tcl  Quartus® II Rate This Page

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