| FPGA Family |
Configuration | Usage | Quartus® II Software Version |
Design Entry Method | Board | |
|---|---|---|---|---|---|---|
| DDR3 SDRAM | ||||||
| Arria® II GX | 300 MHz High-Performance Controller II, AFI, ALTMEMPHY-based, 16-bit, half rate |
Timing closed Walkthrough for the Using DDR, DDR2, and DDR3 SDRAM in Arria II GX Devices chapter in Volume 6, Section 1 of the External Memory Handbook |
9.1 | Verilog HDL | None | |
| Stratix® III | 533 MHz High-Performance Controller II, AFI, ALTMEMPHY-based, x72-bit UDIMM, half rate |
Timing closed and hardware verified Walkthrough for the Using DDR3 SDRAM in Stratix III and Stratix IV Devices chapter in Volume 6, Section 1 of the External Memory Handbook |
9.1 | Verilog HDL | Internal Board | |
| Stratix IV | 400 MHz High-Performance Controller II, AFI, ALTMEMPHY-based x72-bit UDIMM, half rate
|
Timing closed and hardware verified Walkthrough for the Using DDR3 SDRAM in Stratix III and Stratix IV Devices chapter in Volume 6, Section 1 of the External Memory Handbook |
9.1 | Verilog HDL | Development Kit | |
| 400 MHz Three ALTMEMPHY-based controllers (two x16 and one x32) on top edge, half rate |
Timing-closed template Three controllers on one side of the FPGA with delay-locked loop/phase-locked loop (DLL/PLL) sharing |
8.1 | VHDL | None | ||
| 400 MHz Four ALTMEMPHY-based controllers (two on top and two at the bottom, x72) |
Timing-closed template Four controllers on the top and bottom sides |
8.0 SP1 | Verilog HDL | None | ||
| DDR2 SDRAM | ||||||
| Arria II GX | 267 MHz High-Performance Controller II, AFI, ALTMEMPHY-based x64-bit, half rate |
Timing closed and hardware verified Walkthrough for the Using DDR, DDR2, and DDR3 SDRAM in Arria II GX Devices chapter in Volume 6, Section 1 of the External Memory Handbook |
9.1 | Verilog HDL | Development Kit | |
| Cyclone® III | 167 MHz High-Performance Controller, non-AFI, ALTMEMPHY-based x36-bit devices, half rate |
Timing closed Walkthrough for the Using DDR and DDR2 SDRAM in Cyclone III Devices chapter in Volume 6, Section 1 of the External Memory Handbook |
7.2 | Verilog HDL | Development Kit | |
| 150 MHz High-Performance Controller II, AFI, ALTMEMPHY-based x8 device, half rate |
SOPC Builder-integrated example, timing closed and hardware verified Walkthrough for the Using High-Performance Controller with SOPC Builder chapter in Volume 6, Section 1 of the External Memory Handbook |
9.1 | Verilog HDL | Development Kit | ||
| Stratix II | 267 MHz Three ALTMEMPHY-based controllers (one x72 DIMM and two x8 components), half rate |
Multicontroller example design Walkthrough for AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF) |
7.2 | Verilog HDL | None | |
200MHz
High-Performance Controller II, AFI, ALTMEMPHY-based, 8-bit, full rate |
Simulation verified Walkthrough for the Using High-Performance Controller II with Native Interface Design chapter in Volume 6, Section 1 of the External Memory Handbook |
9.1
|
|
None
|
||
| 333 MHz ALTMEMPHY-based x72 devices, half rate |
ALTMEMPHY timing-closed template Walkthrough for AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF) |
7.2 | Verilog HDL | PCI Express Development Kit | ||
| 267 MHz Legacy-based PHY x72 devices, full rate |
Legacy PHY timing-closed template Walkthrough for AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF) |
7.2 | Verilog HDL | PCI Express Development Kit Board | ||
| Stratix III |
400 MHz High-Performance Controller, AFI, ALTMEMPHY-based x72-bit DIMM |
Timing closed and hardware verified Walkthrough for the Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices chapter in Volume 6, Section 1 of the External Memory Handbook |
9.0 | Verilog HDL | Development Kit | |
| 333 MHz ALTMEMPHY-based, x64 single-rank SODIMM, half rate |
Timing-closed template Featuring pin planner board trace model assignments |
8.0 SP1 | Verilog HDL | None | ||
| QDR II+ SRAM | ||||||
| Stratix III | 400 MHz ALTMEMPHY-based PHY x18, half rate |
Timing-closed template |
8.0 | Verilog HDL | Development Kit | |
| 400 MHz UniPHY-based PHY and controller, AFI, 18-bit, half rate |
Timing closed and hardware verified Walkthrough for the Using QDR II and QDR II+ SRAM in Arria II, Stratix III, and Stratix IV Devices chapter in Volume 6, Section 2 of the External Memory Handbook |
9.1 SP1 | Verilog HDL | Development Kit | ||
| Stratix IV | 350 MHz UniPHY-based PHY and controller, AFI, 18-bit, half rate |
Timing closed and hardware verified Walkthrough for the Using QDR II and QDR II+ SRAM in Arria II, Stratix III, and Stratix IV Devices chapter in Volume 6, Section 2 of the External Memory Handbook |
9.1 SP1 | Verilog HDL | Audio Video Development Kit | |
| RLDRAM II | ||||||
| Stratix III | 400 MHz UniPHY-based PHY and controller, AFI, 36-bit, half rate |
Timing closed and hardware verified Walkthrough for the Using RLDRAM II in Stratix III and Stratix IV Devices chapter in Volume 6, Section 2 of the External Memory Handbook |
9.1 SP1 | Verilog HDL | Internal Board | |
| Stratix IV | 400 MHz UniPHY-based PHY and controller, AFI, 36-bit, half rate |
Timing closed and hardware verified Walkthrough for the Using RLDRAM II in Stratix III and Stratix IV Devices chapter in Volume 6, Section 2 of the External Memory Handbook |
9.1 SP1 | Verilog HDL | Development Kit | |
