Design Examples

Altera® FPGAs provide abundant on-chip internal SRAM memory resources, but system bandwidth requirements often necessitate the use of large, fast off-chip memory devices. Memory controller intellectual property (IP) solutions from Altera and our partners include licensable cores, reference designs and design examples. All are hardware-tested drop-in design blocks that greatly simplify the local interface to complex memory devices.

Visit our External Memory section to learn more about interfacing with external memory.

Design Examples	Device Targeted	Development Kits Supported	SOPC Builder Ready	Qsys Compliant	Quartus II Version
CF+ Interface MAX II CPLDs: AN 492 (PDF)	MAX II	-	-	-	10.0
DDR2: 8-Bit Wide DDR2 ALTMEMPHY-Based SOPC Builder Integrated in Cyclone III FPGAs	Cyclone III	Cyclone III FPGA Development Kit		-	9.1
DDR2: Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA	Arria II GX	Arria II GX FPGA Development Kit	-	-	9.1
DDR3: 8-Bit Wide DDR3 UniPHY-Based QSYS Integrated in Stratix IV FPGAs (Verilog)	Stratix IV GX	Audio Video Development Kit, Stratix IV GX Edition	-		11.0
DDR3: Interfacing a 300-MHz DDR3 SDRAM with an Arria II GX FPGA	Arria II GX	Arria II GX FPGA Development Kit	-	-	9.1
DDR3: Interfacing with a 64-bit DDR3 SDRAM UDIMM interface at 400 MHz in a Stratix IV FPGA	Stratix IV E	Stratix IV GX FPGA Development Kit	-	-	9.1
Implementing Multiple Memory Interface using UniPHY in a Stratix IV FPGA (Verilog)	Stratix IV E	Stratix IV E FPGA Development Kit	-	-	10.1
Implementing Multiple Memory Interface Using UniPHY in a Stratix V FPGA	Stratix V GX	-	-	-	11.0
Interfacing with a 64-bit DDR3 SDRAM UniPHY Interface at 533 MHz in a Stratix IV FPGA	Stratix IV GX	Stratix IV GX FPGA Development Kit	-	-	11.0
Mobile SDRAM Interface Using MAX II CPLDs: AN 499 (PDF)	MAX II	-	-	-	-
NAND Flash Memory Interface with MAX II CPLDs: AN 500 (PDF)	MAX II	-	-	-	-
QDRII: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA	Stratix IV E	Stratix IV GX FPGA Development Kit	-	-	11.0
RLDRAMII: Interfacing 533-MHz RLDRAM II in a Stratix IV FPGA	Stratix IV E	Stratix IV E Development Kit	-	-	11.0
Using the Parallel Flash Loader with the Quartus II Software: AN 386 (PDF)	MAX II	-	-	-	10.0
Using the UFM in MAX II Devices: AN 489 (PDF)	MAX II	-	-	-	-

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.