Design Examples

Simulation

Altera provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon® Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.

Design Examples	Device Targeted	Development Kits Supported	SOPC Builder Ready	Qsys Compliant	Quartus II Version
Nios II: Avalon Verification IP Suite Design Example	-	-			11.0
Nios II: Debugging with System Console over TCP/IP	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	12.0
Nios II: Simulating Nios II Embedded Processor Designs	Stratix II	Nios II Development Kit, Stratix II	-		11.0

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.