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Home > Support > Design Examples > Logic Print This Page Subscribe to Email Logic Design Examples Table 1 contains logic design examples for use in designs for Altera® devices. Click on the design entry method icon to see the design example. Table 1. Logic Design Examples Function Design Entry Method 1x64 Shift Register 8x64 Shift Register with Taps Counter with Asynchronous Reset Counter with Synchronous Load Preventing Unintentional Latch Creation Instantiating a DFFE Instantiating a DFF Using lpm_dff Synchronous State Machine Legacy Examples Parameterized Multiplexer (lpm_mux) Comparison Function Using EABs Sequencer (lpm_rom) Linear Feedback Shift Register State Machine Implemented in an EAB The following icons indicate the entry mode(s) used in each example:  Altera hardware description language (AHDL)   VHDL  MAX+PLUS® II Graphic Editor  Verilog hardware description language (HDL)  Tool command language (Tcl)  Quartus® II development tool Rate This Page

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