Logic Design Examples

Table 1 contains logic design examples for use in designs for Altera^® devices. Click on the design entry method icon to see the design example.

Table 1. Logic Design Examples
Function	Design Entry Method
1x64 Shift Register	Verilog HDL
8x64 Shift Register with Taps	Verilog HDL VHDL
Counter with Asynchronous Reset	Verilog HDL
Counter with Synchronous Load	VHDL
Preventing Unintentional Latch Creation	VHDL
Instantiating a DFFE	Verilog HDL VHDL
Instantiating a DFF Using lpm_dff	VHDL
Synchronous State Machine	Verilog HDL
Legacy Examples
Parameterized Multiplexer (lpm_mux)	AHDL MAX+PLUS II Graphic Editor
Comparison Function Using EABs	MAX+PLUS® II Graphic Editor
Sequencer (lpm_rom)	MAX+PLUS II Graphic Editor
Linear Feedback Shift Register	MAX+PLUS II Graphic Editor
State Machine Implemented in an EAB	MAX+PLUS II Graphic Editor

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.