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Home > Support > Design Examples > Memory Print This Page Subscribe to Email Memory Design Examples Table 1 below contains memory design examples for use in designs for Altera® devices. Select the design entry method icon to see the design example. Table 1. Memory Design Examples Function Design Entry Method Dual Clock Synchronous RAM Examples for altufm Megafunction User Guide Single Clock Synchronous RAM Single Clock Synchronous RAM With Asynhcronous Read Address Cycle-Shared Dual-Port RAM (csdpram) Parameterized RAM With Separate Input & Output Ports (lpm_ram_dq) Single-Match Content-Addressable Memory (CAM) (altcam) Quad Data Rate (QDR) SRAM Controller Fast-Multiple Match CAM (altcam) Multiple-Match CAM Zero-Bus Turnaround (ZBT) SRAM Controller Legacy Examples Cycle-Shared Dual-Port RAM (csdpram) Cycle-Shared First-In First-Out (FIFO) (csfifo) Parameterized RAM With Separate Input & Output Ports (lpm_ram_dq) The following icons indicate the entry mode(s) used in each example:  Altera hardware description language (AHDL)  VHDL  MAX+PLUS® II Graphic Editor  Verilog hardware description language (HDL)  Tool command language (Tcl)  Quartus® II development tool  Rate This Page

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