Table 1 contains memory design examples for use in designs for Altera® devices. Select the design entry method icon to see the design example.
For more examples of Verilog and VHDL designs for Altera RAM blocks, refer to the Recommended HDL Coding Styles (PDF) chapter in the Quartus® II Handbook.
| Table 1. Memory Design Examples | |
| Function | Design Entry Method |
|---|---|
| Dual Clock Synchronous RAM | Verilog HDL VHDL |
| Examples for altufm Megafunction User Guide | Quartus II Software |
| Single Clock Synchronous RAM | Verilog HDL VHDL |
| Single Clock Synchronous RAM with Asynchronous Read Address | VHDL |
Cycle-Shared Dual-Port RAM (csdpram) |
VHDL |
Parameterized RAM with Separate Input and Output Ports (lpm_ram_dq) |
Verilog HDL |
Single-Match Content-Addressable Memory (CAM) (altcam) |
Quartus II Software |
Fast-Multiple Match CAM (altcam) |
Quartus II Software |
| Multiple-Match CAM | Quartus II Software |
| Legacy Examples | |
Cycle-Shared Dual-Port RAM (csdpram) |
AHDL MAX+PLUS® II Graphic Editor |
Cycle-Shared FIFO (csfifo) |
AHDL MAX+PLUS II Graphic Editor |
Parameterized RAM with Separate Input and Output Ports (lpm_ram_dq) |
AHDL MAX+PLUS II Graphic Editor |
Design examples disclaimer
These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
