The altlvds megafunction allows the user to instantiate an external phase-locked loop (PLL) when using Stratix® II devices. This external PLL will be a fast PLL set up in LVDS mode. This option gives you more control over the PLL settings and gives you access to PLL options that are not accessible when instantiating the serializer/deserializer (SERDES) circuitry using the altlvds MegaWizard® Plug-In.
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
This project is a complete design illustrating the connections between the external fast PLL and the altlvds transmit and receive megafunctions. Figure 1 shows the top-level design file. A complete vector waveform input file (.vwf) demonstrating the functionality of the circuit is also included in the design files.
Figure 1. siilvds_ext_pll.bdf
When using a fast PLL in conjunction with the altlvds megafunction, you must turn on the Set Up PLL In LVDS Mode option in the general section of the altpll MegaWizard Plug-In. You must also enter the data rate and input clock frequency. Clock output ports c0 and c1 can be used in this mode for the SERDES clocks. You must turn on the Create sclkout0/enable0 outputs if using c0, and you must turn on the Create sclkout1/enable1 outputs if you are using c1, as shown in Figure 2. The sclkout port will be the high-speed serial clock and must be connected to the rx_inclock or tx_inclock port of the altlvds function. The corresponding enable outputs must be connected to the rx_enable or tx_enable input port of the altlvds megafunction. These enable ports are turned on automatically in the altlvds MegaWizard Plug-In when you turn on the Use External PLL option.
Figure 2. altpll MegaWizard Plug-In – Clock c0
The c0 and/or c1 clock parameters are used for the slow-speed clocks in the SERDES circuitry. In the example, c0 is used for the receiver block, and c1 is used for the transmit block. A synchronization register needs to be added after the altlvds receive megafunction for each channel and needs to be clocked using the c0 port (also referred to as rx_outclk). A synchronization register also needs to be added for each channel before the transmit function and needs to be clocked using the c1 port (also referred to as tx_coreclk).
When you use the External PLL option in the altlvds megafunction, all of the control regarding data rates, clock frequencies, and clock alignment moves from the altlvds megafunction to the altpll megafunction. You can control the high-speed clock phase shifts by turning on Enable sclkout Phase Shift edit.
The altlvds transmit megafunction does not have an output port for the tx_outclk in Quartus II version 4.2. Although this will be fixed in a future release, you can use the example shown here to create a separate transmit channel which will create the tx_outclk. You can set up your outclk divide factor by adjusting the VCC and GND connections on the input bus. This example sets up a divide by 2 clock.
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