PLL & Clocking Design Examples

Altera offers users phase-locked loop (PLL) design examples for use in designs for Altera^® devices using Quartus^® II software. Table 1 below lists PLL design examples with links to view their descriptions and to download the examples.

*Table 1. PLL Design Examples*
Description	Links to Download Designs
AN 367: Implementing PLL Reconfiguration in Stratix^® II Devices (PDF)	Example 1: altpll_reconfig Design With the Memory Initialization File (MIF)
	Example 2: altpll_reconfig Design With Write Parameters
	Example 3: altpll_reconfig Design for Phase Shift Stepping
AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (PDF)	Example 1: Shift Register in Logic Elements (LEs)
	Example 2: altpll_reconfig Design With the MIF
	Example 3: altpll_reconfig Design
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices (PDF)	Clock Switchover Example Design
Using altlvds With the External PLL Option in Stratix II Devices	Design Example for Using altlvds With the External PLL Option in Stratix II Devices
Using altlvds With the External PLL Option in Stratix III Devices	Design Example for Using altlvds With the External PLL Option in Stratix III Devices

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

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