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Home > Support > Design Examples > PLL & Clocking Print This Page Subscribe to Email PLL & Clocking Design Examples Altera offers users phase-locked loop (PLL) design examples for use in designs for Altera® devices using Quartus® II software. Table 1 below lists PLL design examples with links to view their descriptions and to download the examples. Table 1. PLL Design Examples Description Links to Download Designs AN 367: Implementing PLL Reconfiguration in Stratix® II Devices (version 1.0, Dec 2004, 665 KB) Example 1: altpll_reconfig Design With the Memory Initialization File (MIF) (175 KB) Example 2: altpll_reconfig Design With Write Parameters (181 KB) Example 3: altpll_reconfig Design for Phase Shift Stepping (182 KB) AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (version 1.0, Jan 2003, 358 KB) Example 1: Shift Register in Logic Elements (LEs) (276 KB) Example 2: altpll_reconfig Design With the MIF (181 KB) Example 3: altpll_reconfig Design (181 KB) AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices (version 1.0, Jan 2004, 273 KB) Clock Switchover Example Design (233 KB) Using altlvds With the External PLL Option in Stratix II Devices (94 KB) Using altlvds With the External PLL Option Design Example (81 KB)   Rate This Page

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