FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Using Tri-State Buses for Bidirectional Communication

Home > Support > Design Examples > Graphic Editor > Using Tri-State Buses for Bidirectional Communication

Tri-State Buses in Altera Devices

Altera devices do not have internal tri-state buses. Consequently, logic inside a device cannot communicate via bidirectional lines. However, MAX+PLUS® II can emulate tri-state buses by using multiplexers and by routing the bidirectional line outside of the device and then back in through another pin.

This example shows the following two methods for using tri-state buses in Altera Devices:

  1. Using Tri-States Buses to Multiplex Signals Together
  2. Using Tri-States Buses for Bidirectional Communication

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.


Using Tri-State Buses to Multiplex Signals Together

When tri-state buses are used to multiplex signals, MAX+PLUS II will convert the logic to a combinatorial multiplexer. The method shown in Figure 1 cannot be performed inside an Altera device because each tri-state buffer can only feed one pin. This design will be converted automatically by MAX+PLUS II into a multiplexer that feeds a single tri-state buffer (see Figure 2). MAX+PLUS II can perform this tri-state emulation automatically for both Graphic Editor and Altera Hardware Description Language (AHDL) designs. Refer to Graphic Editor: Tri-State Buses Converted to a Multiplexer and AHDL: Tri-State Buses Converted to a Multiplexer for more information.


Figure 1. Internally Connected Tri-States

Figure 1

Figure 2. Multiplexer

Figure 2

If the tri-state buffers do not feed a pin, then no tri-state buffer is available after the multiplexer (see Figure 3).


Figure 3. Internally Connected Tri-States Without I/O Pins

Figure 3

If the design in Figure 3 is entered using AHDL or Graphic Editor, MAX+PLUS II will automatically convert it into the design in Figure 4. If the design in Figure 3 is entered using VHDL, you will need to manually create a multiplexer.


Figure 4. Multiplexer Without I/O Pins

Figure 4

In Figure 5, device 1 communicates with device 2 via bidirectional lines. This can be performed inside an Altera PLD since there is a tri-state buffer available at each I/O pin.


Figure 5. Bidirectional Communication Between Two Altera Devices

Figure 5

In Figure 6, logic A communicates with logic B via bidirectional lines inside the device. Since tri-states do not feed into the device, this function cannot be implemented in this manner. To overcome this, you can rout this bidirectional line outside of the device (see Figure 7), which uses the tri-states present at the I/O pins, or you can convert the tri-state bus into a multiplexer (see Figure 8). MAX+PLUS II can convert internal tri-state buses into multiplexeres independently for both AHDL and Graphic Editor designs. Refer to Graphic Editor: Tri-State Buses Converted to a Multiplexer and AHDL: Tri-State Buses Converted to a Multiplexer.


Figure 6. Bidirectional Lines Inside the Device

Figure 6

Figure 7. Bidirectional Line Routed Outside of the Device

Figure 7

Figure 8. Multiplexer Controlling Feedback Lines

Figure 8

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

Rate This Page


  • Products
    • MAX/MAX II
    • Stratix/Stratix GX
    • Nios II
  • Functionality
    • Arithmetic
    • External Memory Interfaces
    • On-Chip Memory
    • Bus & I/O Functions
    • Logic
    • Interfaces & Peripherals
    • DSP
    • Communications
    • PLL & Clocking
  • Design Entry
    • Quartus II
    • Tcl
    • VHDL
    • Verilog HDL
    • C Code
    • DSP Builder
    • TimeQuest
    • On-Chip Debugging
      • SignalTap II
  • Simulation Tools
    • Mentor Graphics ModelSim
    • Cadence NCsim
    • Synopsys VCS
  • Legacy Examples
    • Graphic Editor
    • AHDL
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates