Altera offers design examples involving interfaces and peripherals for use in designs for Altera® devices. Select the Design Entry Method icon to see the design example.
| Table 1. Interfaces and Peripherals Design Examples – Functions and Design Entry Methods | |
| Function | Design Entry Method |
| RapidIO: Maintenance Master to System Maintenance Slave Bridge | Verilog HDL |
PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore® Functions  |
VHDL and Verilog HDL |
| PCI Target Memory Examples for PCI MegaCore functions |
VHDL and Verilog HDL |
| PCI Master Memory Examples for pci_mt32 MegaCore Function |
VHDL and Verilog HDL |
Additional examples are available on the Interfaces & Peripherals Reference Designs page.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
