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Home > Support > Design Examples > MAX/MAX II Print This Page Subscribe to Email MAX II and MAX CPLD Design Examples The examples shown in Tables 1 through 5 demonstrate various features of the Altera® MAX® II and MAX low-power CPLD families using Quartus® II or MAX+PLUS® II software. For more information about the different design entry methods, refer to the help files in Quartus II or MAX+PLUS II software. These design examples are intended only for Altera devices. The examples are provided on an "as-is" basis and come with no warranties. Pin/Port Expansion or Bridging Interface or Control Power Management and Miscellaneous Logic Other MAX II CPLD Design Examples Design Examples for Quartus II or MAX+PLUS II Software Each design example in Tables 1 through 3 includes the following: Source code in Verilog Testbench in Verilog Quartus II Web Edition software version version 6.0 project files and program files for the MDN B2 or MDN B3 demonstration board (the logic element (LE) and I/O resources shown in Tables 1 through 3 are derived from design compilations using Quartus II software version 7.2)  ModelSim® 6.1d Web Edition software project file with testbench, wave image files Simulation file not included for large simulations Documentation Table 1. MAX II, MAX IIG, and MAX IIZ Pin/Port Expansion and Bridging Design Examples Design Name Description  Design Files AN 494: GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs (PDF) General-purpose I/O expansion using I2C interface (Resource utilization: 18 I/Os and ~61 LEs) Download (ZIP) AN 484: SMBus for GPIO Pin Expansion in MAX II CPLDs (PDF) General-purpose I/O expansion using SMBus interface (Resource utilization: 18 I/Os and ~87 LEs) Download (ZIP) AN 487: SPI to I2S Using MAX II CPLDs (PDF) Bridge between devices that have SPI interface and I2S bus (Resource utilization: 8 I/Os and ~286 LEs) Download (ZIP) AN 486: SPI to I2C Using MAX II CPLDs (PDF)  Controls data flow to audio devices on an I2C bus through SPI interface (Resource utilization: 6 I/Os and ~102 LEs) Download (ZIP) Table 2. MAX II, MAX IIG, and MAX IIZ Interface or Control Design Examples Design Name Description Design Files AN 509: Multiplexing SDIO Devices using MAX II CPLDs (PDF) Implementing an SDIO multiplexer through the I2C interface (Resource utilization: 9 I/Os & ~34 LEs) Download (ZIP) (1) AN 492: CF+ Interface MAX II CPLDs (PDF) Implements a compact flash interface (Resource utilization: 45 I/Os and ~119 LEs) Download (ZIP) AN 495: IDE/ATA Controller Using MAX II CPLDs (PDF) Implements an IDE controller (Resource utilization: 89 I/Os and ~134 LEs) Download (ZIP) AN 497: LCD Controller Using MAX II CPLDs (PDF) Implements an LCD controller (example is Optrex 16 x 2 dot matrix LCD module, and can be extended to other LCD modules) (Resource utilization: 46 I/Os and ~211 LEs) Download (ZIP) AN 499: Mobile SDRAM Interface Using MAX II CPLDs (PDF) Implements interface to mobile DRAM devices (Resource utilization: 85 I/Os and ~138 LEs) Download (ZIP) AN 500: NAND Flash Memory Interface with MAX II CPLDs (PDF) Implements interface to NAND flash devices (Resource utilization: 13 I/Os and ~11 LEs) Download (ZIP) AN 502: Implementing an SMBus Controller MAX II CPLDs (PDF) Implements an SMBus controller (Resource utilization: 24 I/Os and ~896 LEs) Download (ZIP) AN 485: Serial Peripheral Interface (SPI) Master in MAX II CPLDs (PDF) Implements SPI master (Resource utilization: 25 I/Os and ~68 LEs) Download (ZIP) AN 488: Stepper Motor Controller Using MAX II CPLDs (PDF) Implements a stepper motor controller (Resource utilization: 8 I/Os and ~59 LEs) Download (ZIP) AN 489: Using the UFM in MAX II Devices (PDF) Accesses MAX II user flash memory through an I2C interface (Resource utilization: 4 I/Os and ~124 LEs) Download (ZIP) Note: The ModelSim and testbench files are not included in this design. Table 3.  MAX II, MAX IIG, and MAX IIZ Power Management and Miscellaneous Logic Design Examples Design Name Description Design Files AN 491: Auto Start Using MAX II CPLDs (PDF) Saves power by automatically starting and stopping the MAX II dynamic operation (Resource utilization: 8 I/Os and ~45 LEs) Download (ZIP) AN 493: I2C Battery Gauge Interface Using MAX II CPLDs (PDF) Remotely monitors the status of a battery gauge using I2C interface (Resource utilization: 34 I/Os and ~107 LEs) Download (ZIP) AN 496: Using the Internal Oscillator in MAX II CPLDs (PDF) Uses the oscillator in the MAX II user flash memory block as a clock source (Resource utilization: 17 I/Os and ~41 LEs) Download (ZIP) AN 498: LED Blink Using Auto Stop and Auto Start in MAX II CPLDs (PDF) Blink LEDs using auto start and auto stop functions (Resource utilization: 3 I/Os and ~20 LEs) Download (ZIP) AN 501: Pulse Width Modulator Using MAX II CPLDs (PDF) Implements pulse-width modulation using the MAX II user flash memory block oscillator (Resource utilization: 8 I/Os and ~52 LEs) Download (ZIP) AN 490: MAX II CPLDs as Voltage Level Shifters (PDF) Implements the voltage level shifting required in a mixed-voltage environment (Resource utilization: 16 I/Os and 0 LEs) Download (ZIP) Table 4. Other MAX II CPLD Design Examples Design Name Description Documents Programming CFI Flash and Configuring FPGAs Uses the MAX II parallel flash loader to program CFI flash devices or configure FPGAs AN 386: Using the Parallel Flash Loader with the Quartus II Software (PDF) LED Driver Implements LED drivers in MAX II CPLDs AN 286: Implementing LED Drivers in MAX & MAX II Devices (PDF) Power Management Controller Uses a MAX II CPLD for power management in portable applications AN 422: Power Management in Portable Systems Using MAX II CPLDs (PDF) The MAX II and MAX CPLD design examples in Table 5 are grouped by functionality. Click the design entry method to see the design example. Table 5. MAX II and MAX CPLD Design Examples for Quartus II or MAX+PLUS II Software Buses and  I/O Functions Design Entry Method Power-Down Design Graphic Editor Analog Keyboard Encoder Graphic Editor Microcontroller I/O Expander Verilog HDL 16 x 16 Crosspoint Switch Verilog HDL Customized 4-Port Crosspoint Switch Verilog HDL Parameterized Tri-State Bus (lpm_bustri) AHDL  Graphic Editor Tri-State Buses Connected to a Bidirectional Bus AHDL  Graphic Editor Tri-State Buses Converted to a Multiplexer AHDL  Graphic Editor  Tri-State Buses in Altera Devices Graphic Editor  VHDL Tri-State Instantiation Verilog HDL Bidirectional Bus VHDL Bidirectional Pin Verilog HDL Logic Design Entry Method Parameterized Multiplexer (lpm_mux) AHDL  Graphic Editor Instantiating a DFFE Verilog HDL  VHDL Instantiating a DFF using (lpm_dff) VHDL Linear Feedback Shift Register Graphic Editor Synchronous State Machine Verilog HDL Arithmetic Functions Design Entry Method Parameterized Counter (lpm_counter) AHDL  Verilog HDL Behavioral Counter Verilog HDL Carry Look-Ahead Adder VHDL Ripple-Carry Adder VHDL Down Counter VHDL Rate This Page

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